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2026-04-01 - 14:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Wed Apr 01, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3342414996158,2cyclictest3915795-21kworker/u16:2+events_unbound11:22:546
3342414996058,2cyclictest4000340-21kworker/u16:4+events_unbound12:23:136
3342414996058,2cyclictest4000340-21kworker/u16:4+events_unbound12:23:136
3342414996058,2cyclictest3940020-21kworker/u16:5+events_unbound11:38:106
3342414995552,2cyclictest3342169-21kworker/u16:2+events_unbound07:47:546
3342414995350,2cyclictest3672725-21kworker/u16:2+events_unbound10:12:586
3342414995250,2cyclictest3966722-21kworker/u16:3+events_unbound11:53:096
3342414995250,2cyclictest3694759-21kworker/u16:0+flush-8:010:48:096
3342414995250,2cyclictest3672725-21kworker/u16:2+events_unbound09:43:086
3342414995250,2cyclictest3587652-21kworker/u16:4+events_unbound09:33:066
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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