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2026-07-23 - 22:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Thu Jul 23, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324188625722,30sleep70-21swapper/707:05:187
324191125343,7sleep50-21swapper/507:05:405
324216724433,8sleep40-21swapper/407:09:164
3242485994338,4cyclictest3782966-21missed_timers11:09:457
3242485994337,5cyclictest3401422-21latency_hist08:29:237
3242485994136,4cyclictest3391719-21latency_hist08:24:227
3242476993937,2cyclictest3882298-21kworker/u16:4+flush-8:012:24:165
3242485993837,0cyclictest0-21swapper/710:46:507
3242485993735,1cyclictest3479204-21diskmemload11:18:017
324197723726,8sleep60-21swapper/607:06:386
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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