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2026-06-17 - 06:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Jun 14, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312075125747,7sleep50-21swapper/507:01:425
312094625444,7sleep40-21swapper/407:04:304
3121333994745,2cyclictest3630335-21kworker/u16:5+flush-8:011:02:275
3121335994240,2cyclictest3856689-21kworker/u16:2+events_unbound12:34:316
3121335994139,2cyclictest3376590-21kworker/u16:1+events_unbound10:02:446
3121333994035,2cyclictest3728603-21kworker/u16:1+flush-8:011:56:175
31207802404,30sleep70-21swapper/707:02:087
3121335993937,2cyclictest3534018-21kworker/u16:1+events_unbound10:43:276
3121335993937,2cyclictest3428267-21kworker/u16:0+events_unbound10:21:006
3121335993937,2cyclictest3376887-21kworker/u16:4+events_unbound11:27:396
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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