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2025-12-14 - 09:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Dec 14, 2025 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8253452427,30sleep70-21swapper/719:04:587
626589400,33rtkit-daemon0-21swapper/619:05:296
834907993731,5cyclictest1062409-21latency_hist21:04:537
83490799370,35cyclictest926180-21latency_hist19:54:537
83446823727,7sleep50-21swapper/519:07:535
834906993331,2cyclictest1335404-21kworker/u16:4+flush-8:023:25:086
834906993331,2cyclictest1043290-21kworker/u16:2+flush-8:021:40:076
83490799320,30cyclictest1315584-21latency_hist23:14:527
83490799320,30cyclictest1315584-21latency_hist23:14:527
834906993230,2cyclictest824604-21kworker/u16:2+flush-8:019:10:036
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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