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2026-08-23 - 08:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Aug 23, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31895812990,0sleep60-21swapper/621:47:526
284585325823,30sleep70-21swapper/719:03:527
284585325823,30sleep70-21swapper/719:03:527
284585124535,7sleep50-21swapper/519:03:505
284585124535,7sleep50-21swapper/519:03:505
34078552440,0sleep73407856-21sh23:20:187
2846399994139,2cyclictest2782481-21kworker/u16:3+flush-8:019:37:254
2846399993836,2cyclictest2908646-21kworker/u16:1+flush-8:020:07:244
2846414993732,4cyclictest3553278-21latency_hist00:22:247
2846412993634,2cyclictest3469039-21kworker/u16:3+events_unbound23:52:586
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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