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2025-12-13 - 00:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Fri Dec 12, 2025 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8303527161,7sleep50-21swapper/503:20:045
83501996663,2cyclictest581198-21kworker/u16:3+flush-8:007:42:136
83497995754,2cyclictest278535-21kworker/u16:0+flush-8:005:27:134
83500995048,2cyclictest369563-21kworker/u16:2+flush-8:006:47:425
8300724838,7sleep40-21swapper/403:19:394
83506994742,4cyclictest399752-21latency_hist05:57:137
83506994540,4cyclictest198183-21latency_hist04:17:147
83497994543,2cyclictest470741-21kworker/u16:3+events_unbound07:02:134
83506994439,4cyclictest490555-21latency_hist06:42:137
83500994240,2cyclictest521055-21kworker/u16:4+events_unbound07:20:295
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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