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2026-10-08 - 04:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Thu Oct 08, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
353906925949,7sleep40-21swapper/419:07:544
353902225242,7sleep50-21swapper/519:07:155
352954724812,30sleep70-21swapper/719:04:047
3539432994643,2cyclictest20644-21kworker/u16:1+events_unbound00:24:185
3539432994341,2cyclictest4030363-21kworker/u16:2+events_unbound23:25:045
3539432994341,2cyclictest4030363-21kworker/u16:2+events_unbound23:09:375
3539432994340,2cyclictest4008054-21kworker/u16:0+events_unbound23:53:455
3539432994240,2cyclictest4008054-21kworker/u16:0+events_unbound00:14:185
3539432994038,2cyclictest4030363-21kworker/u16:2+flush-8:023:44:355
3539432994038,2cyclictest4008054-21kworker/u16:0+events_unbound23:58:055
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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