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2026-08-11 - 06:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Tue Aug 11, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
394445125318,30sleep70-21swapper/719:06:077
394445125318,30sleep70-21swapper/719:06:077
394433025343,7sleep40-21swapper/419:04:274
394433025343,7sleep40-21swapper/419:04:274
394434924939,7sleep50-21swapper/519:04:445
394434924939,7sleep50-21swapper/519:04:445
3944882994844,3cyclictest376480-21kworker/u16:1+flush-8:023:53:105
3944882993935,4cyclictest72894-21kworker/u16:1+flush-8:021:58:115
3944875993937,2cyclictest241304-21kworker/u16:1+events_unbound22:50:054
394440023929,7sleep60-21swapper/619:05:256
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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