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2026-01-11 - 17:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Jan 11, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
255059225847,7sleep40-21swapper/407:04:014
255076825320,29sleep70-21swapper/707:06:297
255086924635,8sleep50-21swapper/507:07:555
2551163994543,2cyclictest2531803-21kworker/u16:4+flush-8:007:58:005
2551163994240,2cyclictest2958656-21kworker/u16:2+events_unbound10:36:305
2551163994139,2cyclictest3217289-21kworker/u16:1+events_unbound12:16:235
2551163994139,2cyclictest3207043-21kworker/u16:0+events_unbound12:02:375
2551163994139,2cyclictest3207043-21kworker/u16:0+events_unbound12:02:375
2551163994139,2cyclictest2936485-21kworker/u16:0+events_unbound11:17:595
2551173994038,1cyclictest2788084-21diskmemload11:34:467
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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