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2025-12-07 - 17:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Dec 07, 2025 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1121423995148,2cyclictest1731019-21kworker/u16:4+flush-8:020:47:456
1121423995148,2cyclictest1629815-21kworker/u16:1+events_unbound19:32:466
1121417995148,2cyclictest1315770-21kworker/u16:5+flush-8:017:12:464
1121423995047,2cyclictest1307683-21kworker/u16:3+flush-8:018:07:476
1121423995045,2cyclictest1713840-21kworker/u16:0+flush-8:020:22:596
112108425028,7sleep60-21swapper/615:22:066
1121417994845,2cyclictest1131148-21kworker/u16:0+flush-8:015:32:314
1121417994745,2cyclictest1091106-21kworker/u16:4+flush-8:015:48:014
1121417994744,2cyclictest1307683-21kworker/u16:3+events_unbound17:17:574
112086524611,30sleep70-21swapper/715:19:027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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