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2026-04-09 - 13:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Thu Apr 09, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
104773425545,7sleep60-21swapper/607:01:316
1048071994946,2cyclictest1038683-21kworker/u16:1+events_unbound09:02:074
104768724838,7sleep50-21swapper/507:00:495
103868024834,9sleep40-21swapper/406:57:114
1048075994745,2cyclictest1488252-21kworker/u16:1+events_unbound10:32:095
1048075994745,2cyclictest1038683-21kworker/u16:1+events_unbound07:24:095
1048075994643,2cyclictest1318249-21kworker/u16:0+events_unbound11:17:255
1048082994539,5cyclictest1166793-21latency_hist08:02:077
1048075994442,2cyclictest1318249-21kworker/u16:0+flush-8:010:52:375
1048075994442,2cyclictest1318249-21kworker/u16:0+flush-8:010:52:375
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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