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2026-04-23 - 02:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Thu Apr 23, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
410695925847,8sleep40-21swapper/419:07:274
40985012413,31sleep70-21swapper/719:04:417
4107399994037,2cyclictest462467-21kworker/u16:1+events_unbound23:59:294
4107403993937,2cyclictest548762-21kworker/u16:3+events_unbound00:29:215
4107403993937,2cyclictest160462-21kworker/u16:1+events_unbound21:37:185
4107408993835,2cyclictest138069-21kworker/u16:3+events_unbound21:04:306
4107403993836,2cyclictest326993-21kworker/u16:2+events_unbound22:52:255
4107403993836,2cyclictest326993-21kworker/u16:2+events_unbound22:52:255
4107399993836,2cyclictest326993-21kworker/u16:2+events_unbound22:41:014
4107399993836,2cyclictest231239-21kworker/u16:0+events_unbound21:56:274
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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