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2026-07-08 - 17:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Wed Jul 08, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269947921000,1sleep72699480-21sh11:57:487
204245225848,7sleep50-21swapper/507:06:265
204264825217,30sleep70-21swapper/707:09:087
25986822500,0sleep50-21swapper/511:15:225
27964932480,0sleep50-21swapper/512:35:215
204266324131,7sleep40-21swapper/407:09:214
2043017994038,2cyclictest2553808-21kworker/u16:0+events_unbound11:05:276
2043017994037,2cyclictest2688802-21kworker/u16:0+flush-8:012:15:086
2043017993936,2cyclictest2503024-21kworker/u16:3+flush-8:011:09:546
2043017993835,2cyclictest2317775-21kworker/u16:2+events_unbound09:30:076
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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