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2026-05-10 - 02:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun May 10, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
103310225040,7sleep50-21swapper/519:07:405
1033435994745,2cyclictest1591794-21kworker/u16:3+events_unbound23:58:465
1033435994744,2cyclictest1689376-21kworker/u16:2+flush-8:000:03:465
103307424720,8sleep40-21swapper/419:07:144
1033435994442,2cyclictest1134972-21kworker/u16:2+flush-8:020:23:465
1033435994341,2cyclictest1075991-21kworker/u16:3+events_unbound19:48:465
10328842403,31sleep70-21swapper/719:04:377
1033435993937,2cyclictest1543943-21kworker/u16:1+events_unbound23:02:585
1033435993937,2cyclictest1304404-21kworker/u16:4+events_unbound22:40:265
1033435993836,2cyclictest1591794-21kworker/u16:3+events_unbound23:29:155
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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