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2026-01-09 - 10:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Fri Jan 09, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
143321025646,7sleep40-21swapper/419:07:574
143292825521,30sleep70-21swapper/719:03:597
1433550994944,4cyclictest1824695-21latency_hist22:28:107
1433550994740,5cyclictest1640591-21latency_hist20:53:107
1433550994640,5cyclictest1960184-21latency_hist23:38:107
143320324029,8sleep60-21swapper/619:07:516
143292624029,8sleep50-21swapper/519:03:575
1433541993834,3cyclictest1650454-21kworker/u16:0+flush-8:021:03:105
1433543993735,2cyclictest1592616-21kworker/u16:0+events_unbound20:48:246
1433541993733,3cyclictest1843692-21kworker/u16:0+flush-8:023:18:105
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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