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2026-07-05 - 16:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Jul 05, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205219825520,30sleep70-21swapper/707:08:017
205203524938,8sleep40-21swapper/407:05:424
2052538994846,2cyclictest2336250-21kworker/u16:7+events_unbound10:24:134
2052538994744,2cyclictest2621049-21kworker/u16:1+events_unbound11:53:494
2052538994240,2cyclictest2424865-21kworker/u16:2+events_unbound10:33:304
2052551994136,4cyclictest2338758-21latency_hist09:28:477
2052551994034,5cyclictest2202005-21latency_hist08:23:487
2052547993933,6cyclictest2559632-21kworker/u16:2+events_unbound11:20:146
2052538993937,2cyclictest2606241-21kworker/u16:0+events_unbound11:48:464
2052538993937,2cyclictest2336250-21kworker/u16:7+events_unbound11:03:224
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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