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2026-06-08 - 04:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Mon Jun 08, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
135908421060,1sleep71359086-21kthreadcore22:51:437
13792782950,1sleep40-21swapper/422:59:024
870568996360,2cyclictest1104687-21kworker/u16:0+events_unbound21:06:384
870568996260,2cyclictest1225785-21kworker/u16:2+events_unbound23:36:574
870568996159,2cyclictest1260615-21kworker/u16:4+events_unbound22:51:584
870575996057,2cyclictest1047943-21smartctl20:36:407
870568995856,1cyclictest1094534-21kworker/u16:1+events_unbound21:16:404
870573995755,2cyclictest860459-21kworker/u16:3+flush-8:019:36:536
870573995755,2cyclictest1104687-21kworker/u16:0+events_unbound21:16:546
870568995755,2cyclictest979705-21kworker/u16:3+flush-8:020:36:544
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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