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2026-08-08 - 06:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sat Aug 08, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2650102940,1sleep50-21swapper/521:13:475
2650102940,1sleep50-21swapper/521:13:475
7838995856,2cyclictest215453-21kworker/u16:1+events_unbound21:13:546
7838995856,2cyclictest215453-21kworker/u16:1+events_unbound21:13:546
7844995551,2cyclictest482955-21swap22:43:547
7826995250,2cyclictest483397-21kworker/u16:5+events_unbound23:28:534
7834994946,2cyclictest416802-21kworker/u16:0+flush-8:022:23:375
7838994845,2cyclictest60110-21kworker/u16:3+flush-8:020:08:386
7838994845,2cyclictest461890-21kworker/u16:3+flush-8:022:58:366
7834994844,3cyclictest546079-21kworker/u16:0+flush-8:023:13:475
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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