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2026-06-14 - 05:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Jun 14, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4582952910,0sleep40-21swapper/419:51:224
35906625948,8sleep40-21swapper/419:04:524
359433994946,2cyclictest1063568-21kworker/u16:5+flush-8:000:35:595
359431994946,2cyclictest450097-21kworker/u16:1+flush-8:020:01:164
35891424939,7sleep50-21swapper/519:02:445
359431994846,2cyclictest760450-21kworker/u16:4+events_unbound22:41:144
359438994641,4cyclictest497713-21latency_hist20:16:007
359434994643,2cyclictest555817-21kworker/u16:0+flush-8:020:56:016
359433994239,2cyclictest929468-21kworker/u16:1+events_unbound23:45:595
3588602426,31sleep70-21swapper/719:01:587
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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