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2026-08-14 - 07:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Fri Aug 14, 2026 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
394721421000,1sleep73947215-21cut21:28:247
38953582970,1sleep73895357-21kthreadcore21:08:217
39099192950,0sleep50-21swapper/521:13:245
37023862550,1sleep60-21swapper/619:28:206
3654238995350,2cyclictest95917-21kworker/u16:1+flush-8:023:57:596
3654237995250,2cyclictest4066197-21kworker/u16:4+events_unbound22:28:265
3654237995048,2cyclictest4082868-21kworker/u16:0+flush-8:022:53:265
365380125040,7sleep40-21swapper/419:05:434
36493602431,31sleep70-21swapper/719:03:227
3654237994240,2cyclictest3784775-21kworker/u16:1+flush-8:022:08:155
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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