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2026-07-20 - 21:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Mon Jul 20, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
199123424939,7sleep50-21swapper/507:09:325
198197324533,8sleep40-21swapper/407:04:424
199109124130,8sleep60-21swapper/607:07:336
19904742403,31sleep70-21swapper/707:05:097
1991520993634,2cyclictest2500094-21kworker/u16:2+flush-8:011:49:285
1991520993633,2cyclictest2647543-21kworker/u16:0+events_unbound12:19:335
1991524993533,2cyclictest2559486-21kworker/u16:1+events_unbound11:38:196
1991524993533,2cyclictest2484853-21kworker/u16:0+events_unbound10:55:476
1991520993532,2cyclictest2537032-21kworker/u16:4+flush-8:011:19:345
1991524993427,7cyclictest2131184-21kworker/u16:3+flush-8:010:23:516
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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