You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-30 - 19:57
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Nov 30, 2025 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1428807995750,5cyclictest2068332-21latency_hist20:37:597
142834625343,7sleep60-21swapper/615:21:546
1428807994840,7cyclictest589235-21systemd-journal18:29:457
1428806994744,2cyclictest727396-21kworker/u16:4+flush-8:016:22:596
142833624636,7sleep50-21swapper/515:21:455
1428803994543,2cyclictest1976468-21kworker/u16:5+flush-8:019:51:145
1428807994439,4cyclictest1755420-21latency_hist18:02:597
1428803994442,2cyclictest1786017-21kworker/u16:2+events_unbound18:46:155
1428803994442,2cyclictest1705128-21kworker/u16:4+events_unbound18:08:425
1428803994442,2cyclictest1504373-21kworker/u16:3+events_unbound16:06:145
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional