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2026-09-01 - 12:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Tue Sep 01, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205952121030,1sleep72059522-21kthreadcore23:44:557
144104126857,7sleep40-21swapper/419:05:514
144131425746,8sleep50-21swapper/519:09:375
143204125319,29sleep70-21swapper/719:04:417
1441639995247,4cyclictest1861797-21latency_hist22:24:387
1441635994341,2cyclictest1862183-21kworker/u16:1+flush-8:022:34:386
1441635994341,2cyclictest1862183-21kworker/u16:1+flush-8:022:34:386
1441635994038,2cyclictest1862183-21kworker/u16:1+flush-8:022:59:396
1441627993835,2cyclictest1650539-21kworker/u16:0+events_unbound21:14:544
1441627993735,2cyclictest2033114-21kworker/u16:5+events_unbound23:35:364
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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