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2026-07-14 - 20:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Tue Jul 14, 2026 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325708925746,8sleep50-21swapper/507:08:095
325692825520,30sleep70-21swapper/707:05:547
325694623929,7sleep60-21swapper/607:06:096
3257508993331,1cyclictest0-21swapper/711:29:577
3257499993229,2cyclictest3915170-21kworker/u16:2+events_unbound12:05:114
3257502993129,2cyclictest3416929-21kworker/u16:2+flush-8:008:40:135
3257502993129,2cyclictest3416929-21kworker/u16:2+flush-8:008:40:135
3257502992826,2cyclictest3358725-21kworker/u16:0+flush-8:008:15:275
325629622815,8sleep40-21swapper/407:05:274
33982852270,1chrt3398284-21gltestperf08:20:104
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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