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2025-09-18 - 21:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Thu Sep 18, 2025 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51875225645,7sleep60-21swapper/615:26:276
51881925544,8sleep50-21swapper/515:27:225
51876125139,8sleep40-21swapper/415:26:334
51859924511,29sleep70-21swapper/715:24:197
519126994341,2cyclictest561181-21kworker/u16:4+events_unbound16:07:454
519126994240,2cyclictest621045-21kworker/u16:0+events_unbound17:13:174
519131994139,2cyclictest470432-21kworker/u16:1+flush-8:015:59:456
519131994038,2cyclictest621193-21kworker/u16:1+flush-8:016:26:466
519131994038,2cyclictest621193-21kworker/u16:1+flush-8:016:26:466
519128993937,2cyclictest729659-21kworker/u16:1+events_unbound17:48:265
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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