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2026-03-22 - 02:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Mar 22, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46861425848,7sleep40-21swapper/418:58:284
478012994842,5cyclictest1031885-21latency_hist23:18:207
478011994644,2cyclictest1124618-21kworker/u16:5+flush-8:000:08:206
4774052436,32sleep70-21swapper/718:59:037
478011994240,2cyclictest974207-21kworker/u16:3+events_unbound23:01:196
478011994240,2cyclictest770316-21kworker/u16:1+events_unbound21:35:146
478011994240,2cyclictest501120-21kworker/u16:0+events_unbound22:12:476
478011994139,2cyclictest671776-21kworker/u16:3+events_unbound21:10:546
478011994139,2cyclictest671776-21kworker/u16:3+events_unbound21:10:546
47757624131,7sleep60-21swapper/619:01:276
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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