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2026-03-29 - 12:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Mar 29, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1027794995048,2cyclictest1607568-21kworker/u16:1+events_unbound00:02:544
102740424838,7sleep40-21swapper/419:01:184
102734924838,7sleep50-21swapper/519:00:315
1027794994341,2cyclictest1476278-21kworker/u16:3+events_unbound23:05:114
1027794994341,2cyclictest1379116-21kworker/u16:4+events_unbound21:54:404
1027794994341,2cyclictest1368630-21kworker/u16:2+events_unbound22:03:594
1027794994341,2cyclictest1356652-21kworker/u16:3+events_unbound21:50:284
1027794994341,2cyclictest1222440-21kworker/u16:0+events_unbound22:24:244
1027794994341,2cyclictest1222440-21kworker/u16:0+events_unbound21:33:204
1027802994240,2cyclictest1222440-21kworker/u16:0+flush-8:021:43:166
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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