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2026-01-04 - 16:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Jan 04, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26706192930,0sleep60-21swapper/607:23:586
262838926334,9sleep40-21swapper/407:07:384
262839225419,31sleep70-21swapper/707:07:417
262841825141,7sleep60-21swapper/607:08:046
262822224938,8sleep50-21swapper/507:05:155
2628748994543,2cyclictest2845082-21kworker/u16:1+flush-8:009:08:285
2628748994543,2cyclictest2661570-21kworker/u16:2+flush-8:007:58:285
2628743994542,2cyclictest2998666-21kworker/u16:4+events_unbound10:18:464
2628748994441,2cyclictest3183185-21kworker/u16:0+flush-8:012:28:275
2628748994239,2cyclictest2777723-21kworker/u16:0+flush-8:008:33:285
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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