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2025-12-04 - 16:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Thu Dec 04, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1938810996663,2cyclictest2235413-21kworker/u16:1+flush-8:018:02:436
193842125747,7sleep50-21swapper/515:21:505
193843425320,29sleep70-21swapper/715:22:007
193841125343,7sleep40-21swapper/415:21:414
1938802994744,2cyclictest2499758-21kworker/u16:2+events_unbound20:46:104
1938802994644,2cyclictest2195203-21kworker/u16:4+events_unbound17:55:104
1938813994540,4cyclictest2296240-21latency_hist18:17:437
1938810994542,2cyclictest2548506-21kworker/u16:5+flush-8:020:42:436
192889324434,7sleep60-21swapper/615:17:506
193881399430,41cyclictest589235-21systemd-journal16:57:437
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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