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2026-07-30 - 02:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Thu Jul 30, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1428580995552,2cyclictest1932221-21kworker/u16:0+events_unbound23:54:154
142815724838,7sleep50-21swapper/519:07:035
1428580994442,2cyclictest1932221-21kworker/u16:0+flush-8:023:24:304
1428580994442,2cyclictest1871609-21kworker/u16:3+events_unbound22:44:294
1428580994340,2cyclictest1932221-21kworker/u16:0+events_unbound00:24:114
1428580994340,2cyclictest1932221-21kworker/u16:0+events_unbound00:24:114
1428580994239,2cyclictest1932221-21kworker/u16:0+flush-8:022:59:344
14199932425,31sleep70-21swapper/719:04:177
1428580994039,1cyclictest1665752-21kworker/u16:2+events_unbound22:39:144
1428580993937,2cyclictest2114757-21kworker/u16:4+flush-8:000:19:194
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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