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2026-06-23 - 08:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Tue Jun 23, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
351042925722,30sleep70-21swapper/719:07:557
351042925722,30sleep70-21swapper/719:07:557
351052224535,7sleep50-21swapper/519:09:135
351052224535,7sleep50-21swapper/519:09:135
3510826993937,2cyclictest4114970-21kworker/u16:0+flush-8:023:40:074
3510826993937,2cyclictest4054059-21kworker/u16:1+events_unbound23:35:064
3510826993837,1cyclictest3896606-21kworker/u16:5+events_unbound23:21:564
3510826993836,2cyclictest3720125-21kworker/u16:1+events_unbound21:37:014
3510826993835,2cyclictest3896606-21kworker/u16:5+events_unbound22:59:394
351037923828,7sleep40-21swapper/419:07:114
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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