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2025-12-28 - 23:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sun Dec 28, 2025 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
295130624635,8sleep50-21swapper/507:04:505
2951898994539,5cyclictest3013785-21latency_hist07:38:567
2951893994139,2cyclictest3324361-21kworker/u16:0+events_unbound11:03:555
29513572418,29sleep70-21swapper/707:05:327
2951893994038,2cyclictest3488648-21kworker/u16:1+events_unbound12:29:115
2951897993836,2cyclictest3343583-21kworker/u16:4+events_unbound10:29:106
2951897993836,2cyclictest3343583-21kworker/u16:4+events_unbound10:29:106
2951893993735,2cyclictest2965665-21kworker/u16:4+flush-8:007:23:565
295153323727,7sleep60-21swapper/607:08:046
2951893993533,2cyclictest3168949-21kworker/u16:0+events_unbound09:08:555
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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