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2026-10-30 - 10:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Fri Oct 30, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26890612960,1sleep40-21swapper/419:32:344
263636825622,29sleep70-21swapper/719:04:347
263640425443,8sleep50-21swapper/519:05:045
263639425241,8sleep40-21swapper/419:04:554
2636885994240,2cyclictest2766942-21kworker/u16:2+events_unbound21:22:505
2636887994139,2cyclictest3143920-21kworker/u16:1+events_unbound23:32:076
2636885994139,2cyclictest2864552-21kworker/u16:1+flush-8:021:38:005
2636885994038,2cyclictest3202206-21kworker/u16:2+events_unbound23:31:415
2636881994038,2cyclictest3202206-21kworker/u16:2+flush-8:023:28:074
2636881994037,2cyclictest2864552-21kworker/u16:1+events_unbound21:07:374
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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