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2026-06-20 - 08:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sat Jun 20, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
234374621040,1sleep40-21swapper/421:15:084
21145102980,1sleep7911-21dbus-daemon19:19:497
208176525038,8sleep50-21swapper/519:04:575
209098624713,29sleep70-21swapper/719:09:257
208176424736,7sleep40-21swapper/419:04:564
2091282994240,2cyclictest2437172-21kworker/u16:3+events_unbound22:20:045
2091282993735,2cyclictest2658886-21kworker/u16:0+events_unbound23:49:485
2091282993735,2cyclictest2571361-21kworker/u16:1+events_unbound23:02:195
2091282993735,2cyclictest2509988-21kworker/u16:2+events_unbound22:42:445
2091282993634,2cyclictest2830415-21kworker/u16:4+events_unbound00:39:285
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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