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2026-06-26 - 08:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Fri Jun 26, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
396244125646,7sleep40-21swapper/419:08:424
396224325520,30sleep70-21swapper/719:05:577
396246025040,7sleep50-21swapper/519:08:595
396239524232,7sleep60-21swapper/619:08:046
3962787993936,2cyclictest251183-21kworker/u16:0+events_unbound00:14:274
3962794993836,2cyclictest43386-21kworker/u16:4+events_unbound21:43:566
3962787993734,2cyclictest251183-21kworker/u16:0+events_unbound00:25:434
396279799360,34cyclictest92294-21latency_hist21:44:267
3962794993634,2cyclictest4112451-21kworker/u16:2+events_unbound22:35:166
3962794993634,2cyclictest358450-21kworker/u16:2+events_unbound23:37:316
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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