You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-03 - 19:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
OSADL QA Farm

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of system in rack #0, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next 		  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot2.osadl.org (updated Tue Feb 03, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)		T*(,W**)
latency
(µs)		CmdPIDPrioCmd
23863825847,7sleep60-21swapper/607:01:336
24777025644,8sleep50-21swapper/507:05:015
248152995448,5cyclictest667379-21kworker/u16:2+flush-8:010:31:264
24775625343,7sleep40-21swapper/407:04:524
248157995248,3cyclictest534803-21kworker/u16:1+flush-8:010:56:255
2476312523,45sleep70-21swapper/707:03:037
248157994037,2cyclictest728681-21kworker/u16:2+flush-8:011:06:535
248166993933,5cyclictest407989-21latency_hist08:31:267
248166993832,5cyclictest650-21systemd-journal08:16:267
248157993835,2cyclictest512240-21kworker/u16:3+flush-8:009:41:265
3055702310,1chrt0-21swapper/507:31:455
248166993025,4cyclictest650-21systemd-journal10:46:347
248166993025,4cyclictest650-21systemd-journal10:46:347
248157993028,2cyclictest534803-21kworker/u16:1+events_unbound10:11:485
248157993028,2cyclictest219006-21kworker/u16:0+flush-8:007:28:415
248166992924,4cyclictest427317-21latency_hist08:41:257
248157992927,2cyclictest310048-21kworker/u16:2+flush-8:008:46:205
248157992826,2cyclictest534803-21kworker/u16:1+events_unbound10:41:485
24816699270,26cyclictest899604-21latency_hist12:01:257
248157992725,2cyclictest851084-21kworker/u16:1+events_unbound11:51:495
248157992724,2cyclictest811782-21kworker/u16:0+flush-8:011:36:315
248165992623,2cyclictest683070-21kworker/u16:0+flush-8:010:37:246
248157992623,2cyclictest851084-21kworker/u16:1+events_unbound11:46:425
248157992521,3cyclictest851084-21kworker/u16:1+flush-8:012:06:315
248157992422,2cyclictest851084-21kworker/u16:1+events_unbound12:16:485
248157992422,2cyclictest485710-21kworker/u16:1+events_unbound09:11:505
248157992421,2cyclictest512240-21kworker/u16:3+flush-8:009:26:265
248157992421,2cyclictest512240-21kworker/u16:3+flush-8:009:26:265
248166992317,5cyclictest456443-21latency_hist08:56:267
24816699230,22cyclictest887502-21latency_hist11:56:267
248157992321,2cyclictest548546-21kworker/u16:0+events_unbound09:41:445
248152992321,2cyclictest584911-21kworker/u16:4+flush-8:009:56:414
248157992220,2cyclictest728681-21kworker/u16:2+events_unbound11:01:425
248166992119,1cyclictest860324-21sh11:41:537
248166992118,2cyclictest1267-21snmpd12:03:257
248157992119,2cyclictest811782-21kworker/u16:0+events_unbound11:36:255
248157992119,2cyclictest475527-21kworker/u16:0+events_unbound09:06:515
248152992118,2cyclictest512240-21kworker/u16:3+flush-8:010:06:564
248152992118,2cyclictest512240-21kworker/u16:3+flush-8:010:06:564
248152992117,3cyclictest837199-21kworker/u16:2+flush-8:012:16:434
248166992014,5cyclictest742269-21latency_hist10:56:267
248157992018,2cyclictest534803-21kworker/u16:1+events_unbound10:21:485
248157992018,2cyclictest534803-21kworker/u16:1+events_unbound10:01:575
248157992018,2cyclictest534803-21kworker/u16:1+events_unbound09:48:155
248157992018,2cyclictest219007-21kworker/u16:4+flush-8:007:06:525
248166991915,3cyclictest1267-21snmpd08:20:027
24816699180,16cyclictest300164-21fwupd07:28:277
248165991816,2cyclictest728681-21kworker/u16:2+events_unbound10:54:086
248152991814,3cyclictest816092-21cat11:26:404
248152991814,3cyclictest548546-21kworker/u16:0+flush-8:009:41:514
248166991717,0cyclictest0-21swapper/712:16:587
248166991716,0cyclictest0-21swapper/712:26:407
248166991715,1cyclictest475860-21diskmemload11:11:427
248166991713,3cyclictest1267-21snmpd11:32:287
248166991711,5cyclictest851166-21latency_hist11:41:267
24816599170,14cyclictest0-21swapper/611:44:486
248157991715,2cyclictest728681-21kworker/u16:2+events_unbound11:21:385
248157991715,2cyclictest310048-21kworker/u16:2+events_unbound08:36:515
248157991714,2cyclictest310048-21kworker/u16:2+events_unbound08:01:405
248157991713,3cyclictest646865-21cat10:16:425
24816699168,7cyclictest0-21swapper/711:46:507
24816699168,7cyclictest0-21swapper/709:31:507
24816699167,8cyclictest0-21swapper/709:20:377
24816599161,14cyclictest745733-21kthreadcore10:56:436
24816599160,0cyclictest0-21swapper/611:53:476
248157991614,2cyclictest310048-21kworker/u16:2+flush-8:009:01:265
248157991613,2cyclictest512240-21kworker/u16:3+flush-8:009:51:315
24815799160,2cyclictest521246-21ntpq09:21:495
248152991615,1cyclictest851084-21kworker/u16:1+events_unbound12:21:414
24816699159,5cyclictest271270-21latency_hist07:16:267
24816699157,7cyclictest0-21swapper/712:06:497
24816699157,7cyclictest0-21swapper/710:11:487
24816699157,7cyclictest0-21swapper/710:06:377
24816699157,7cyclictest0-21swapper/710:06:377
24816699157,7cyclictest0-21swapper/709:11:497
24816699156,8cyclictest0-21swapper/712:21:377
24816699156,8cyclictest0-21swapper/711:16:507
24816699156,8cyclictest0-21swapper/711:06:437
24816699156,8cyclictest0-21swapper/710:04:547
248166991512,2cyclictest1267-21snmpd10:57:247
248165991514,1cyclictest0-21swapper/611:14:136
248165991514,1cyclictest0-21swapper/610:11:006
248165991514,1cyclictest0-21swapper/610:11:006
248165991513,2cyclictest358392-21kworker/u16:1+events_unbound07:59:416
248165991512,3cyclictest0-21swapper/610:03:546
248165991512,3cyclictest0-21swapper/609:22:176
248157991513,2cyclictest219006-21kworker/u16:0+flush-8:007:36:445
24815799150,15cyclictest0-21swapper/508:51:435
24815299150,1cyclictest0-21swapper/410:02:144
24815299150,1cyclictest0-21swapper/407:11:294
24815299150,14cyclictest0-21swapper/408:26:504
24816699148,5cyclictest650-21systemd-journal09:46:267
24816699147,6cyclictest0-21swapper/709:51:317
24816699147,6cyclictest0-21swapper/709:36:407
24816699146,7cyclictest0-21swapper/712:32:237
24816699146,7cyclictest0-21swapper/711:21:417
24816699146,7cyclictest0-21swapper/710:24:007
24816699146,7cyclictest0-21swapper/709:26:467
24816699146,7cyclictest0-21swapper/709:26:467
24816699146,7cyclictest0-21swapper/709:06:557
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional