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2025-05-03 - 01:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot2.osadl.org (updated Sat May 03, 2025 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2105221994241,0cyclictest0-21swapper/704:32:277
2105190993835,2cyclictest2591896-21kworker/u16:2+events_unbound07:37:064
2105221993736,0cyclictest0-21swapper/707:32:267
2105210993735,2cyclictest2335223-21kworker/u16:2+events_unbound05:41:516
210522199360,34cyclictest2685330-21latency_hist08:17:087
2105210993432,2cyclictest2114769-21kworker/u16:1+events_unbound05:33:196
2105210993331,2cyclictest2101228-21kworker/u16:5+events_unbound05:09:196
2105210993330,2cyclictest2448282-21kworker/u16:1+flush-8:006:29:196
2105210993330,2cyclictest2222118-21kworker/u16:4+events_unbound04:33:596
2105210993230,2cyclictest2170287-21kworker/u16:0+events_unbound04:04:206
2105210993129,2cyclictest2746208-21kworker/u16:2+events_unbound09:06:186
2105210993129,2cyclictest2727309-21kworker/u16:0+flush-8:008:51:186
2105210993129,2cyclictest2101228-21kworker/u16:5+events_unbound04:16:196
2105210993128,2cyclictest2222118-21kworker/u16:4+flush-8:004:57:186
2105210993128,2cyclictest2191900-21kworker/u16:3+events_unbound04:55:196
2105210993028,2cyclictest2304339-21kworker/u16:0+events_unbound05:44:186
2105221992928,0cyclictest0-21swapper/708:07:217
2105210992927,2cyclictest2715445-21kworker/u16:3+flush-8:008:30:196
2105210992927,2cyclictest2715445-21kworker/u16:3+events_unbound08:34:196
2105210992927,2cyclictest2602659-21kworker/u16:0+events_unbound07:55:186
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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