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2025-08-21 - 22:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot2.osadl.org (updated Thu Aug 21, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1067898996563,2cyclictest1258454-21kworker/u16:6+flush-8:017:03:186
106735025646,7sleep60-21swapper/615:26:396
106757125545,7sleep40-21swapper/415:29:424
106727325141,7sleep50-21swapper/515:25:335
1067900994944,4cyclictest589235-21systemd-journal17:02:117
1067898994543,2cyclictest1474106-21kworker/u16:3+events_unbound18:55:536
1067893994340,2cyclictest1464988-21kworker/u16:0+flush-8:019:09:445
10674082417,30sleep70-21swapper/715:27:287
1067900994039,0cyclictest0-21swapper/719:35:127
1067900994039,0cyclictest0-21swapper/719:29:457
1067900994039,0cyclictest0-21swapper/719:29:457
1067900994039,0cyclictest0-21swapper/716:05:187
1067900994037,2cyclictest1493950-21smart_sda19:00:127
1067900993938,0cyclictest0-21swapper/719:43:057
1067898993937,2cyclictest1552649-21kworker/u16:5+flush-8:020:55:106
1067886993734,2cyclictest1091205-21kworker/u16:5+flush-8:016:24:444
1067898993634,2cyclictest1661143-21kworker/u16:4+events_unbound20:28:046
1067898993634,2cyclictest1130575-21kworker/u16:1+events_unbound16:41:286
1067898993633,2cyclictest359591-21kworker/u16:3+events_unbound15:29:546
1067898993533,2cyclictest1228459-21kworker/u16:2+events_unbound17:07:236
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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