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2026-06-29 - 07:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Jun 29, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
383181926555,7sleep50-21swapper/519:05:365
383207726048,8sleep40-21swapper/419:09:124
3832372994741,5cyclictest3953121-21latency_hist20:09:147
3832361994442,2cyclictest4001526-21kworker/u16:4+events_unbound22:44:154
38227652447,30sleep70-21swapper/719:04:187
3832372994136,4cyclictest4031071-21latency_hist20:49:147
3832361993938,1cyclictest33454-21kworker/u16:0+events_unbound22:10:444
3832361993937,2cyclictest4092501-21kworker/u16:3+events_unbound21:16:324
3832361993936,2cyclictest33454-21kworker/u16:0+events_unbound22:33:464
3832372993833,4cyclictest353709-21latency_hist00:24:137
3832362993734,2cyclictest33454-21kworker/u16:0+flush-8:022:34:125
3832361993736,1cyclictest255953-21kworker/u16:3+events_unbound00:18:524
3832361993735,2cyclictest354016-21kworker/u16:0+events_unbound00:37:124
3832361993735,2cyclictest354016-21kworker/u16:0+events_unbound00:37:124
3832361993735,2cyclictest155635-21kworker/u16:0+events_unbound23:03:084
3832361993634,2cyclictest4001526-21kworker/u16:4+flush-8:021:09:134
3832361993634,2cyclictest4001526-21kworker/u16:4+events_unbound21:43:154
3832361993634,2cyclictest155635-21kworker/u16:0+events_unbound23:56:084
3832361993634,2cyclictest155635-21kworker/u16:0+events_unbound23:56:084
3832361993634,2cyclictest155635-21kworker/u16:0+events_unbound23:04:154
3832367993531,3cyclictest170646-21kworker/u16:5+flush-8:000:39:126
3832367993531,3cyclictest170646-21kworker/u16:5+flush-8:000:39:126
3832361993533,2cyclictest95528-21kworker/u16:2+flush-8:022:59:134
3832361993533,2cyclictest46643-21kworker/u16:1+events_unbound22:20:404
3832361993533,2cyclictest170646-21kworker/u16:5+events_unbound23:49:184
3832361993533,2cyclictest155635-21kworker/u16:0+events_unbound23:39:104
3832361993533,2cyclictest121335-21kworker/u16:1+events_unbound23:14:034
3832361993432,2cyclictest46643-21kworker/u16:1+events_unbound22:26:164
3832361993432,2cyclictest4180220-21kworker/u16:2+events_unbound22:03:444
3832361993432,2cyclictest4092501-21kworker/u16:3+events_unbound21:29:164
3832361993432,2cyclictest233157-21kworker/u16:2+events_unbound00:05:154
3832361993432,2cyclictest230306-21kworker/u16:1+events_unbound23:33:124
3832361993432,2cyclictest155635-21kworker/u16:0+events_unbound00:03:124
3832361993431,2cyclictest4001526-21kworker/u16:4+flush-8:021:44:134
382276423424,7sleep60-21swapper/619:04:176
3832361993331,2cyclictest95528-21kworker/u16:2+events_unbound22:49:434
3832361993331,2cyclictest4001526-21kworker/u16:4+events_unbound22:07:194
3832361993331,2cyclictest4001526-21kworker/u16:4+events_unbound21:52:244
3832361993331,2cyclictest4001526-21kworker/u16:4+events_unbound21:52:244
3832361993331,2cyclictest4001526-21kworker/u16:4+events_unbound21:37:404
3832361993331,2cyclictest317142-21kworker/u16:1+events_unbound00:11:404
3832361993331,2cyclictest170646-21kworker/u16:5+events_unbound23:27:364
3832361993230,2cyclictest95528-21kworker/u16:2+events_unbound22:40:154
3832361993230,2cyclictest4141203-21kworker/u16:0+events_unbound21:58:194
3832361993230,2cyclictest4060778-21kworker/u16:0+events_unbound21:13:034
3832361993230,2cyclictest4060778-21kworker/u16:0+events_unbound21:13:034
3832361993230,2cyclictest3992492-21kworker/u16:2+events_unbound21:26:324
3832361993230,2cyclictest170646-21kworker/u16:5+events_unbound00:20:244
3832361993229,2cyclictest95528-21kworker/u16:2+events_unbound22:38:064
3832372993130,0cyclictest0-21swapper/721:04:437
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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