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2026-06-10 - 00:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Tue Jun 09, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
72386225848,7sleep40-21swapper/407:04:304
9919922560,0sleep7991991-21rm09:17:177
72429799420,40cyclictest1102639-21latency_hist10:06:187
724288994139,2cyclictest1126899-21kworker/u16:3+events_unbound12:24:405
724288994038,2cyclictest1174994-21kworker/u16:1+events_unbound11:38:055
7236992403,31sleep70-21swapper/707:02:087
724297993934,4cyclictest1391493-21latency_hist12:06:177
724288993937,2cyclictest1174994-21kworker/u16:1+events_unbound11:49:005
724288993937,2cyclictest1040629-21kworker/u16:1+events_unbound09:52:375
724288993836,2cyclictest852947-21kworker/u16:2+events_unbound11:02:495
724288993836,2cyclictest852947-21kworker/u16:2+events_unbound10:57:185
724288993836,2cyclictest1259626-21kworker/u16:4+events_unbound11:15:505
724288993836,2cyclictest1174994-21kworker/u16:1+events_unbound11:57:325
724288993835,2cyclictest1063852-21kworker/u16:0+events_unbound10:01:215
724287993835,2cyclictest1126899-21kworker/u16:3+flush-8:011:16:444
724288993735,2cyclictest852947-21kworker/u16:2+events_unbound10:47:365
724288993735,2cyclictest852947-21kworker/u16:2+events_unbound10:25:085
724288993735,2cyclictest1174994-21kworker/u16:1+events_unbound11:43:085
724288993735,2cyclictest1063852-21kworker/u16:0+events_unbound10:00:135
724288993735,2cyclictest1040629-21kworker/u16:1+events_unbound09:38:215
724287993734,2cyclictest890129-21kworker/u16:4+events_unbound08:51:334
724288993634,2cyclictest890129-21kworker/u16:4+events_unbound09:27:055
724288993634,2cyclictest852947-21kworker/u16:2+events_unbound11:10:105
724288993634,2cyclictest852947-21kworker/u16:2+events_unbound09:12:375
724288993634,2cyclictest1126899-21kworker/u16:3+events_unbound11:17:445
72380723628,5sleep50-21swapper/507:03:435
724292993532,2cyclictest1063852-21kworker/u16:0+flush-8:009:56:186
724288993533,2cyclictest890129-21kworker/u16:4+events_unbound09:36:015
724288993533,2cyclictest890129-21kworker/u16:4+events_unbound09:36:015
724288993533,2cyclictest1414396-21kworker/u16:2+events_unbound12:19:085
724288993533,2cyclictest1414396-21kworker/u16:2+events_unbound12:15:565
724288993533,2cyclictest1174994-21kworker/u16:1+events_unbound11:53:455
724288993533,2cyclictest1126899-21kworker/u16:3+events_unbound12:09:085
724288993533,2cyclictest1126899-21kworker/u16:3+events_unbound12:05:255
724288993533,2cyclictest1126899-21kworker/u16:3+events_unbound10:28:135
724288993533,2cyclictest1063852-21kworker/u16:0+events_unbound10:17:095
724288993532,2cyclictest715609-21kworker/u16:0+events_unbound07:06:215
724287993532,2cyclictest852947-21kworker/u16:2+events_unbound09:36:404
724292993432,2cyclictest890129-21kworker/u16:4+flush-8:009:26:446
724288993432,2cyclictest890129-21kworker/u16:4+events_unbound09:22:495
724288993432,2cyclictest852947-21kworker/u16:2+events_unbound10:55:375
724288993432,2cyclictest833110-21kworker/u16:1+flush-8:008:11:405
724288993432,2cyclictest833110-21kworker/u16:1+flush-8:008:11:405
724288993432,2cyclictest1414396-21kworker/u16:2+events_unbound12:33:085
724288993432,2cyclictest1414396-21kworker/u16:2+events_unbound12:30:415
724288993432,2cyclictest1063852-21kworker/u16:0+events_unbound09:47:305
724288993331,2cyclictest852947-21kworker/u16:2+events_unbound10:07:485
724288993331,2cyclictest852947-21kworker/u16:2+events_unbound09:07:015
724288993331,2cyclictest1174994-21kworker/u16:1+events_unbound11:23:065
724288993331,2cyclictest1162716-21kworker/u16:0+events_unbound10:38:005
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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