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2026-03-25 - 19:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Wed Mar 25, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
293932626150,7sleep60-21swapper/607:00:426
293932525444,7sleep50-21swapper/507:00:415
2939794994341,2cyclictest2901817-21kworker/u16:2+events_unbound07:23:255
29394302422,36sleep70-21swapper/707:02:117
626589410,34rtkit-daemon0-21swapper/407:01:524
2939795994038,2cyclictest3485590-21kworker/u16:1+flush-8:011:28:396
2939794993836,2cyclictest3558320-21kworker/u16:3+events_unbound12:18:315
2939795993735,2cyclictest3329606-21kworker/u16:3+events_unbound10:13:246
2939794993634,2cyclictest3435267-21kworker/u16:0+events_unbound10:53:205
2939799993534,0cyclictest0-21swapper/707:48:437
2939794993533,2cyclictest3435267-21kworker/u16:0+events_unbound12:08:315
35233032340,1sleep50-21swapper/511:28:215
2939794993431,3cyclictest3485590-21kworker/u16:1+events_unbound11:23:205
2939792993432,2cyclictest3521826-21kworker/u16:2+events_unbound11:43:204
2939792993432,2cyclictest2991043-21kworker/u16:3+events_unbound07:33:294
2939792993432,2cyclictest2920528-21kworker/u16:1+events_unbound07:08:104
2939795993331,2cyclictest3438024-21kworker/u16:4+events_unbound11:08:196
2939794993331,2cyclictest3020106-21kworker/u16:1+events_unbound07:58:375
2939794993331,2cyclictest2920528-21kworker/u16:1+events_unbound07:08:345
2939795993230,2cyclictest3435267-21kworker/u16:0+events_unbound12:13:356
2939794993230,2cyclictest3020106-21kworker/u16:1+events_unbound09:13:225
2939799993130,0cyclictest0-21swapper/707:08:227
2939792993129,2cyclictest3435267-21kworker/u16:0+events_unbound11:28:234
2939795993028,2cyclictest3197295-21kworker/u16:4+flush-8:010:08:386
2939795993027,2cyclictest3154031-21kworker/u16:2+flush-8:009:28:226
2939795993027,2cyclictest3154031-21kworker/u16:2+flush-8:009:28:226
2939794993028,2cyclictest3580968-21kworker/u16:1+events_unbound12:08:015
2939799992929,0cyclictest0-21swapper/709:58:417
2939795992927,2cyclictest3413993-21kworker/u16:3+flush-8:010:43:356
2939795992926,2cyclictest3435267-21kworker/u16:0+flush-8:012:08:386
2939794992927,2cyclictest3048535-21kworker/u16:2+events_unbound08:08:245
2939792992927,2cyclictest3048535-21kworker/u16:2+events_unbound08:28:184
2939794992826,2cyclictest3230294-21kworker/u16:0+events_unbound09:48:195
2939792992826,2cyclictest3230294-21kworker/u16:0+events_unbound09:43:364
2939799992727,0cyclictest0-21swapper/711:08:417
2939799992726,0cyclictest0-21swapper/712:13:457
2939799992721,5cyclictest3173096-21latency_hist09:03:077
2939795992725,2cyclictest3001088-21kworker/u16:0+events_unbound08:13:216
2939795992724,3cyclictest3558320-21kworker/u16:3+flush-8:012:33:016
2939794992725,2cyclictest3485590-21kworker/u16:1+events_unbound11:34:195
2939794992725,2cyclictest3329606-21kworker/u16:3+events_unbound10:23:205
2939794992725,2cyclictest3230294-21kworker/u16:0+events_unbound09:43:205
2939794992725,2cyclictest3174390-21kworker/u16:3+events_unbound09:13:055
2939794992725,2cyclictest3154031-21kworker/u16:2+events_unbound10:42:335
2939792992725,2cyclictest3558320-21kworker/u16:3+events_unbound12:18:254
2939799992621,4cyclictest2949195-21latency_hist07:08:077
2939799992620,5cyclictest3000899-21latency_hist07:33:077
2939795992624,2cyclictest2920528-21kworker/u16:1+events_unbound07:08:126
2939794992624,2cyclictest3154031-21kworker/u16:2+events_unbound10:23:015
2939794992624,2cyclictest3001088-21kworker/u16:0+events_unbound08:38:205
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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