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2026-01-04 - 17:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sun Jan 04, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26706192930,0sleep60-21swapper/607:23:586
262838926334,9sleep40-21swapper/407:07:384
262839225419,31sleep70-21swapper/707:07:417
262841825141,7sleep60-21swapper/607:08:046
262822224938,8sleep50-21swapper/507:05:155
2628748994543,2cyclictest2845082-21kworker/u16:1+flush-8:009:08:285
2628748994543,2cyclictest2661570-21kworker/u16:2+flush-8:007:58:285
2628743994542,2cyclictest2998666-21kworker/u16:4+events_unbound10:18:464
2628748994441,2cyclictest3183185-21kworker/u16:0+flush-8:012:28:275
2628748994239,2cyclictest2777723-21kworker/u16:0+flush-8:008:33:285
2628743993936,2cyclictest2661570-21kworker/u16:2+events_unbound09:18:414
2628751993833,4cyclictest955-21in:imjournal12:13:287
2628743993836,2cyclictest2729207-21kworker/u16:3+events_unbound08:03:424
2628743993836,2cyclictest2661570-21kworker/u16:2+events_unbound08:28:544
2628743993835,2cyclictest3240841-21kworker/u16:3+flush-8:012:33:274
2628748993735,2cyclictest3057646-21kworker/u16:1+flush-8:011:13:285
2628743993734,2cyclictest2912570-21kworker/u16:3+events_unbound09:48:424
2628743993634,2cyclictest2845082-21kworker/u16:1+events_unbound08:58:584
2628743993634,2cyclictest2661570-21kworker/u16:2+events_unbound07:28:434
2628743993633,2cyclictest3240841-21kworker/u16:3+events_unbound12:33:414
262875199350,34cyclictest650-21systemd-journal09:33:287
2628749993432,2cyclictest2628949-21kworker/u16:4+events_unbound07:08:436
2628743993431,2cyclictest3076939-21kworker/u16:3+events_unbound12:03:414
2628743993431,2cyclictest2729207-21kworker/u16:3+events_unbound08:08:414
2628751993332,0cyclictest0-21swapper/710:38:587
2628749993331,2cyclictest2912570-21kworker/u16:3+flush-8:010:08:436
2628743993331,2cyclictest2661570-21kworker/u16:2+events_unbound08:13:424
2628743993330,2cyclictest3183185-21kworker/u16:0+flush-8:012:08:564
2628743993330,2cyclictest2680826-21kworker/u16:1+flush-8:008:38:434
2628743993330,2cyclictest2680826-21kworker/u16:1+flush-8:008:38:434
2628743993229,2cyclictest2661570-21kworker/u16:2+events_unbound07:48:414
2628743993129,2cyclictest2661570-21kworker/u16:2+flush-8:009:13:584
2628748993027,3cyclictest3183185-21kworker/u16:0+flush-8:012:03:455
2628743993028,2cyclictest3100792-21kworker/u16:4+events_unbound11:13:534
2628743993028,2cyclictest3076939-21kworker/u16:3+flush-8:011:28:434
2628743993028,2cyclictest2661570-21kworker/u16:2+events_unbound08:53:284
2628743993027,2cyclictest3183185-21kworker/u16:0+flush-8:011:58:384
2628743993027,2cyclictest3076939-21kworker/u16:3+events_unbound11:18:304
2628743993027,2cyclictest2661570-21kworker/u16:2+events_unbound08:43:464
2628743993026,3cyclictest2912570-21kworker/u16:3+flush-8:010:13:434
2628749992927,2cyclictest3213616-21kworker/u16:2+events_unbound12:09:336
2628748992927,2cyclictest2777723-21kworker/u16:0+flush-8:008:48:595
2628743992927,2cyclictest2998666-21kworker/u16:4+events_unbound10:38:424
2628751992825,2cyclictest3230573-21smartctl12:14:017
2628751992822,5cyclictest3134824-21latency_hist11:28:287
2628749992826,2cyclictest2680826-21kworker/u16:1+events_unbound08:24:016
2628749992826,2cyclictest2661570-21kworker/u16:2+events_unbound07:56:226
2628743992826,2cyclictest2680826-21kworker/u16:1+flush-8:008:23:564
2628743992826,2cyclictest2595040-21kworker/u16:0+events_unbound07:13:564
2628743992825,2cyclictest3037946-21kworker/u16:0+events_unbound10:53:414
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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