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2026-04-06 - 21:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Apr 06, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127746826145,11sleep40-21swapper/406:57:304
127745825847,7sleep50-21swapper/506:57:235
1286881994845,2cyclictest1481985-21kworker/u16:1+flush-8:009:57:494
1286881994543,2cyclictest1869430-21kworker/u16:2+events_unbound11:27:484
1286890994438,5cyclictest1347874-21latency_hist07:32:197
1286881994441,2cyclictest1750626-21kworker/u16:2+events_unbound10:42:364
1286890994336,5cyclictest1519997-21latency_hist09:02:197
12777502413,31sleep70-21swapper/706:57:347
1286890994039,0cyclictest0-21swapper/708:42:427
12796212400,2chrt0-21swapper/606:57:406
1286881993734,3cyclictest1481985-21kworker/u16:1+events_unbound10:17:414
1286881993533,2cyclictest1869430-21kworker/u16:2+events_unbound11:47:484
1286881993533,2cyclictest1869430-21kworker/u16:2+events_unbound11:34:254
1286881993432,2cyclictest1855980-21kworker/u16:0+events_unbound11:17:524
1286881993432,2cyclictest1750626-21kworker/u16:2+events_unbound10:52:534
1286881993331,2cyclictest1942893-21kworker/u16:1+events_unbound12:02:534
1286881993331,2cyclictest1651217-21kworker/u16:0+events_unbound10:22:524
1286881993330,2cyclictest1481985-21kworker/u16:1+events_unbound10:32:364
1286883993229,2cyclictest1990863-21kworker/u16:3+flush-8:012:27:186
1286881993129,2cyclictest1990184-21kworker/u16:2+events_unbound12:12:514
1286881993129,2cyclictest1914605-21kworker/u16:5+events_unbound11:42:454
1286881993129,2cyclictest1481985-21kworker/u16:1+events_unbound10:12:404
1286881993128,2cyclictest1750626-21kworker/u16:2+events_unbound10:37:214
1286882993028,1cyclictest1750626-21kworker/u16:2+flush-8:011:07:185
1286881993028,2cyclictest1990863-21kworker/u16:3+events_unbound12:27:484
1286881993028,2cyclictest1750626-21kworker/u16:2+events_unbound11:02:534
1286881993028,2cyclictest1556857-21kworker/u16:5+events_unbound09:27:414
1286881993028,2cyclictest1544664-21kworker/u16:2+flush-8:009:22:354
18135742290,1chrt1813575-21kthreadcore11:02:387
1286882992927,2cyclictest1357635-21kworker/u16:1+events_unbound08:02:345
1286881992927,2cyclictest1811060-21kworker/u16:1+events_unbound11:23:364
1286881992927,2cyclictest1544664-21kworker/u16:2+flush-8:009:37:494
1286881992927,2cyclictest1481985-21kworker/u16:1+events_unbound09:48:404
1286881992926,2cyclictest1532135-21kworker/u16:4+flush-8:009:17:144
1286882992825,2cyclictest1318808-21kworker/u16:2+events_unbound07:27:455
1286881992826,2cyclictest1942893-21kworker/u16:1+events_unbound12:17:484
18061632270,1chrt1806164-21grep10:57:417
1286881992725,2cyclictest1942893-21kworker/u16:1+events_unbound11:57:424
1286881992725,2cyclictest1869430-21kworker/u16:2+events_unbound11:53:364
1286883992624,2cyclictest1295047-21kworker/u16:0+events_unbound07:07:456
1286882992624,2cyclictest1328767-21kworker/u16:0+events_unbound07:47:325
1286881992623,2cyclictest1651217-21kworker/u16:0+events_unbound10:07:334
1286882992523,2cyclictest1463032-21kworker/u16:3+flush-8:008:52:455
1286881992524,1cyclictest1651217-21kworker/u16:0+events_unbound10:02:464
1286881992523,2cyclictest1855980-21kworker/u16:0+events_unbound11:37:374
1286881992523,2cyclictest1651217-21kworker/u16:0+events_unbound10:30:484
1286881992523,2cyclictest1481985-21kworker/u16:1+flush-8:009:17:454
1286881992522,3cyclictest1424538-21kworker/u16:2+flush-8:008:57:444
1286881992522,2cyclictest1811060-21kworker/u16:1+events_unbound11:07:294
1286881992522,2cyclictest1556857-21kworker/u16:5+events_unbound09:52:324
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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