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2025-12-10 - 10:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Wed Dec 10, 2025 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
194457427546,7sleep40-21swapper/403:21:064
1944981995956,2cyclictest2119612-21kworker/u16:0+flush-8:005:17:214
1944981995956,2cyclictest2119612-21kworker/u16:0+flush-8:005:17:214
194462125646,7sleep60-21swapper/603:21:496
193578225419,29sleep70-21swapper/703:17:417
1944992995246,5cyclictest2603316-21latency_hist08:47:207
1944992995146,4cyclictest589235-21systemd-journal07:02:217
194446625040,7sleep50-21swapper/503:19:395
1944992994843,4cyclictest2059515-21latency_hist04:17:217
1944981994543,2cyclictest2270876-21kworker/u16:0+flush-8:006:22:214
1944992994237,4cyclictest2512561-21latency_hist08:02:217
1944992994237,4cyclictest2150123-21latency_hist05:02:217
1944992993932,5cyclictest589235-21systemd-journal08:14:027
1944981993937,2cyclictest1998946-21kworker/u16:2+flush-8:004:27:524
1944981993937,2cyclictest1998946-21kworker/u16:2+flush-8:004:27:524
1944981993836,2cyclictest2099635-21kworker/u16:3+events_unbound05:37:474
1944992993328,4cyclictest589235-21systemd-journal05:42:227
194499299320,30cyclictest2381720-21latency_hist06:57:217
1944981993230,2cyclictest2119612-21kworker/u16:0+events_unbound05:17:514
1944992993025,4cyclictest2401829-21latency_hist07:07:217
1944992993024,5cyclictest2119928-21latency_hist04:47:227
1944981993029,1cyclictest2583050-21kworker/u16:0+flush-8:008:52:204
1944981993028,2cyclictest2432434-21kworker/u16:4+events_unbound08:22:384
1944981993027,2cyclictest2059191-21kworker/u16:3+flush-8:004:22:434
1944981993026,3cyclictest2190504-21kworker/u16:1+events_unbound06:02:404
1944992992927,1cyclictest0-21swapper/704:00:287
1944992992923,5cyclictest2502508-21latency_hist07:57:217
194499299280,26cyclictest2210606-21latency_hist05:32:227
1944987992826,2cyclictest1998946-21kworker/u16:2+events_unbound04:27:415
1944987992826,2cyclictest1998946-21kworker/u16:2+events_unbound04:27:415
1944987992824,3cyclictest2170034-21kworker/u16:2+flush-8:005:24:225
194499299270,25cyclictest2281166-21latency_hist06:07:217
1944992992625,0cyclictest0-21swapper/708:47:377
1944987992624,2cyclictest2300955-21kworker/u16:3+events_unbound06:47:395
1944987992623,2cyclictest2099635-21kworker/u16:3+flush-8:005:32:365
1944981992623,2cyclictest2150511-21kworker/u16:1+events_unbound05:07:454
1944992992524,0cyclictest0-21swapper/707:25:197
1944992992524,0cyclictest0-21swapper/704:25:277
1944992992524,0cyclictest0-21swapper/703:24:227
1944992992520,4cyclictest2331471-21latency_hist06:32:217
194499299250,23cyclictest2140046-21latency_hist04:57:227
1944981992522,2cyclictest2472018-21kworker/u16:1+flush-8:007:57:424
1944992992423,0cyclictest0-21swapper/703:36:597
1944987992422,2cyclictest1944452-21kworker/u16:3+flush-8:003:42:365
1944981992422,2cyclictest2099635-21kworker/u16:3+flush-8:005:02:444
1944992992322,0cyclictest0-21swapper/705:15:197
1944992992322,0cyclictest0-21swapper/705:15:197
1944992992321,1cyclictest0-21swapper/707:47:477
1944992992321,1cyclictest0-21swapper/704:17:357
1944992992318,4cyclictest2049491-21cut04:12:227
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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