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2026-05-22 - 14:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Fri May 22, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278438426554,7sleep50-21swapper/507:04:085
278457425848,7sleep40-21swapper/407:06:484
278445924925,7sleep60-21swapper/607:05:136
2784913994543,2cyclictest3385501-21kworker/u16:0+events_unbound12:17:525
2784913994139,2cyclictest3165881-21kworker/u16:3+flush-8:011:07:545
27844242416,30sleep70-21swapper/707:04:427
2784913993836,2cyclictest3227100-21kworker/u16:0+flush-8:010:52:535
2784913993835,3cyclictest2097566-21kworker/u16:2+events_unbound09:17:535
2784908993836,2cyclictest3385501-21kworker/u16:0+events_unbound12:16:054
2784908993735,2cyclictest3361185-21kworker/u16:3+events_unbound11:28:394
2784908993735,2cyclictest3240466-21kworker/u16:1+flush-8:010:45:514
2784908993735,2cyclictest3113950-21kworker/u16:3+flush-8:009:50:234
2784908993735,2cyclictest2904192-21kworker/u16:0+events_unbound09:34:394
2784908993734,2cyclictest3385501-21kworker/u16:0+flush-8:012:32:414
2784908993734,2cyclictest3385501-21kworker/u16:0+flush-8:012:32:414
2784908993734,2cyclictest3200059-21kworker/u16:2+flush-8:010:33:174
2784922993635,0cyclictest0-21swapper/710:16:507
278492299360,34cyclictest5819-21gnome-shell11:28:397
2784913993634,2cyclictest3361185-21kworker/u16:3+flush-8:011:42:255
2784913993634,2cyclictest3009089-21kworker/u16:1+flush-8:009:32:265
2784908993634,2cyclictest3385501-21kworker/u16:0+flush-8:012:06:544
2784908993634,2cyclictest3346640-21kworker/u16:2+flush-8:011:37:024
2784908993634,2cyclictest3009089-21kworker/u16:1+flush-8:009:41:304
2784908993633,2cyclictest2904192-21kworker/u16:0+events_unbound09:54:024
2784922993533,1cyclictest3019039-21diskmemload11:40:507
2784922993533,1cyclictest0-21swapper/710:49:057
2784908993533,2cyclictest3385501-21kworker/u16:0+events_unbound11:49:344
2784908993533,2cyclictest3385501-21kworker/u16:0+events_unbound11:49:344
2784908993533,2cyclictest3346640-21kworker/u16:2+events_unbound11:19:504
2784908993533,2cyclictest3150996-21kworker/u16:4+flush-8:010:07:064
2784908993533,2cyclictest3150996-21kworker/u16:4+events_unbound10:19:264
2784908993533,2cyclictest3009089-21kworker/u16:1+flush-8:009:26:294
2784922993433,0cyclictest0-21swapper/711:06:307
2784913993432,2cyclictest3346640-21kworker/u16:2+events_unbound11:27:135
2784913993432,2cyclictest2904192-21kworker/u16:0+events_unbound09:47:275
2784913993432,2cyclictest2904192-21kworker/u16:0+events_unbound09:47:275
2784908993432,2cyclictest3385501-21kworker/u16:0+flush-8:012:24:494
2784908993432,2cyclictest3150996-21kworker/u16:4+flush-8:010:02:094
2784908993432,2cyclictest3009089-21kworker/u16:1+flush-8:009:13:314
2784908993432,2cyclictest3009089-21kworker/u16:1+events_unbound09:18:054
2784908993432,2cyclictest2904192-21kworker/u16:0+flush-8:008:42:254
2784908993432,2cyclictest2904192-21kworker/u16:0+events_unbound10:13:504
2784922993332,0cyclictest0-21swapper/712:30:387
2784922993332,0cyclictest0-21swapper/712:30:387
2784922993332,0cyclictest0-21swapper/711:09:347
2784913993331,2cyclictest3385501-21kworker/u16:0+events_unbound11:57:335
2784913993331,2cyclictest3361185-21kworker/u16:3+flush-8:011:54:585
2784913993331,2cyclictest3227100-21kworker/u16:0+events_unbound11:01:455
2784913993330,2cyclictest3165881-21kworker/u16:3+events_unbound10:37:275
2784908993331,2cyclictest3385501-21kworker/u16:0+events_unbound11:59:464
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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