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2026-06-13 - 10:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sat Jun 13, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38229172640,1sleep50-21swapper/523:21:265
325785925746,8sleep40-21swapper/419:02:584
325802824838,7sleep50-21swapper/519:05:245
32576522473,38sleep70-21swapper/719:01:417
3258370994443,0cyclictest0-21swapper/723:21:367
3258370994440,3cyclictest3504243-21latency_hist21:11:047
3258359994240,2cyclictest3600711-21kworker/u16:1+events_unbound22:11:324
3258370994038,1cyclictest3492270-21diskmemload22:26:307
325837099400,38cyclictest3588287-21latency_hist21:46:057
3258359994038,2cyclictest3248891-21kworker/u16:3+events_unbound19:11:094
3258370993934,4cyclictest3482695-21latency_hist21:01:057
3258359993331,2cyclictest3564368-21kworker/u16:4+events_unbound22:56:334
3258365993230,2cyclictest3482364-21kworker/u16:3+events_unbound21:26:316
325804023220,9sleep60-21swapper/619:05:336
36771872310,0chrt3677189-21kthreadcore22:21:257
3258370993130,0cyclictest0-21swapper/721:56:107
3258370993130,0cyclictest0-21swapper/721:56:107
3258370993130,0cyclictest0-21swapper/721:01:197
3258370993130,0cyclictest0-21swapper/719:27:237
3258370993126,4cyclictest3281267-21latency_hist19:16:057
3258359993129,2cyclictest3513571-21kworker/u16:0+events_unbound21:17:344
3258359993129,2cyclictest3513571-21kworker/u16:0+events_unbound21:17:344
3258370993029,0cyclictest0-21swapper/722:40:107
3258370993029,0cyclictest0-21swapper/719:36:307
3258359993028,2cyclictest3564368-21kworker/u16:4+flush-8:000:11:324
3258359993028,2cyclictest3552358-21kworker/u16:2+events_unbound22:32:424
3258359993028,2cyclictest3482364-21kworker/u16:3+events_unbound21:48:564
37725882290,1chrt3772591-21kthreadcore23:01:247
3258370992928,0cyclictest0-21swapper/721:25:157
3258359992927,2cyclictest3728683-21kworker/u16:0+events_unbound22:49:234
3258359992927,2cyclictest3482364-21kworker/u16:3+events_unbound21:24:544
3258359992927,2cyclictest3310075-21kworker/u16:1+events_unbound19:42:274
3258370992827,0cyclictest0-21swapper/723:27:247
3258359992826,2cyclictest3728683-21kworker/u16:0+events_unbound23:53:134
3258359992826,2cyclictest3552358-21kworker/u16:2+events_unbound21:56:334
3258359992826,2cyclictest3552358-21kworker/u16:2+events_unbound21:56:334
37311302270,1chrt3731129-21ssh22:43:457
3258370992726,0cyclictest0-21swapper/723:40:337
3258370992726,0cyclictest0-21swapper/722:46:537
3258370992726,0cyclictest0-21swapper/722:16:457
3258370992725,1cyclictest3897398-21ssh23:51:347
3258359992725,2cyclictest3728683-21kworker/u16:0+flush-8:023:06:304
3258359992725,2cyclictest3672323-21kworker/u16:0+events_unbound22:21:204
3258359992725,2cyclictest3513571-21kworker/u16:0+events_unbound21:14:404
3258370992625,0cyclictest0-21swapper/723:11:127
3258370992625,0cyclictest0-21swapper/722:59:137
3258370992625,0cyclictest0-21swapper/720:52:277
3258370992625,0cyclictest0-21swapper/700:05:097
3258370992625,0cyclictest0-21swapper/700:05:097
3258365992624,2cyclictest3239357-21kworker/u16:2+events_unbound19:16:186
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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