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2025-12-30 - 01:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Tue Dec 30, 2025 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
270779521040,1sleep72707796-21cat20:19:097
30949492930,1sleep73094951-21tr23:39:097
30609532670,1sleep73060956-21tr23:19:137
29562072630,1sleep40-21swapper/422:29:034
256425525822,31sleep70-21swapper/719:06:277
256437325444,7sleep40-21swapper/419:08:084
256428125129,7sleep60-21swapper/619:06:506
2564723994441,2cyclictest2674808-21kworker/u16:0+flush-8:020:09:075
256440324331,9sleep50-21swapper/519:08:335
2564723994138,2cyclictest2762140-21kworker/u16:0+events_unbound21:28:515
2564725993835,2cyclictest2884256-21kworker/u16:5+events_unbound21:54:076
2564725993735,2cyclictest2674808-21kworker/u16:0+flush-8:020:04:156
2564729993629,6cyclictest650-21systemd-journal19:43:507
2564725993633,2cyclictest2965760-21kworker/u16:1+events_unbound22:54:076
2564725993633,2cyclictest2965760-21kworker/u16:1+events_unbound22:54:076
2564723993634,2cyclictest3169220-21kworker/u16:3+flush-8:000:38:495
2564723993633,2cyclictest2636169-21kworker/u16:3+events_unbound20:19:035
2564725993532,2cyclictest2950256-21kworker/u16:2+flush-8:022:28:516
2564723993533,2cyclictest2884256-21kworker/u16:5+events_unbound21:59:125
2564723993432,2cyclictest2965760-21kworker/u16:1+flush-8:023:49:145
2564723993432,2cyclictest2771766-21kworker/u16:2+events_unbound21:04:075
2564725993331,2cyclictest2965760-21kworker/u16:1+events_unbound23:06:206
2564725993331,2cyclictest2746232-21kworker/u16:1+events_unbound21:12:166
2564723993331,2cyclictest2975196-21kworker/u16:3+flush-8:022:39:055
2564723993331,2cyclictest2636169-21kworker/u16:3+events_unbound19:59:205
2564723993330,2cyclictest2829905-21kworker/u16:3+events_unbound21:24:095
2564723993330,2cyclictest2674808-21kworker/u16:0+flush-8:020:29:075
2564729993231,0cyclictest0-21swapper/721:34:077
2564725993230,2cyclictest3101215-21kworker/u16:2+events_unbound23:53:006
2564725993230,2cyclictest2746232-21kworker/u16:1+events_unbound21:14:196
2564725993229,2cyclictest3149399-21kworker/u16:0+events_unbound00:09:066
2564725993229,2cyclictest2946019-21kworker/u16:0+events_unbound22:24:036
2564723993230,2cyclictest3072414-21kworker/u16:0+events_unbound23:36:595
2564723993230,2cyclictest2965760-21kworker/u16:1+events_unbound23:29:595
2564723993230,2cyclictest2897071-21kworker/u16:0+events_unbound22:04:195
2564723993230,2cyclictest2746232-21kworker/u16:1+events_unbound20:59:515
2564729993126,4cyclictest2994462-21latency_hist22:48:497
2564729993124,6cyclictest2752234-21latency_hist20:43:507
2564725993129,2cyclictest2876117-21kworker/u16:4+events_unbound23:02:006
2564725993128,2cyclictest2746232-21kworker/u16:1+events_unbound21:44:036
2564723993129,2cyclictest2965760-21kworker/u16:1+events_unbound22:59:225
2564723993129,2cyclictest2704202-21kworker/u16:2+flush-8:020:24:035
2564723993129,2cyclictest2674808-21kworker/u16:0+events_unbound20:35:005
2564719993129,2cyclictest3130452-21kworker/u16:5+events_unbound00:05:114
2564725993028,2cyclictest3033433-21kworker/u16:3+events_unbound23:26:006
2564725993028,2cyclictest2897760-21kworker/u16:3+events_unbound22:04:136
2564725993028,2cyclictest2839747-21kworker/u16:2+events_unbound21:49:186
2564723993028,2cyclictest3101215-21kworker/u16:2+events_unbound23:58:525
2564723993028,2cyclictest2876117-21kworker/u16:4+flush-8:021:48:505
2564723993028,2cyclictest2876117-21kworker/u16:4+events_unbound00:06:595
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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