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2026-06-03 - 01:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Wed Jun 03, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31831582980,1sleep73183157-21ssh21:44:127
288064925848,7sleep40-21swapper/419:04:484
288055525039,8sleep50-21swapper/519:03:295
2881070994846,2cyclictest3399056-21kworker/u16:1+events_unbound23:27:134
2881070994139,2cyclictest3305422-21kworker/u16:0+events_unbound22:56:464
28807772413,32sleep70-21swapper/719:06:357
2881070994038,2cyclictest3570612-21kworker/u16:3+flush-8:000:31:454
2881070993836,2cyclictest2992615-21kworker/u16:1+events_unbound22:26:464
2881070993835,2cyclictest3206303-21kworker/u16:2+events_unbound21:55:134
2881070993835,2cyclictest2808535-21kworker/u16:0+events_unbound19:41:464
2881070993735,2cyclictest2904714-21kworker/u16:3+flush-8:021:15:504
2881070993734,2cyclictest3305422-21kworker/u16:0+flush-8:022:56:214
2881070993734,2cyclictest3305422-21kworker/u16:0+flush-8:022:56:214
2881070993734,2cyclictest3305422-21kworker/u16:0+events_unbound23:11:144
2881070993734,2cyclictest3305422-21kworker/u16:0+events_unbound00:26:464
2881070993635,1cyclictest3206303-21kworker/u16:2+events_unbound22:23:504
2881070993634,2cyclictest3305422-21kworker/u16:0+flush-8:023:20:454
2881070993634,2cyclictest3305422-21kworker/u16:0+events_unbound23:56:214
2881070993633,2cyclictest2992615-21kworker/u16:1+events_unbound20:21:464
2881076993533,2cyclictest3329494-21kworker/u16:5+flush-8:023:11:446
2881070993533,2cyclictest3305422-21kworker/u16:0+flush-8:000:09:134
2881070993532,3cyclictest2963716-21kworker/u16:0+flush-8:020:31:444
2881070993433,1cyclictest3206303-21kworker/u16:2+events_unbound22:16:334
2881070993433,1cyclictest3206303-21kworker/u16:2+events_unbound22:16:334
2881070993432,2cyclictest3206303-21kworker/u16:2+flush-8:022:01:344
2881070993432,2cyclictest2904714-21kworker/u16:3+events_unbound23:04:104
2881070993431,2cyclictest2904714-21kworker/u16:3+flush-8:022:17:094
2881070993331,2cyclictest3522088-21kworker/u16:2+events_unbound00:22:264
2881070993331,2cyclictest3329494-21kworker/u16:5+flush-8:023:32:264
2881070993331,2cyclictest3100354-21kworker/u16:0+events_unbound21:44:434
2881070993331,2cyclictest2904714-21kworker/u16:3+events_unbound21:36:414
2881070993331,2cyclictest2904714-21kworker/u16:3+events_unbound21:36:414
2881070993331,2cyclictest2904714-21kworker/u16:3+events_unbound21:29:034
2881070993330,2cyclictest3522088-21kworker/u16:2+events_unbound00:11:534
2881070993330,2cyclictest2904714-21kworker/u16:3+events_unbound21:16:454
2881076993230,2cyclictest2904714-21kworker/u16:3+events_unbound22:32:056
2881070993230,2cyclictest3522088-21kworker/u16:2+flush-8:000:18:264
2881070993230,2cyclictest3399056-21kworker/u16:1+flush-8:023:36:534
2881070993230,2cyclictest3329494-21kworker/u16:5+events_unbound00:06:424
2881070993230,2cyclictest3305422-21kworker/u16:0+flush-8:023:58:184
2881070993230,2cyclictest2992615-21kworker/u16:1+flush-8:022:10:264
2881070993230,2cyclictest2992615-21kworker/u16:1+events_unbound21:37:354
2881070993230,2cyclictest2904714-21kworker/u16:3+events_unbound22:38:304
2881076993129,2cyclictest3305422-21kworker/u16:0+events_unbound23:42:016
2881073993128,2cyclictest3305422-21kworker/u16:0+flush-8:023:56:495
2881070993129,2cyclictest3206303-21kworker/u16:2+events_unbound22:02:584
2881070993028,2cyclictest3399056-21kworker/u16:1+events_unbound23:46:054
2881070993028,2cyclictest3329494-21kworker/u16:5+events_unbound23:48:064
2881070993028,2cyclictest3329494-21kworker/u16:5+events_unbound22:48:424
2881070993028,2cyclictest2992615-21kworker/u16:1+flush-8:021:10:434
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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