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2026-06-19 - 21:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Fri Jun 19, 2026 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
323837126049,7sleep40-21swapper/407:07:464
323851925520,30sleep70-21swapper/707:09:507
322923224535,7sleep50-21swapper/507:04:595
3238800993533,2cyclictest3563377-21kworker/u16:1+flush-8:011:34:465
3238800993331,2cyclictest3209625-21kworker/u16:0+events_unbound07:14:545
3238800993229,2cyclictest3909902-21kworker/u16:2+flush-8:012:20:015
3238800993229,2cyclictest3909902-21kworker/u16:2+flush-8:012:20:015
36384902310,1sleep60-21swapper/610:15:066
32919062310,1chrt3291908-21cpuspeed_turbos07:35:057
3238800993028,2cyclictest3732977-21kworker/u16:3+flush-8:010:59:475
323836423020,7sleep60-21swapper/607:07:406
39731082290,1chrt0-21swapper/412:30:084
39208192290,1chrt0-21swapper/512:07:575
37374012290,1chrt3737402-21ssh10:55:067
34338312280,0chrt0-21swapper/408:45:134
39444612270,1chrt3944460-21ssh12:16:087
39444612270,1chrt3944460-21ssh12:16:087
32871772270,1chrt0-21swapper/407:30:134
3238805992724,2cyclictest3869196-21ntpq11:45:177
3238800992624,2cyclictest3848000-21kworker/u16:4+flush-8:012:00:535
3238800992624,2cyclictest3406109-21kworker/u16:1+events_unbound08:45:065
3238800992624,2cyclictest3348635-21kworker/u16:2+flush-8:008:10:235
323880599250,23cyclictest1345-21dockerd09:20:507
3238795992520,4cyclictest3897167-21latency_hist11:59:514
38925132240,0sleep5741rcuc/511:55:145
3238805992423,0cyclictest0-21swapper/710:39:047
3238805992423,0cyclictest0-21swapper/710:30:347
3238805992322,0cyclictest0-21swapper/707:50:167
3238800992319,3cyclictest3359412-21cat08:09:525
3238800992319,3cyclictest3359412-21cat08:09:525
3238805992221,0cyclictest0-21swapper/711:06:127
3238800992220,2cyclictest3773328-21kworker/u16:2+flush-8:011:25:225
3238795992217,4cyclictest3909547-21latency_hist12:04:514
3238805992120,0cyclictest0-21swapper/710:42:497
3238805992120,0cyclictest0-21swapper/708:28:377
3238800992119,2cyclictest3535760-21kworker/u16:0+flush-8:010:00:225
3238795992116,4cyclictest3300965-21latency_hist07:39:524
3238805992019,0cyclictest0-21swapper/712:30:317
3238805992019,0cyclictest0-21swapper/711:55:277
3238805992019,0cyclictest0-21swapper/709:09:387
3238805992019,0cyclictest0-21swapper/708:46:597
3238800992015,4cyclictest3271800-21awk07:24:515
3238795992016,3cyclictest3281491-21latency_hist07:29:524
3238805991918,0cyclictest0-21swapper/708:52:577
3238805991918,0cyclictest0-21swapper/707:44:417
3238805991917,1cyclictest0-21swapper/709:53:457
3238805991916,2cyclictest3497919-21smart_sda09:15:227
3238800991917,2cyclictest3848000-21kworker/u16:4+flush-8:012:15:585
3238800991917,2cyclictest3848000-21kworker/u16:4+flush-8:012:15:585
3238800991917,2cyclictest3732977-21kworker/u16:3+events_unbound11:10:225
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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