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2025-09-18 - 17:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Thu Sep 18, 2025 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51875225645,7sleep60-21swapper/615:26:276
51881925544,8sleep50-21swapper/515:27:225
51876125139,8sleep40-21swapper/415:26:334
51859924511,29sleep70-21swapper/715:24:197
519126994341,2cyclictest561181-21kworker/u16:4+events_unbound16:07:454
519126994240,2cyclictest621045-21kworker/u16:0+events_unbound17:13:174
519131994139,2cyclictest470432-21kworker/u16:1+flush-8:015:59:456
519131994038,2cyclictest621193-21kworker/u16:1+flush-8:016:26:466
519131994038,2cyclictest621193-21kworker/u16:1+flush-8:016:26:466
519128993937,2cyclictest729659-21kworker/u16:1+events_unbound17:48:265
519131993836,2cyclictest523379-21kworker/u16:3+events_unbound15:31:456
519131993836,2cyclictest470432-21kworker/u16:1+events_unbound16:03:456
519126993836,2cyclictest1053373-21kworker/u16:0+flush-8:020:08:164
519126993735,2cyclictest621045-21kworker/u16:0+events_unbound17:06:564
519126993735,2cyclictest581837-21kworker/u16:2+events_unbound16:22:444
519126993735,2cyclictest1141226-21kworker/u16:5+events_unbound20:47:264
519126993634,2cyclictest523379-21kworker/u16:3+flush-8:015:33:024
519131993432,2cyclictest621193-21kworker/u16:1+events_unbound16:20:026
519131993432,2cyclictest1102408-21kworker/u16:0+events_unbound20:37:446
519126993432,2cyclictest945010-21kworker/u16:3+events_unbound19:23:204
519131993331,2cyclictest945010-21kworker/u16:3+flush-8:019:23:276
519131993331,2cyclictest797964-21kworker/u16:5+events_unbound18:18:296
519131993331,2cyclictest777393-21kworker/u16:3+flush-8:017:45:286
519131993331,2cyclictest1122139-21kworker/u16:4+events_unbound20:55:336
519131993331,2cyclictest1053373-21kworker/u16:0+events_unbound20:08:006
519126993331,2cyclictest1141226-21kworker/u16:5+events_unbound20:50:014
519131993230,2cyclictest680517-21kworker/u16:2+flush-8:017:15:016
519131993230,2cyclictest680517-21kworker/u16:2+flush-8:016:51:016
519131993230,2cyclictest1141226-21kworker/u16:5+events_unbound20:45:006
519126993230,2cyclictest797964-21kworker/u16:5+events_unbound18:54:274
519126993230,2cyclictest1132273-21kworker/u16:2+events_unbound20:39:264
519131993129,2cyclictest906062-21kworker/u16:1+flush-8:019:39:136
519131993129,2cyclictest797964-21kworker/u16:5+flush-8:018:30:276
519131993129,2cyclictest621045-21kworker/u16:0+flush-8:017:10:556
519131993129,2cyclictest222843-21kworker/u16:5+events_unbound15:37:456
519126993129,2cyclictest846893-21kworker/u16:0+events_unbound18:37:094
519126993129,2cyclictest1063790-21kworker/u16:1+events_unbound20:31:014
519126993128,2cyclictest846893-21kworker/u16:0+events_unbound19:43:014
519126993128,2cyclictest777393-21kworker/u16:3+flush-8:017:37:534
519126993128,2cyclictest621193-21kworker/u16:1+events_unbound16:57:554
519131993028,2cyclictest906062-21kworker/u16:1+flush-8:018:59:266
519131993028,2cyclictest818093-21kworker/u16:3+events_unbound18:05:596
519131993028,2cyclictest797965-21kworker/u16:6+flush-8:018:08:236
519131993028,2cyclictest797964-21kworker/u16:5+flush-8:018:50:336
519131993028,2cyclictest797964-21kworker/u16:5+flush-8:018:50:336
519131993028,2cyclictest797952-21kworker/u16:2+events_unbound17:48:066
519131993028,2cyclictest621193-21kworker/u16:1+events_unbound16:53:546
519131993028,2cyclictest1083048-21kworker/u16:2+events_unbound20:13:306
519128993028,2cyclictest1043408-21kworker/u16:4+flush-8:020:18:205
519126993028,2cyclictest846893-21kworker/u16:0+events_unbound19:21:274
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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