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2026-06-13 - 16:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sat Jun 13, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23143952980,1sleep72314393-21ssh10:54:237
23143952980,1sleep72314393-21ssh10:54:237
181508825848,7sleep40-21swapper/407:02:544
181505125847,8sleep50-21swapper/507:02:235
1815619994539,5cyclictest1886420-21latency_hist07:41:037
1815619994237,4cyclictest2267075-21latency_hist10:36:027
1815610994241,1cyclictest2144297-21kworker/u16:0+flush-8:009:46:025
1815614994038,2cyclictest2170536-21kworker/u16:2+events_unbound10:53:296
1815614994038,2cyclictest2170536-21kworker/u16:2+events_unbound10:53:296
18060432393,30sleep70-21swapper/707:01:047
1815614993836,2cyclictest2482361-21kworker/u16:3+events_unbound12:13:246
1815614993836,2cyclictest2352726-21kworker/u16:1+events_unbound11:45:536
1815614993836,2cyclictest2204441-21kworker/u16:0+events_unbound10:30:296
1815614993836,2cyclictest2170536-21kworker/u16:2+events_unbound10:12:186
1815614993735,2cyclictest2482361-21kworker/u16:3+events_unbound12:31:546
1815614993735,2cyclictest2352726-21kworker/u16:1+events_unbound12:00:346
1815614993735,2cyclictest2148134-21kworker/u16:4+events_unbound10:05:496
1815614993735,2cyclictest2083983-21kworker/u16:0+events_unbound09:31:286
1815614993735,2cyclictest2040331-21kworker/u16:5+events_unbound09:15:386
1815619993634,1cyclictest2049906-21diskmemload10:45:207
181561999360,34cyclictest1924532-21pool-/usr/libex07:57:127
1815614993634,2cyclictest2352726-21kworker/u16:1+events_unbound11:35:006
1815614993634,2cyclictest2352726-21kworker/u16:1+events_unbound11:35:006
1815614993634,2cyclictest2204441-21kworker/u16:0+events_unbound10:23:546
1815614993634,2cyclictest2170536-21kworker/u16:2+events_unbound10:48:536
1815614993634,2cyclictest2030775-21kworker/u16:3+events_unbound09:07:336
1815602993633,2cyclictest2352726-21kworker/u16:1+events_unbound12:26:164
1815619993534,0cyclictest0-21swapper/712:03:447
1815619993534,0cyclictest0-21swapper/711:35:207
1815619993534,0cyclictest0-21swapper/711:35:207
1815619993534,0cyclictest0-21swapper/708:06:047
1815614993533,2cyclictest2457522-21kworker/u16:0+events_unbound12:02:086
1815614993533,2cyclictest2352726-21kworker/u16:1+events_unbound12:30:486
1815614993533,2cyclictest2352726-21kworker/u16:1+events_unbound11:28:246
1815614993533,2cyclictest2325056-21kworker/u16:3+events_unbound11:03:446
1815614993533,2cyclictest2148134-21kworker/u16:4+events_unbound11:17:336
1815614993533,2cyclictest2148134-21kworker/u16:4+events_unbound09:57:336
1815614993533,2cyclictest2096662-21kworker/u16:2+events_unbound09:40:496
1815614993532,2cyclictest2352726-21kworker/u16:1+events_unbound11:36:036
1815619993433,0cyclictest0-21swapper/711:55:337
1815619993433,0cyclictest0-21swapper/711:29:057
1815619993433,0cyclictest0-21swapper/710:22:097
1815614993432,2cyclictest2352726-21kworker/u16:1+events_unbound11:48:536
1815614993432,2cyclictest2325056-21kworker/u16:3+events_unbound11:23:446
1815614993432,2cyclictest2148134-21kworker/u16:4+flush-8:011:13:256
1815614993432,2cyclictest2144297-21kworker/u16:0+flush-8:009:54:446
1815614993432,2cyclictest2083983-21kworker/u16:0+flush-8:009:30:416
1815614993432,2cyclictest2083983-21kworker/u16:0+events_unbound09:24:246
1815614993431,2cyclictest2148134-21kworker/u16:4+flush-8:011:06:056
1815602993430,3cyclictest1896214-21kworker/u16:1+flush-8:007:57:144
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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