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2026-05-01 - 05:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Fri May 01, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184838625443,8sleep40-21swapper/419:06:324
1848852994842,5cyclictest2287274-21latency_hist22:33:557
1848852994842,5cyclictest2287274-21latency_hist22:33:557
183940624736,7sleep50-21swapper/519:04:005
1848842994542,2cyclictest1966507-21kworker/u16:3+events_unbound21:13:574
1848852994438,5cyclictest2419837-21latency_hist23:28:557
1848847994340,2cyclictest2053706-21kworker/u16:4+flush-8:020:59:136
1848852994140,0cyclictest0-21swapper/719:13:597
1848847994138,2cyclictest2118590-21kworker/u16:4+events_unbound23:39:256
628089400,33rtkit-daemon0-21swapper/619:04:206
18749012400,0sleep40-21swapper/419:19:134
1848842994037,2cyclictest2118590-21kworker/u16:4+events_unbound00:08:574
18399362392,31sleep70-21swapper/719:04:107
1848842993836,2cyclictest2190802-21kworker/u16:2+flush-8:022:59:334
1848842993836,2cyclictest2151858-21kworker/u16:0+events_unbound22:43:574
1848842993735,2cyclictest2369247-21kworker/u16:0+events_unbound23:48:534
1848842993735,2cyclictest2118590-21kworker/u16:4+events_unbound23:08:444
1848842993735,2cyclictest2082397-21kworker/u16:1+events_unbound21:20:064
1848842993634,2cyclictest2369247-21kworker/u16:0+events_unbound00:01:414
1848842993533,2cyclictest2369247-21kworker/u16:0+events_unbound00:06:544
1848842993533,2cyclictest2190802-21kworker/u16:2+events_unbound22:33:574
1848842993533,2cyclictest2190802-21kworker/u16:2+events_unbound22:28:054
1848842993532,2cyclictest2369247-21kworker/u16:0+events_unbound23:23:584
1848842993433,1cyclictest2190802-21kworker/u16:2+events_unbound22:18:344
1848842993331,2cyclictest2118590-21kworker/u16:4+events_unbound23:20:064
1848842993330,2cyclictest2118590-21kworker/u16:4+events_unbound22:03:574
25753952320,1chrt2575396-21kthreadcore00:34:177
25753952320,1chrt2575396-21kthreadcore00:34:177
24270392320,0chrt0-21swapper/623:29:166
1848852993226,5cyclictest2063263-21latency_hist20:58:557
1848842993230,2cyclictest2426695-21kworker/u16:2+events_unbound00:19:254
1848842993230,2cyclictest2347608-21kworker/u16:1+events_unbound23:17:374
1848842993230,2cyclictest2151858-21kworker/u16:0+events_unbound21:44:574
1848842993230,2cyclictest2151858-21kworker/u16:0+events_unbound21:42:054
1848842993230,2cyclictest2118590-21kworker/u16:4+flush-8:022:39:334
1848842993230,2cyclictest2118590-21kworker/u16:4+events_unbound23:57:574
1848842993230,2cyclictest2118590-21kworker/u16:4+events_unbound23:57:574
1848842993129,2cyclictest2369247-21kworker/u16:0+events_unbound23:09:464
1848842993129,2cyclictest2190802-21kworker/u16:2+events_unbound22:21:054
1848842993129,2cyclictest2151858-21kworker/u16:0+events_unbound22:55:054
1848842993129,2cyclictest2151858-21kworker/u16:0+events_unbound22:49:054
1848842993129,2cyclictest2151858-21kworker/u16:0+events_unbound21:55:054
1848842993129,2cyclictest2118590-21kworker/u16:4+events_unbound00:37:044
1848842993129,2cyclictest2118590-21kworker/u16:4+events_unbound00:37:044
1848842993129,2cyclictest2082397-21kworker/u16:1+events_unbound21:38:054
1848847993028,2cyclictest2151858-21kworker/u16:0+flush-8:021:34:576
1848842993028,2cyclictest2518493-21kworker/u16:3+events_unbound00:33:424
1848852992924,4cyclictest2335517-21latency_hist22:53:567
184885299290,27cyclictest1900439-21latency_hist19:33:567
1848847992927,2cyclictest2151858-21kworker/u16:0+flush-8:022:38:506
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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