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2026-06-08 - 10:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Jun 08, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
135908421060,1sleep71359086-21kthreadcore22:51:437
13792782950,1sleep40-21swapper/422:59:024
870568996360,2cyclictest1104687-21kworker/u16:0+events_unbound21:06:384
870568996260,2cyclictest1225785-21kworker/u16:2+events_unbound23:36:574
870568996159,2cyclictest1260615-21kworker/u16:4+events_unbound22:51:584
870575996057,2cyclictest1047943-21smartctl20:36:407
870568995856,1cyclictest1094534-21kworker/u16:1+events_unbound21:16:404
870573995755,2cyclictest860459-21kworker/u16:3+flush-8:019:36:536
870573995755,2cyclictest1104687-21kworker/u16:0+events_unbound21:16:546
870568995755,2cyclictest979705-21kworker/u16:3+flush-8:020:36:544
870568995654,2cyclictest1438293-21kworker/u16:0+events_unbound00:01:544
870573995553,2cyclictest1260615-21kworker/u16:4+events_unbound23:11:506
870568995452,2cyclictest903339-21kworker/u16:2+events_unbound19:31:384
870568995452,2cyclictest1210496-21kworker/u16:3+events_unbound21:51:574
87027725443,8sleep50-21swapper/519:06:175
870573995351,2cyclictest1225785-21kworker/u16:2+events_unbound22:41:586
870568995351,2cyclictest1513129-21kworker/u16:3+events_unbound00:26:574
870573995249,2cyclictest960859-21kworker/u16:0+events_unbound20:16:426
87014325241,8sleep40-21swapper/419:04:234
870568995149,2cyclictest1560790-21kworker/u16:1+events_unbound00:31:544
870573995048,2cyclictest960859-21kworker/u16:0+flush-8:020:56:536
870568995048,2cyclictest1260615-21kworker/u16:4+events_unbound23:11:544
870568995048,2cyclictest1225785-21kworker/u16:2+events_unbound00:16:534
870568995047,2cyclictest903339-21kworker/u16:2+events_unbound19:51:394
870575994946,2cyclictest921417-21sed19:26:537
870573994947,2cyclictest1438293-21kworker/u16:0+events_unbound23:57:016
870575994844,3cyclictest1130169-21kthreadcore21:16:427
870573994845,2cyclictest960859-21kworker/u16:0+flush-8:020:31:406
870573994845,2cyclictest1513129-21kworker/u16:3+events_unbound00:01:416
870575994744,2cyclictest901989-21ntpq19:16:507
870575994744,2cyclictest901989-21ntpq19:16:507
870575994744,2cyclictest1341600-21ntpq22:41:537
870573994746,1cyclictest1225785-21kworker/u16:2+events_unbound23:26:556
870573994746,1cyclictest1225785-21kworker/u16:2+events_unbound23:26:556
870573994745,2cyclictest960859-21kworker/u16:0+events_unbound20:36:506
870568994745,2cyclictest1260615-21kworker/u16:4+events_unbound23:06:464
870568994745,2cyclictest1225785-21kworker/u16:2+flush-8:022:16:494
870568994745,2cyclictest1104687-21kworker/u16:0+events_unbound21:31:554
870568994744,2cyclictest1560790-21kworker/u16:1+events_unbound00:21:254
870568994744,2cyclictest1248638-21kworker/u16:1+flush-8:022:11:574
870575994645,0cyclictest0-21swapper/720:46:547
870573994644,2cyclictest1225785-21kworker/u16:2+events_unbound00:26:396
870573994643,2cyclictest1248638-21kworker/u16:1+events_unbound22:11:556
870568994644,2cyclictest1225785-21kworker/u16:2+events_unbound23:16:594
870568994543,2cyclictest979705-21kworker/u16:3+events_unbound20:41:554
870568994543,2cyclictest960859-21kworker/u16:0+events_unbound20:46:464
870568994543,2cyclictest1260615-21kworker/u16:4+events_unbound23:51:564
870575994442,1cyclictest1177621-21ssh21:36:407
870575994442,1cyclictest1104413-21diskmemload22:16:397
870568994442,2cyclictest1438293-21kworker/u16:0+events_unbound23:31:414
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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