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2025-12-10 - 16:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Wed Dec 10, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44101526049,7sleep50-21swapper/515:22:025
44072125948,7sleep60-21swapper/615:18:026
44079125722,30sleep70-21swapper/715:18:597
441356995550,4cyclictest515643-21latency_hist15:57:197
441356995548,6cyclictest707266-21latency_hist17:32:197
441344995553,2cyclictest606395-21kworker/u16:5+flush-8:016:52:196
441344995553,2cyclictest606395-21kworker/u16:5+flush-8:016:52:196
44077925240,8sleep40-21swapper/415:18:484
441344995149,2cyclictest1010509-21kworker/u16:3+events_unbound20:17:466
441356994843,4cyclictest757741-21latency_hist17:57:207
441343994846,2cyclictest3185582-21kworker/u16:3+flush-8:015:22:355
441356994337,5cyclictest589235-21systemd-journal20:47:387
441343994341,2cyclictest889465-21kworker/u16:0+events_unbound19:06:345
441343994341,2cyclictest505560-21kworker/u16:4+events_unbound16:41:205
441343994341,2cyclictest3185582-21kworker/u16:3+events_unbound16:03:235
441343994341,2cyclictest3185582-21kworker/u16:3+events_unbound16:03:235
441356994237,4cyclictest589235-21systemd-journal20:26:387
441343994239,2cyclictest354755-21kworker/u16:0+flush-8:015:47:505
441343994139,2cyclictest968917-21kworker/u16:2+events_unbound20:03:345
441343994139,2cyclictest505560-21kworker/u16:4+flush-8:016:12:455
441343994139,2cyclictest1039541-21kworker/u16:5+events_unbound20:13:345
441343994139,2cyclictest1009282-21kworker/u16:1+events_unbound20:28:395
441343994038,2cyclictest968917-21kworker/u16:2+flush-8:019:45:345
441343994038,2cyclictest818702-21kworker/u16:3+events_unbound19:24:335
441343994038,2cyclictest787076-21kworker/u16:5+events_unbound19:54:335
441343994038,2cyclictest1009282-21kworker/u16:1+events_unbound20:41:395
441344993936,2cyclictest3185582-21kworker/u16:3+events_unbound15:22:386
441343993937,2cyclictest827573-21kworker/u16:4+events_unbound18:40:335
441344993836,2cyclictest827573-21kworker/u16:4+events_unbound20:45:196
441343993836,2cyclictest818702-21kworker/u16:3+events_unbound19:13:195
441343993836,2cyclictest606395-21kworker/u16:5+flush-8:017:02:145
441343993836,2cyclictest354755-21kworker/u16:0+events_unbound16:20:235
441343993735,2cyclictest818702-21kworker/u16:3+events_unbound18:50:335
441343993734,2cyclictest827573-21kworker/u16:4+flush-8:020:46:095
441344993634,2cyclictest606395-21kworker/u16:5+events_unbound17:29:196
441343993634,2cyclictest827573-21kworker/u16:4+events_unbound18:56:345
441343993633,2cyclictest606395-21kworker/u16:5+flush-8:016:47:365
441343993633,2cyclictest606395-21kworker/u16:5+flush-8:016:47:365
441344993533,2cyclictest666691-21kworker/u16:0+events_unbound17:14:316
441343993533,2cyclictest666691-21kworker/u16:0+flush-8:017:37:145
441343993533,2cyclictest1009282-21kworker/u16:1+flush-8:020:01:535
441356993428,5cyclictest868897-21latency_hist18:52:197
441344993432,2cyclictest726327-21kworker/u16:1+events_unbound17:41:336
441344993432,2cyclictest666691-21kworker/u16:0+events_unbound17:10:316
44135699330,31cyclictest1080786-21latency_hist20:37:197
441344993332,1cyclictest768206-21kworker/u16:2+flush-8:018:28:426
441344993331,2cyclictest726327-21kworker/u16:1+events_unbound18:09:326
441344993331,2cyclictest606395-21kworker/u16:5+events_unbound16:56:276
441343993331,2cyclictest768206-21kworker/u16:2+events_unbound18:30:295
441343993331,2cyclictest768206-21kworker/u16:2+events_unbound18:20:335
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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