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2026-03-22 - 07:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sun Mar 22, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46861425848,7sleep40-21swapper/418:58:284
478012994842,5cyclictest1031885-21latency_hist23:18:207
478011994644,2cyclictest1124618-21kworker/u16:5+flush-8:000:08:206
4774052436,32sleep70-21swapper/718:59:037
478011994240,2cyclictest974207-21kworker/u16:3+events_unbound23:01:196
478011994240,2cyclictest770316-21kworker/u16:1+events_unbound21:35:146
478011994240,2cyclictest501120-21kworker/u16:0+events_unbound22:12:476
478011994139,2cyclictest671776-21kworker/u16:3+events_unbound21:10:546
478011994139,2cyclictest671776-21kworker/u16:3+events_unbound21:10:546
47757624131,7sleep60-21swapper/619:01:276
478011994038,2cyclictest889638-21kworker/u16:2+events_unbound22:34:116
478011993937,2cyclictest839595-21kworker/u16:4+events_unbound22:16:466
478011993937,2cyclictest818222-21kworker/u16:1+events_unbound23:51:156
478011993937,2cyclictest818222-21kworker/u16:1+events_unbound23:51:156
478011993937,2cyclictest818222-21kworker/u16:1+events_unbound22:58:196
478011993937,2cyclictest818222-21kworker/u16:1+events_unbound22:47:076
478011993937,2cyclictest501120-21kworker/u16:0+events_unbound21:47:116
478011993937,2cyclictest1138904-21kworker/u16:1+events_unbound00:12:106
478011993936,2cyclictest449309-21kworker/u16:1+events_unbound19:03:236
478002993937,2cyclictest1124618-21kworker/u16:5+flush-8:000:33:194
478002993937,2cyclictest1124618-21kworker/u16:5+flush-8:000:33:194
478012993833,4cyclictest710719-21latency_hist21:03:207
478011993836,2cyclictest974207-21kworker/u16:3+events_unbound23:40:466
478011993836,2cyclictest889638-21kworker/u16:2+events_unbound22:18:456
478011993836,2cyclictest839595-21kworker/u16:4+events_unbound22:01:106
478011993836,2cyclictest818222-21kworker/u16:1+events_unbound21:54:456
478011993836,2cyclictest770316-21kworker/u16:1+events_unbound21:30:156
478011993836,2cyclictest722391-21kworker/u16:2+events_unbound21:39:266
478011993836,2cyclictest1138904-21kworker/u16:1+events_unbound00:15:586
478011993836,2cyclictest1115477-21kworker/u16:4+events_unbound00:02:106
478011993735,2cyclictest818222-21kworker/u16:1+events_unbound22:51:586
478011993735,2cyclictest653437-21kworker/u16:1+events_unbound21:05:436
478011993735,2cyclictest501120-21kworker/u16:0+events_unbound22:25:556
478011993735,2cyclictest501120-21kworker/u16:0+events_unbound22:08:066
478011993735,2cyclictest1138904-21kworker/u16:1+events_unbound00:31:036
478011993735,2cyclictest1138904-21kworker/u16:1+events_unbound00:31:036
478011993735,2cyclictest1067531-21kworker/u16:0+events_unbound23:56:026
478011993634,2cyclictest974207-21kworker/u16:3+events_unbound23:44:386
478011993634,2cyclictest974207-21kworker/u16:3+events_unbound23:20:546
478011993634,2cyclictest818222-21kworker/u16:1+flush-8:022:28:506
478011993634,2cyclictest818222-21kworker/u16:1+flush-8:022:28:506
478011993634,2cyclictest818222-21kworker/u16:1+events_unbound23:12:396
478011993634,2cyclictest818222-21kworker/u16:1+events_unbound23:12:396
478011993634,2cyclictest818222-21kworker/u16:1+events_unbound23:06:266
478011993634,2cyclictest501120-21kworker/u16:0+events_unbound21:25:436
478011993634,2cyclictest1138904-21kworker/u16:1+events_unbound00:18:296
478011993634,2cyclictest1044150-21kworker/u16:2+events_unbound23:30:306
478011993634,2cyclictest1044150-21kworker/u16:2+events_unbound23:25:376
478011993533,2cyclictest722391-21kworker/u16:2+events_unbound21:52:476
478011993533,2cyclictest722391-21kworker/u16:2+events_unbound21:52:476
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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