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2026-05-08 - 03:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Fri May 08, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29047232980,1sleep72904722-21cut21:38:527
32719032650,1sleep60-21swapper/600:10:136
2590671994947,2cyclictest3163135-21kworker/u16:2+events_unbound23:28:556
31497412460,0sleep60-21swapper/623:19:006
2590671994643,2cyclictest3028739-21kworker/u16:1+flush-8:023:03:436
2590671994643,2cyclictest2632810-21kworker/u16:2+events_unbound19:53:556
259017724636,7sleep50-21swapper/519:05:545
2590671994543,2cyclictest3285829-21kworker/u16:1+events_unbound00:33:566
2590673994443,0cyclictest0-21swapper/720:18:427
2590671994442,2cyclictest2885657-21kworker/u16:2+events_unbound21:44:006
2590671994442,2cyclictest2709407-21kworker/u16:1+flush-8:020:43:576
259029124333,7sleep40-21swapper/419:07:294
2590671994236,6cyclictest3163135-21kworker/u16:2+events_unbound00:29:346
2590671994038,2cyclictest3308074-21kworker/u16:0+events_unbound00:27:586
2590671994038,2cyclictest3163135-21kworker/u16:2+events_unbound23:50:116
2590671994038,2cyclictest3163135-21kworker/u16:2+events_unbound23:43:446
2590671994038,2cyclictest3149262-21kworker/u16:0+events_unbound23:37:156
2590671993937,2cyclictest2946610-21kworker/u16:0+events_unbound22:51:346
25903322395,29sleep70-21swapper/719:08:047
2590673993836,1cyclictest0-21swapper/720:33:437
2590673993835,2cyclictest3295099-21smartctl00:19:017
2590673993835,2cyclictest2749165-21perl20:28:427
2590671993837,1cyclictest2859899-21kworker/u16:0+events_unbound21:23:536
2590671993836,2cyclictest3176652-21kworker/u16:3+events_unbound23:40:156
2590671993836,2cyclictest3176652-21kworker/u16:3+events_unbound00:08:146
2590671993836,2cyclictest3163135-21kworker/u16:2+events_unbound23:28:026
2590673993736,0cyclictest0-21swapper/700:23:427
2590671993735,2cyclictest3176652-21kworker/u16:3+events_unbound00:18:516
2590671993735,2cyclictest2946610-21kworker/u16:0+events_unbound22:36:116
2590671993735,2cyclictest2946610-21kworker/u16:0+events_unbound22:04:356
2590671993735,2cyclictest2885657-21kworker/u16:2+events_unbound22:26:546
2590671993634,2cyclictest3237764-21kworker/u16:4+events_unbound00:02:016
2590671993634,2cyclictest3115975-21kworker/u16:4+events_unbound23:16:426
2590671993634,2cyclictest3115975-21kworker/u16:4+events_unbound23:11:596
2590671993634,2cyclictest2946610-21kworker/u16:0+events_unbound22:46:426
2590671993634,2cyclictest2946610-21kworker/u16:0+events_unbound22:21:026
2590671993634,2cyclictest2946610-21kworker/u16:0+events_unbound22:16:586
2590671993634,2cyclictest2885657-21kworker/u16:2+events_unbound21:52:076
2590671993634,2cyclictest2825011-21kworker/u16:2+events_unbound21:19:016
2590673993534,0cyclictest0-21swapper/723:38:437
2590673993532,2cyclictest2955189-21ntpq21:58:557
2590671993533,2cyclictest2872348-21kworker/u16:3+events_unbound21:33:196
2590671993533,2cyclictest2872348-21kworker/u16:3+events_unbound21:33:196
2590671993533,2cyclictest2709407-21kworker/u16:1+events_unbound20:53:276
2590671993533,2cyclictest2709407-21kworker/u16:1+events_unbound20:53:276
2590671993533,2cyclictest2690838-21kworker/u16:3+events_unbound19:58:546
2590671993533,2cyclictest2632810-21kworker/u16:2+flush-8:019:38:456
2590671993532,2cyclictest2690838-21kworker/u16:3+flush-8:020:23:446
2590660993532,2cyclictest3163135-21kworker/u16:2+flush-8:023:28:514
2590673993431,2cyclictest3252910-21kthreadcore00:03:467
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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