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2026-05-26 - 12:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Tue May 26, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17234712990,1sleep71723470-21sendmail_mailtr23:47:447
1094362999996,2cyclictest1678123-21kworker/u16:1+flush-8:023:58:516
109382825444,7sleep50-21swapper/519:03:445
1094362994846,2cyclictest1174993-21kworker/u16:4+events_unbound20:12:466
109385424433,8sleep40-21swapper/419:04:074
1094357994038,2cyclictest1075335-21kworker/u16:2+events_unbound19:12:325
1094357993937,2cyclictest1690507-21kworker/u16:2+events_unbound00:17:305
10857252393,30sleep70-21swapper/719:02:337
1094357993834,3cyclictest1174993-21kworker/u16:4+events_unbound19:57:315
1094364993734,2cyclictest1421971-21ntp_states21:42:427
1094362993734,2cyclictest1364773-21kworker/u16:2+events_unbound23:23:346
1094362993633,2cyclictest1364773-21kworker/u16:2+events_unbound21:39:036
109404723626,7sleep60-21swapper/619:06:506
1094364993529,5cyclictest1352629-21latency_hist21:17:167
1094364993529,5cyclictest1352629-21latency_hist21:17:167
1094362993533,2cyclictest1422596-21kworker/u16:1+flush-8:022:49:546
1094362993533,2cyclictest1349758-21kworker/u16:3+events_unbound21:25:186
1094354993533,2cyclictest1126888-21kworker/u16:0+events_unbound19:32:304
1094362993432,2cyclictest1690507-21kworker/u16:2+events_unbound00:04:116
1094362993432,2cyclictest1349758-21kworker/u16:3+events_unbound21:16:156
1094362993432,2cyclictest1349758-21kworker/u16:3+events_unbound21:16:156
1094357993432,2cyclictest1318919-21kworker/u16:2+events_unbound21:12:425
1094357993432,2cyclictest1318919-21kworker/u16:2+events_unbound21:12:425
1094357993432,2cyclictest1075335-21kworker/u16:2+events_unbound19:07:415
1094357993331,2cyclictest1241297-21kworker/u16:1+events_unbound20:37:415
1094362993230,2cyclictest1364773-21kworker/u16:2+events_unbound21:51:476
1094357993230,2cyclictest1602812-21kworker/u16:0+events_unbound23:02:295
1094357993230,2cyclictest1449183-21kworker/u16:3+flush-8:022:02:425
1094354993230,2cyclictest1449183-21kworker/u16:3+events_unbound22:27:424
1094362993129,2cyclictest1422596-21kworker/u16:1+events_unbound21:56:386
1094362993129,2cyclictest1422596-21kworker/u16:1+events_unbound21:56:386
109436499300,28cyclictest827-21dbus-daemon19:22:177
1094362993028,2cyclictest1602812-21kworker/u16:0+flush-8:023:19:466
1094362993028,2cyclictest1422596-21kworker/u16:1+events_unbound21:46:546
1094362993028,2cyclictest1364773-21kworker/u16:2+events_unbound23:04:546
1094362993028,2cyclictest1174993-21kworker/u16:4+events_unbound21:28:226
1094357993028,2cyclictest1241297-21kworker/u16:1+events_unbound20:32:445
1094357993028,2cyclictest1174993-21kworker/u16:4+events_unbound20:22:465
1094354993028,2cyclictest1364773-21kworker/u16:2+events_unbound22:32:434
1094354993028,2cyclictest1364773-21kworker/u16:2+events_unbound22:32:434
1094354993028,2cyclictest1174993-21kworker/u16:4+events_unbound20:57:394
1094362992927,2cyclictest1422596-21kworker/u16:1+events_unbound21:59:386
1094362992927,2cyclictest1174993-21kworker/u16:4+events_unbound21:34:476
1094357992927,2cyclictest1364773-21kworker/u16:2+events_unbound22:42:395
1094357992927,2cyclictest1241297-21kworker/u16:1+events_unbound20:27:395
1094354992927,2cyclictest1174993-21kworker/u16:4+events_unbound19:57:454
1094354992927,2cyclictest1075334-21kworker/u16:1+flush-8:019:42:414
1094354992927,2cyclictest1075334-21kworker/u16:1+flush-8:019:42:414
1094362992826,2cyclictest1690507-21kworker/u16:2+events_unbound23:49:476
1094362992826,2cyclictest1449183-21kworker/u16:3+events_unbound22:22:146
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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