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2026-05-14 - 21:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Thu May 14, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6509552940,1sleep7650954-21cut07:08:157
650521995149,2cyclictest1019520-21kworker/u16:3+flush-8:011:58:275
65021124736,7sleep50-21swapper/507:07:425
650521994644,2cyclictest1252298-21kworker/u16:0+events_unbound12:28:305
650521994644,2cyclictest1252298-21kworker/u16:0+events_unbound12:28:305
6501462415,31sleep70-21swapper/707:06:477
650521993937,2cyclictest1019520-21kworker/u16:3+events_unbound12:21:085
650521993836,2cyclictest982179-21kworker/u16:2+events_unbound10:00:165
650521993836,2cyclictest1019520-21kworker/u16:3+events_unbound10:56:195
650521993836,2cyclictest1006014-21kworker/u16:0+events_unbound10:31:035
650521993835,2cyclictest827135-21kworker/u16:4+events_unbound09:23:315
65017423828,7sleep40-21swapper/407:07:094
650521993735,2cyclictest865829-21kworker/u16:0+events_unbound09:33:045
650521993735,2cyclictest1252298-21kworker/u16:0+events_unbound12:33:215
650521993735,2cyclictest1201921-21kworker/u16:1+events_unbound11:26:315
650521993735,2cyclictest1019520-21kworker/u16:3+flush-8:012:05:035
650521993735,2cyclictest1019520-21kworker/u16:3+events_unbound12:23:525
650521993735,2cyclictest1019520-21kworker/u16:3+events_unbound12:17:555
650521993735,2cyclictest1019520-21kworker/u16:3+events_unbound10:45:155
650526993632,3cyclictest1387323-21/usr/sbin/munin12:33:177
650521993634,2cyclictest865829-21kworker/u16:0+flush-8:009:29:045
650521993634,2cyclictest1201921-21kworker/u16:1+events_unbound12:09:275
650521993634,2cyclictest1142164-21kworker/u16:4+events_unbound11:05:525
650521993634,2cyclictest1019520-21kworker/u16:3+events_unbound10:42:365
650521993633,2cyclictest1019520-21kworker/u16:3+events_unbound10:08:035
650526993529,5cyclictest1203223-21latency_hist11:18:027
650521993533,2cyclictest982383-21kworker/u16:3+events_unbound09:53:555
650521993533,2cyclictest982179-21kworker/u16:2+flush-8:009:51:355
650521993533,2cyclictest982179-21kworker/u16:2+events_unbound10:05:485
650521993533,2cyclictest865829-21kworker/u16:0+events_unbound09:45:195
650521993533,2cyclictest865829-21kworker/u16:0+events_unbound09:45:195
650521993533,2cyclictest1201921-21kworker/u16:1+events_unbound11:45:075
650521993533,2cyclictest1176750-21kworker/u16:0+events_unbound11:14:475
650521993533,2cyclictest1142164-21kworker/u16:4+flush-8:011:09:555
650521993533,2cyclictest1142164-21kworker/u16:4+events_unbound11:00:005
650521993533,2cyclictest1019520-21kworker/u16:3+flush-8:011:51:035
650521993533,2cyclictest1019520-21kworker/u16:3+events_unbound11:31:085
650521993432,2cyclictest856216-21kworker/u16:1+events_unbound09:10:325
650521993432,2cyclictest1056677-21kworker/u16:1+events_unbound10:24:165
650521993432,2cyclictest1019520-21kworker/u16:3+flush-8:010:19:355
650521993432,2cyclictest1019520-21kworker/u16:3+events_unbound10:33:435
650521993431,2cyclictest578190-21kworker/u16:0+flush-8:007:28:045
13701742340,1chrt1370175-21kthreadcore12:23:247
650521993331,2cyclictest856216-21kworker/u16:1+events_unbound09:20:245
650521993331,2cyclictest1142164-21kworker/u16:4+events_unbound11:21:205
650521993331,2cyclictest1019520-21kworker/u16:3+events_unbound11:57:515
650521993331,2cyclictest1019520-21kworker/u16:3+events_unbound11:42:565
650521993230,2cyclictest1142164-21kworker/u16:4+events_unbound11:34:045
650521993230,2cyclictest1056677-21kworker/u16:1+events_unbound10:50:515
650521993230,2cyclictest1019520-21kworker/u16:3+events_unbound10:15:565
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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