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2026-05-09 - 18:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sat May 09, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29542862590,1sleep50-21swapper/510:44:475
2477140994542,2cyclictest2931865-21/usr/sbin/munin10:38:227
247678624432,8sleep40-21swapper/407:07:324
2477136994239,2cyclictest2519410-21kworker/u16:2+flush-8:007:53:526
24766842422,32sleep70-21swapper/707:06:067
2477127994038,2cyclictest2990941-21kworker/u16:4+events_unbound11:56:454
2477136993937,2cyclictest2835177-21kworker/u16:0+events_unbound10:07:016
2477140993836,1cyclictest2966378-21ssh10:49:287
2477140993836,1cyclictest2711756-21diskmemload12:09:287
2477136993836,2cyclictest3112955-21kworker/u16:2+events_unbound12:12:256
2477127993836,2cyclictest2567424-21kworker/u16:1+events_unbound08:28:454
2477136993735,2cyclictest3015290-21kworker/u16:2+events_unbound11:10:526
2477136993735,2cyclictest2835177-21kworker/u16:0+events_unbound10:19:576
2477136993735,2cyclictest2772809-21kworker/u16:1+flush-8:010:55:246
2477136993735,2cyclictest2772809-21kworker/u16:1+events_unbound10:30:176
2477136993735,2cyclictest2519410-21kworker/u16:2+flush-8:009:41:416
2477134993736,1cyclictest14150irq/27-ahci[0000:00:1f.2]10:59:255
2477136993634,2cyclictest3112955-21kworker/u16:2+events_unbound12:16:206
2477136993634,2cyclictest3078789-21kworker/u16:1+events_unbound11:42:086
2477136993634,2cyclictest2835177-21kworker/u16:0+events_unbound10:46:286
2477136993634,2cyclictest2772809-21kworker/u16:1+flush-8:009:51:456
2477136993634,2cyclictest2772809-21kworker/u16:1+events_unbound09:58:216
2477136993634,2cyclictest2567424-21kworker/u16:1+events_unbound08:28:476
2477136993633,2cyclictest3138769-21kworker/u16:0+events_unbound12:19:006
2477127993634,2cyclictest3152087-21kworker/u16:1+events_unbound12:09:374
247672123626,7sleep60-21swapper/607:06:376
2477140993534,0cyclictest0-21swapper/709:54:137
2477140993533,1cyclictest2992499-21ssh11:02:127
2477140993532,2cyclictest2604485-21kthreadcore08:08:457
2477140993531,3cyclictest2795109-21ssh09:39:057
2477136993533,2cyclictest3138769-21kworker/u16:0+events_unbound12:32:086
2477136993533,2cyclictest3078789-21kworker/u16:1+events_unbound11:59:536
2477136993533,2cyclictest3015290-21kworker/u16:2+events_unbound11:19:246
2477136993533,2cyclictest2835177-21kworker/u16:0+events_unbound10:50:056
2477136993533,2cyclictest2772809-21kworker/u16:1+flush-8:009:37:256
2477136993533,2cyclictest2772809-21kworker/u16:1+events_unbound10:40:526
2477136993533,2cyclictest2519410-21kworker/u16:2+events_unbound09:27:256
2477127993532,2cyclictest2835177-21kworker/u16:0+events_unbound10:18:254
2477136993432,2cyclictest2772809-21kworker/u16:1+events_unbound10:35:456
2477127993432,2cyclictest2809183-21kworker/u16:3+events_unbound10:18:004
2477127993432,2cyclictest2772809-21kworker/u16:1+flush-8:011:06:204
2477127993432,2cyclictest2772809-21kworker/u16:1+flush-8:011:06:204
2477127993432,2cyclictest2519410-21kworker/u16:2+flush-8:009:39:484
2477140993332,0cyclictest0-21swapper/711:20:327
2477140993332,0cyclictest0-21swapper/710:42:297
2477140993332,0cyclictest0-21swapper/710:00:487
2477140993331,1cyclictest2979059-21ssh10:55:127
2477140993331,1cyclictest2857000-21ssh10:05:297
2477140993330,1cyclictest3077869-21sh11:36:417
2477136993331,2cyclictest3152087-21kworker/u16:1+events_unbound12:36:556
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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