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2026-04-06 - 02:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Apr 06, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
341922621020,0sleep50-21swapper/500:17:335
341922621020,0sleep50-21swapper/500:17:335
29570612970,1sleep72957063-21tr21:02:447
271713599590,57cyclictest650-21systemd-journal23:22:217
2717126995754,2cyclictest3319470-21kworker/u16:5+flush-8:023:37:355
271669625746,8sleep60-21swapper/619:00:336
2717126995451,2cyclictest3358796-21kworker/u16:2+events_unbound00:02:235
2717126995250,2cyclictest2807197-21kworker/u16:0+flush-8:021:12:365
2717126995048,2cyclictest3358796-21kworker/u16:2+events_unbound00:12:515
2717126995048,2cyclictest2998276-21kworker/u16:0+events_unbound21:57:355
2717127994945,3cyclictest3319470-21kworker/u16:5+flush-8:023:57:206
2717126994947,2cyclictest2984048-21kworker/u16:1+events_unbound22:07:355
2717127994846,2cyclictest2726571-21kworker/u16:4+events_unbound19:17:216
2717126994846,2cyclictest2984048-21kworker/u16:1+events_unbound21:37:355
2717126994846,2cyclictest2984048-21kworker/u16:1+events_unbound21:37:355
2717126994846,2cyclictest2726571-21kworker/u16:4+flush-8:019:12:475
2717126994644,2cyclictest3310675-21kworker/u16:2+events_unbound23:32:475
2717135994539,5cyclictest2883207-21latency_hist20:27:217
2717126994543,2cyclictest3166637-21kworker/u16:3+flush-8:022:37:215
2717126994543,2cyclictest2962087-21kworker/u16:5+events_unbound21:32:475
2717135994439,4cyclictest3394397-21latency_hist00:07:217
2717127994442,2cyclictest2962087-21kworker/u16:5+events_unbound22:12:206
2717127994441,2cyclictest2962087-21kworker/u16:5+flush-8:022:17:356
2717126994442,2cyclictest3106233-21kworker/u16:2+events_unbound22:57:115
2717126994442,2cyclictest3106233-21kworker/u16:2+events_unbound22:57:115
2717126994439,2cyclictest2807197-21kworker/u16:0+events_unbound20:37:355
2717127994341,2cyclictest3416133-21kworker/u16:4+events_unbound00:22:356
2717127994341,2cyclictest2962087-21kworker/u16:5+flush-8:021:12:216
2717127994340,2cyclictest2635520-21kworker/u16:3+events_unbound19:42:366
2717127994339,3cyclictest2746491-21kworker/u16:1+flush-8:019:37:216
2717126994341,2cyclictest3358796-21kworker/u16:2+events_unbound00:01:195
2717126994341,2cyclictest3213374-21kworker/u16:4+events_unbound23:09:045
2717126994340,2cyclictest2962087-21kworker/u16:5+events_unbound21:22:345
2717126994240,2cyclictest3213153-21kworker/u16:3+events_unbound23:16:515
2717126994239,2cyclictest3416132-21kworker/u16:3+events_unbound00:22:235
271668524232,7sleep40-21swapper/419:00:224
271666824232,7sleep50-21swapper/519:00:075
27117922423,32sleep70-21swapper/718:57:457
2717127994138,2cyclictest3213374-21kworker/u16:4+events_unbound23:12:396
2717127994138,2cyclictest3213153-21kworker/u16:3+events_unbound23:22:396
2717126994139,2cyclictest3213374-21kworker/u16:4+events_unbound23:04:035
2717126994139,2cyclictest2984048-21kworker/u16:1+events_unbound21:47:465
2717126994139,2cyclictest2984048-21kworker/u16:1+events_unbound21:29:485
2717126994139,2cyclictest2962086-21kworker/u16:4+events_unbound21:08:595
2717126994038,2cyclictest2998276-21kworker/u16:0+events_unbound21:57:195
2717126994038,2cyclictest2984048-21kworker/u16:1+events_unbound22:41:275
2717126994038,2cyclictest2864101-21kworker/u16:1+events_unbound21:03:445
2717126994037,2cyclictest2787685-21kworker/u16:4+events_unbound20:07:355
2717126994037,2cyclictest2746491-21kworker/u16:1+flush-8:019:47:365
2717127993937,2cyclictest3247878-21kworker/u16:0+flush-8:023:03:166
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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