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2025-12-02 - 20:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Tue Dec 02, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
377339025949,7sleep50-21swapper/515:19:305
3773948995553,2cyclictest3898482-21kworker/u16:2+events_unbound16:57:516
377341925419,30sleep70-21swapper/715:19:567
3773948994441,3cyclictest3970246-21kworker/u16:5+flush-8:017:27:516
377394999410,39cyclictest4130964-21latency_hist18:17:517
3773944994138,2cyclictest88584-21kworker/u16:2+flush-8:019:53:135
3773949994035,4cyclictest4191451-21latency_hist18:47:517
377394999380,36cyclictest3888715-21latency_hist16:17:527
377352523828,7sleep40-21swapper/415:21:224
3773949993734,2cyclictest4090621-21latency_hist17:57:527
3773948993735,2cyclictest4020308-21kworker/u16:2+flush-8:017:29:296
3773944993734,2cyclictest3773446-21kworker/u16:1+events_unbound15:22:545
3773949993635,0cyclictest0-21swapper/719:43:057
3773949993529,5cyclictest68579-21latency_hist19:22:517
3773944993533,2cyclictest98913-21kworker/u16:1+events_unbound20:08:155
3773949993428,5cyclictest589235-21systemd-journal16:04:117
3773944993431,2cyclictest3868596-21kworker/u16:0+events_unbound16:48:105
377351823323,7sleep60-21swapper/615:21:166
3773944993230,2cyclictest168420-21kworker/u16:4+flush-8:020:28:145
2486582320,1chrt248661-21kthreadcore20:48:157
3773944993129,2cyclictest26862-21kworker/u16:5+flush-8:019:28:225
3773937993128,2cyclictest98913-21kworker/u16:1+flush-8:020:08:164
3773949993025,4cyclictest3929022-21latency_hist16:37:517
3773949993024,5cyclictest4120875-21latency_hist18:12:517
377394999300,28cyclictest209744-21latency_hist20:32:517
3773944993028,2cyclictest4080956-21kworker/u16:0+flush-8:018:08:215
3773944993028,2cyclictest26862-21kworker/u16:5+events_unbound19:08:215
3773944993027,3cyclictest3969718-21kworker/u16:4+flush-8:016:58:075
3773944993026,3cyclictest3797749-21kworker/u16:3+flush-8:015:42:525
3773948992927,2cyclictest3797750-21kworker/u16:4+flush-8:015:43:266
3773948992927,2cyclictest3797749-21kworker/u16:3+events_unbound15:53:176
3773937992927,2cyclictest168420-21kworker/u16:4+flush-8:020:43:224
3773948992825,2cyclictest88584-21kworker/u16:2+flush-8:019:48:066
3773948992825,2cyclictest3797749-21kworker/u16:3+flush-8:015:38:056
3773944992826,2cyclictest4080956-21kworker/u16:0+flush-8:019:13:065
3773944992825,2cyclictest7467-21kworker/u16:1+flush-8:018:53:125
3773949992725,1cyclictest0-21swapper/718:18:097
3773948992724,2cyclictest98913-21kworker/u16:1+events_unbound20:12:516
3773944992725,2cyclictest88584-21kworker/u16:2+flush-8:019:43:215
3773944992725,2cyclictest3773446-21kworker/u16:1+events_unbound15:28:205
3773944992724,2cyclictest3832787-21kworker/u16:1+flush-8:016:18:075
3773944992723,3cyclictest3832787-21kworker/u16:1+flush-8:015:58:235
3773944992723,3cyclictest3832787-21kworker/u16:1+flush-8:015:58:235
3773949992625,0cyclictest0-21swapper/717:33:157
3773944992624,2cyclictest3832787-21kworker/u16:1+flush-8:016:13:185
3773937992624,2cyclictest3970246-21kworker/u16:5+flush-8:017:29:214
3773948992523,2cyclictest3784069-21kworker/u16:2+flush-8:015:28:076
3773944992523,2cyclictest4020308-21kworker/u16:2+flush-8:018:48:225
3773948992421,2cyclictest4130751-21kworker/u16:1+flush-8:018:38:176
3773944992422,2cyclictest98913-21kworker/u16:1+flush-8:019:52:515
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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