You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-18 - 17:56
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Tue Aug 18, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3309000997068,2cyclictest3409640-21kworker/u16:4+events_unbound08:22:046
330851525746,7sleep40-21swapper/407:05:104
3309000995249,2cyclictest3341696-21kworker/u16:1+events_unbound07:47:566
3308997995147,4cyclictest3922661-21kworker/u16:1+flush-8:011:47:425
3308997995146,5cyclictest3740455-21kworker/u16:1+flush-8:010:37:425
3308995995149,2cyclictest3535740-21kworker/u16:4+events_unbound09:13:164
3308995994947,2cyclictest3526332-21kworker/u16:3+flush-8:009:03:084
3308995994744,2cyclictest3935150-21kworker/u16:2+flush-8:012:23:074
330844924636,7sleep50-21swapper/507:04:155
3309000994543,2cyclictest3922661-21kworker/u16:1+events_unbound12:32:566
3309000994542,2cyclictest3680132-21kworker/u16:5+flush-8:010:23:106
3309000994542,2cyclictest3567767-21kworker/u16:0+flush-8:009:47:566
3308997994541,3cyclictest3740455-21kworker/u16:1+flush-8:010:28:005
3308995994543,2cyclictest3863585-21kworker/u16:5+flush-8:011:33:144
3309000994442,2cyclictest3400098-21kworker/u16:2+events_unbound08:07:426
3308995994442,2cyclictest3800681-21kworker/u16:2+events_unbound11:03:144
3308995994442,2cyclictest3516363-21kworker/u16:1+events_unbound09:08:154
3308995994441,2cyclictest3341696-21kworker/u16:1+events_unbound07:52:594
3308995994341,2cyclictest3680132-21kworker/u16:5+flush-8:010:33:204
3309001994241,0cyclictest0-21swapper/709:53:187
3309001994241,0cyclictest0-21swapper/709:48:117
3309001994239,2cyclictest3860086-21ntpq11:13:107
3309000994240,2cyclictest3800681-21kworker/u16:2+flush-8:010:53:026
3308995994240,2cyclictest3535740-21kworker/u16:4+events_unbound09:23:104
3308995994240,2cyclictest3535740-21kworker/u16:4+events_unbound09:23:104
33085492427,30sleep70-21swapper/707:05:377
3309000994138,2cyclictest3468449-21kworker/u16:0+events_unbound08:27:566
3308995994139,2cyclictest4023690-21kworker/u16:3+events_unbound12:28:104
3309000994037,2cyclictest3567767-21kworker/u16:0+events_unbound09:27:576
3309000994037,2cyclictest3535740-21kworker/u16:4+flush-8:009:13:036
3308995994038,2cyclictest3680132-21kworker/u16:5+events_unbound10:48:094
3308995994038,2cyclictest3680131-21kworker/u16:4+events_unbound10:07:594
3308995994038,2cyclictest3516363-21kworker/u16:1+flush-8:009:57:584
3308995994037,2cyclictest3740455-21kworker/u16:1+flush-8:010:38:034
3309001993938,0cyclictest0-21swapper/707:43:147
3309001993934,3cyclictest3584100-21kthreadcore09:23:047
3309001993934,3cyclictest3584100-21kthreadcore09:23:047
3309000993937,2cyclictest3644324-21kworker/u16:3+events_unbound10:03:106
3309000993937,2cyclictest3644324-21kworker/u16:3+events_unbound10:03:106
3308995993937,2cyclictest3935150-21kworker/u16:2+events_unbound11:58:144
3308995993937,2cyclictest3863585-21kworker/u16:5+flush-8:011:27:564
3308995993937,2cyclictest3618297-21kworker/u16:2+events_unbound09:43:164
3308995993936,2cyclictest3341696-21kworker/u16:1+events_unbound07:57:444
3309001993836,1cyclictest0-21swapper/710:08:147
3309001993831,5cyclictest648-21systemd-journal10:32:427
3309000993836,2cyclictest3922661-21kworker/u16:1+events_unbound12:03:526
3309000993836,2cyclictest3922661-21kworker/u16:1+events_unbound12:03:526
3309000993836,2cyclictest3516363-21kworker/u16:1+flush-8:009:18:126
3308997993836,2cyclictest3727958-21kworker/u16:0+events_unbound10:42:425
3308995993836,2cyclictest3922661-21kworker/u16:1+events_unbound12:11:244
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional