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2026-05-23 - 04:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sat May 23, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
132748525948,7sleep50-21swapper/519:02:355
1336917995754,2cyclictest1435640-21ntpq19:52:517
133661924737,7sleep40-21swapper/419:07:164
1336912994543,2cyclictest1919338-21kworker/u16:0+flush-8:000:07:525
13365382432,36sleep70-21swapper/719:06:067
628089400,33rtkit-daemon0-21swapper/619:03:256
1336910994038,2cyclictest1666027-21kworker/u16:0+events_unbound22:11:454
1336917993934,4cyclictest1861533-21latency_hist23:07:287
1336917993836,1cyclictest2053856-21sh00:25:397
1336917993836,1cyclictest1763033-21ssh22:24:247
1336917993736,0cyclictest0-21swapper/723:08:247
1336910993734,2cyclictest1666027-21kworker/u16:0+flush-8:021:57:394
1336917993634,1cyclictest1801585-21ssh22:42:367
1336917993634,1cyclictest1571062-21diskmemload23:15:457
1336910993634,2cyclictest1726103-21kworker/u16:1+events_unbound22:30:194
1336917993534,0cyclictest0-21swapper/723:19:117
1336917993533,1cyclictest1920289-21ssh23:29:157
1336916993533,2cyclictest1883364-21kworker/u16:1+events_unbound00:17:116
1336910993533,2cyclictest1919338-21kworker/u16:0+events_unbound00:02:244
1336917993433,0cyclictest0-21swapper/723:41:357
1336917993433,0cyclictest0-21swapper/721:18:247
1336917993433,0cyclictest0-21swapper/700:20:117
1336917993429,4cyclictest1970308-21latency_hist23:52:277
1336910993432,2cyclictest1919338-21kworker/u16:0+events_unbound23:41:274
1336910993432,2cyclictest1919338-21kworker/u16:0+events_unbound00:10:524
1336910993432,2cyclictest1919338-21kworker/u16:0+events_unbound00:06:364
1336910993432,2cyclictest1883364-21kworker/u16:1+events_unbound23:55:554
1336910993432,2cyclictest1883364-21kworker/u16:1+events_unbound23:55:554
1336910993432,2cyclictest1740112-21kworker/u16:2+flush-8:022:33:154
1336910993432,2cyclictest1740112-21kworker/u16:2+events_unbound22:50:394
1336917993332,0cyclictest0-21swapper/723:25:477
1336917993332,0cyclictest0-21swapper/721:08:367
1336917993332,0cyclictest0-21swapper/700:33:447
1336917993332,0cyclictest0-21swapper/700:02:117
1336916993331,2cyclictest1317902-21kworker/u16:3+flush-8:020:02:286
1336912993331,2cyclictest1883364-21kworker/u16:1+flush-8:023:57:115
1336912993331,2cyclictest1883364-21kworker/u16:1+flush-8:023:57:115
1336912993331,2cyclictest1834978-21kworker/u16:3+events_unbound22:57:235
1336912993331,2cyclictest1740112-21kworker/u16:2+flush-8:022:27:595
1336910993332,1cyclictest1619346-21kworker/u16:6+events_unbound21:40:044
1336917993231,0cyclictest0-21swapper/723:44:097
1336917993231,0cyclictest0-21swapper/722:18:287
1336917993231,0cyclictest0-21swapper/721:55:407
1336917993231,0cyclictest0-21swapper/721:35:367
1336917993231,0cyclictest0-21swapper/721:29:447
1336917993230,1cyclictest1571062-21diskmemload22:31:037
1336917993229,2cyclictest1666926-21ssh21:46:007
1336912993230,2cyclictest1666027-21kworker/u16:0+events_unbound22:04:395
1336910993230,2cyclictest1883364-21kworker/u16:1+flush-8:000:22:594
1336910993230,2cyclictest1446246-21kworker/u16:1+flush-8:020:52:234
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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