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2026-04-20 - 17:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Apr 20, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33004412640,1sleep73300443-21ssh10:05:267
292215025545,7sleep40-21swapper/407:06:154
292234924535,7sleep50-21swapper/507:09:055
2922695994438,5cyclictest3643468-21latency_hist12:29:367
2922695994235,5cyclictest635-21systemd-journal10:04:377
2922692994038,2cyclictest3361282-21kworker/u16:1+events_unbound11:14:376
29221222403,31sleep70-21swapper/707:05:547
2922695993933,5cyclictest3436812-21latency_hist11:04:387
2922690993633,2cyclictest3361282-21kworker/u16:1+flush-8:011:23:555
2922692993533,2cyclictest3388192-21kworker/u16:4+events_unbound12:24:556
2922690993533,2cyclictest3593641-21kworker/u16:1+events_unbound12:08:405
2922690993533,2cyclictest3546645-21kworker/u16:0+flush-8:012:00:555
2922690993533,2cyclictest3388192-21kworker/u16:4+flush-8:011:59:155
2922692993432,2cyclictest3593641-21kworker/u16:1+flush-8:012:30:476
2922690993432,2cyclictest3422491-21kworker/u16:3+events_unbound10:56:525
2922690993432,2cyclictest3388192-21kworker/u16:4+flush-8:011:45:355
2922690993432,2cyclictest3388192-21kworker/u16:4+flush-8:011:41:405
2922690993432,2cyclictest3277310-21kworker/u16:2+events_unbound10:08:035
2922690993432,2cyclictest3088576-21kworker/u16:2+flush-8:009:48:315
2922690993432,2cyclictest3088576-21kworker/u16:2+events_unbound09:28:485
2922692993331,2cyclictest3628849-21kworker/u16:0+flush-8:012:37:476
2922692993331,2cyclictest3628849-21kworker/u16:0+flush-8:012:37:476
2922692993331,2cyclictest3413392-21kworker/u16:0+events_unbound11:05:116
2922690993331,2cyclictest3593641-21kworker/u16:1+flush-8:012:18:325
2922690993331,2cyclictest3388192-21kworker/u16:4+events_unbound11:29:195
2922690993331,2cyclictest3361282-21kworker/u16:1+events_unbound11:13:565
2922690993331,2cyclictest3361282-21kworker/u16:1+events_unbound11:09:195
2922690993331,2cyclictest3302338-21kworker/u16:0+events_unbound10:26:475
2922690993331,2cyclictest3118539-21kworker/u16:0+events_unbound09:13:415
2922690993331,2cyclictest3088576-21kworker/u16:2+flush-8:009:23:125
2922692993230,2cyclictest3361282-21kworker/u16:1+events_unbound10:33:476
2922692993230,2cyclictest3361282-21kworker/u16:1+events_unbound10:33:476
2922692993230,2cyclictest3239482-21kworker/u16:4+flush-8:009:43:046
2922692993229,2cyclictest3388192-21kworker/u16:4+events_unbound12:04:396
2922690993230,2cyclictest3388192-21kworker/u16:4+flush-8:011:35:405
2922690993230,2cyclictest3315400-21kworker/u16:3+flush-8:010:43:085
2922690993230,2cyclictest3191969-21kworker/u16:0+flush-8:009:38:275
2922695993130,0cyclictest0-21swapper/711:55:557
2922690993129,2cyclictest3593641-21kworker/u16:1+flush-8:012:29:275
2922690993129,2cyclictest3522012-21kworker/u16:2+flush-8:012:10:595
2922690993129,2cyclictest3108744-21kworker/u16:1+flush-8:009:54:525
2922692993028,2cyclictest3375732-21kworker/u16:2+flush-8:010:39:436
2922692993028,2cyclictest3361282-21kworker/u16:1+flush-8:010:50:126
2922692993028,2cyclictest3302338-21kworker/u16:0+events_unbound10:14:516
2922692993028,2cyclictest3108744-21kworker/u16:1+events_unbound09:54:036
2922692993028,2cyclictest2875279-21kworker/u16:1+flush-8:007:29:326
2922692993027,2cyclictest3388192-21kworker/u16:4+flush-8:011:39:476
2922690993028,2cyclictest3643853-21kworker/u16:3+flush-8:012:38:205
2922690993028,2cyclictest3643853-21kworker/u16:3+flush-8:012:38:205
2922690993028,2cyclictest3388192-21kworker/u16:4+events_unbound12:21:515
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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