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2026-06-08 - 22:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Jun 08, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
360978725847,8sleep50-21swapper/507:06:225
360951825847,7sleep40-21swapper/407:02:364
3610075994846,2cyclictest3528114-21kworker/u16:0+flush-8:007:16:486
3610083994439,4cyclictest3680920-21latency_hist07:41:227
36097502414,32sleep70-21swapper/707:05:527
3610075993836,2cyclictest82144-21kworker/u16:1+events_unbound12:24:336
3610075993836,2cyclictest3973314-21kworker/u16:4+events_unbound10:06:216
3610075993832,6cyclictest3868097-21kworker/u16:0+events_unbound09:44:406
3610075993735,2cyclictest95288-21kworker/u16:2+events_unbound12:09:486
3610075993735,2cyclictest4167042-21kworker/u16:1+events_unbound11:22:366
3610075993735,2cyclictest4143322-21kworker/u16:2+events_unbound11:12:176
3610075993634,2cyclictest4191177-21kworker/u16:2+events_unbound11:32:136
3610075993634,2cyclictest3973314-21kworker/u16:4+events_unbound10:50:376
3610075993634,2cyclictest3973314-21kworker/u16:4+events_unbound10:26:176
3610075993533,2cyclictest82144-21kworker/u16:1+events_unbound12:31:126
3610075993533,2cyclictest4142164-21kworker/u16:0+events_unbound11:17:536
3610075993533,2cyclictest4119119-21kworker/u16:3+events_unbound11:08:576
3610066993533,2cyclictest3868097-21kworker/u16:0+events_unbound10:26:374
3610075993432,2cyclictest4142164-21kworker/u16:0+events_unbound11:29:176
3610075993432,2cyclictest3973314-21kworker/u16:4+events_unbound11:38:536
3610075993432,2cyclictest3962528-21kworker/u16:3+events_unbound09:55:016
3610075993432,2cyclictest3962528-21kworker/u16:3+events_unbound09:55:016
3610075993432,2cyclictest3928549-21kworker/u16:1+events_unbound09:57:496
3610075993432,2cyclictest3815363-21kworker/u16:2+flush-8:009:07:146
3610075993432,2cyclictest3681304-21kworker/u16:1+events_unbound09:12:256
3610075993432,2cyclictest3681304-21kworker/u16:1+events_unbound09:12:256
3610075993432,2cyclictest25542-21kworker/u16:6+events_unbound12:18:246
3610075993432,2cyclictest25542-21kworker/u16:6+events_unbound12:15:456
3610075993432,2cyclictest154592-21kworker/u16:2+events_unbound12:32:486
3610075993331,2cyclictest3880524-21kworker/u16:3+events_unbound09:34:456
3610075993230,2cyclictest3973314-21kworker/u16:4+events_unbound10:59:016
3610075993230,2cyclictest3973314-21kworker/u16:4+events_unbound10:30:256
3610083993129,1cyclictest3844199-21diskmemload10:58:117
3610075993129,2cyclictest4085134-21kworker/u16:1+events_unbound10:52:426
3610075993129,2cyclictest3973314-21kworker/u16:4+events_unbound11:54:416
3610075993129,2cyclictest3868097-21kworker/u16:0+events_unbound10:41:126
3610075993129,2cyclictest3868097-21kworker/u16:0+events_unbound10:41:126
3610075993129,2cyclictest3868097-21kworker/u16:0+events_unbound10:15:096
3610075993129,2cyclictest25542-21kworker/u16:6+events_unbound12:05:446
3610075993129,2cyclictest2180334-21kworker/u16:2+flush-8:007:11:276
3610070993128,3cyclictest4034856-21kworker/u16:2+flush-8:010:36:375
3610070993128,3cyclictest4034856-21kworker/u16:2+flush-8:010:36:375
361008399300,28cyclictest635-21systemd-journal07:26:237
3610075993028,2cyclictest3973314-21kworker/u16:4+events_unbound10:10:436
3610070993028,2cyclictest3528114-21kworker/u16:0+flush-8:007:56:375
3610066993027,2cyclictest2180334-21kworker/u16:2+events_unbound07:26:374
3610075992927,2cyclictest25542-21kworker/u16:6+events_unbound12:00:026
3610075992926,2cyclictest3528114-21kworker/u16:0+events_unbound07:36:246
3610070992927,2cyclictest82144-21kworker/u16:1+events_unbound12:24:515
3610070992927,2cyclictest3815363-21kworker/u16:2+events_unbound09:06:375
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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