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2026-01-12 - 10:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Jan 12, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
113763727463,8sleep40-21swapper/419:03:394
11365232562,48sleep70-21swapper/719:03:267
1138244994540,4cyclictest1863162-21latency_hist00:27:597
113789824232,7sleep60-21swapper/619:07:186
18429642410,1sleep60-21swapper/600:18:186
1138244994034,5cyclictest1789910-21latency_hist23:57:587
1138240993936,2cyclictest1545894-21kworker/u16:2+flush-8:023:48:236
1138244993529,5cyclictest650-21systemd-journal23:52:587
1138235993533,2cyclictest1545894-21kworker/u16:2+events_unbound00:13:275
1138235993533,2cyclictest1545894-21kworker/u16:2+events_unbound00:13:275
113782123525,7sleep50-21swapper/519:06:135
1138235993432,2cyclictest1589900-21kworker/u16:3+flush-8:000:33:245
1138235993432,2cyclictest1319773-21kworker/u16:2+events_unbound21:12:355
17903682330,1chrt1790370-21sh23:58:077
1138244993328,4cyclictest1306790-21latency_hist20:32:597
1138235993331,2cyclictest1589900-21kworker/u16:3+events_unbound23:26:105
1138235993331,2cyclictest1544113-21kworker/u16:1+events_unbound23:13:065
1138235993331,2cyclictest1411416-21kworker/u16:3+events_unbound22:11:305
1138235993331,2cyclictest1119860-21kworker/u16:2+events_unbound19:14:095
1138235993230,2cyclictest1544113-21kworker/u16:1+flush-8:023:30:195
1138235993230,2cyclictest1460629-21kworker/u16:0+events_unbound22:23:265
1138235993130,1cyclictest1411416-21kworker/u16:3+events_unbound21:56:025
1138235993129,2cyclictest1589900-21kworker/u16:3+flush-8:000:28:155
1138235993129,2cyclictest1589900-21kworker/u16:3+events_unbound00:20:235
1138235993128,2cyclictest1161360-21kworker/u16:4+events_unbound19:18:145
1138235993028,2cyclictest1589900-21kworker/u16:3+events_unbound23:36:065
1138235993028,2cyclictest1589900-21kworker/u16:3+events_unbound23:36:065
1138235993028,2cyclictest1589900-21kworker/u16:3+events_unbound23:00:305
1138235993028,2cyclictest1545894-21kworker/u16:2+events_unbound23:40:315
1138235993028,2cyclictest1545894-21kworker/u16:2+events_unbound22:50:355
1138235993028,2cyclictest1545894-21kworker/u16:2+events_unbound00:26:295
1138235993028,2cyclictest1319773-21kworker/u16:2+flush-8:021:43:425
1138235993028,2cyclictest1319773-21kworker/u16:2+events_unbound20:46:205
1138235993028,2cyclictest1319773-21kworker/u16:2+events_unbound20:40:285
1138235993028,2cyclictest1248896-21kworker/u16:1+events_unbound20:16:325
1138235993028,2cyclictest1219593-21kworker/u16:4+events_unbound20:03:205
1138235993028,2cyclictest1219593-21kworker/u16:4+events_unbound19:55:535
12781732290,1chrt1278175-21cpuspeed_turbos20:18:097
1138235992927,2cyclictest3817920-21kworker/u16:1+events_unbound19:40:485
1138235992927,2cyclictest3817920-21kworker/u16:1+events_unbound19:24:215
1138235992927,2cyclictest1799158-21kworker/u16:4+events_unbound00:01:555
1138235992927,2cyclictest1589900-21kworker/u16:3+flush-8:023:10:315
1138235992927,2cyclictest1589900-21kworker/u16:3+events_unbound23:51:105
1138235992927,2cyclictest1589900-21kworker/u16:3+events_unbound00:05:505
1138235992927,2cyclictest1545894-21kworker/u16:2+events_unbound22:47:305
1138235992927,2cyclictest1545894-21kworker/u16:2+events_unbound22:39:065
1138235992927,2cyclictest1411416-21kworker/u16:3+flush-8:022:16:155
1138235992927,2cyclictest1355329-21kworker/u16:1+flush-8:021:13:275
1138235992927,2cyclictest1277788-21kworker/u16:3+events_unbound20:26:535
1138235992927,2cyclictest1258602-21kworker/u16:2+events_unbound20:12:335
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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