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2026-08-06 - 05:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Thu Aug 06, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1541443994842,5cyclictest1958552-21latency_hist22:23:307
154085324712,30sleep70-21swapper/719:04:267
1541438994239,2cyclictest2003534-21kworker/u16:2+events_unbound23:53:316
1541429994139,2cyclictest1718966-21kworker/u16:0+events_unbound21:18:304
1541443994039,0cyclictest0-21swapper/720:39:007
1541429994037,2cyclictest1838242-21kworker/u16:1+events_unbound22:08:324
1541443993933,5cyclictest1994674-21latency_hist22:38:307
1541438993836,2cyclictest2163491-21kworker/u16:0+events_unbound00:16:326
1541429993836,2cyclictest2150288-21kworker/u16:3+events_unbound00:06:154
1541429993836,2cyclictest2150288-21kworker/u16:3+events_unbound00:06:154
154083023827,7sleep50-21swapper/519:04:085
1541438993735,2cyclictest2016899-21kworker/u16:3+events_unbound23:06:486
1541443993634,1cyclictest0-21swapper/723:27:597
1541443993634,1cyclictest0-21swapper/723:27:597
1541438993634,2cyclictest1946591-21kworker/u16:0+events_unbound22:35:286
1541438993634,2cyclictest1838242-21kworker/u16:1+events_unbound23:18:286
1541438993634,2cyclictest1690312-21kworker/u16:2+flush-8:020:38:546
1541429993633,2cyclictest1838242-21kworker/u16:1+events_unbound21:48:324
1541429993632,3cyclictest1790008-21kworker/u16:4+flush-8:021:23:304
1541443993534,0cyclictest0-21swapper/721:33:337
1541443993530,4cyclictest2079086-21latency_hist23:13:307
1541438993533,2cyclictest1811762-21kworker/u16:2+events_unbound21:25:566
1541438993533,2cyclictest1790008-21kworker/u16:4+events_unbound21:42:566
1541429993534,1cyclictest1838242-21kworker/u16:1+events_unbound22:04:164
1541429993533,2cyclictest2079128-21kworker/u16:0+events_unbound23:39:404
1541429993533,2cyclictest1946591-21kworker/u16:0+events_unbound22:19:564
1541429993533,2cyclictest1910512-21kworker/u16:4+events_unbound22:36:094
1541429993533,2cyclictest1838242-21kworker/u16:1+events_unbound22:51:164
1541429993532,3cyclictest1718966-21kworker/u16:0+events_unbound22:02:484
1541443993433,0cyclictest0-21swapper/723:21:287
1541443993432,1cyclictest1777957-21diskmemload22:26:487
1541438993432,2cyclictest2079128-21kworker/u16:0+events_unbound23:29:236
1541438993432,2cyclictest1838242-21kworker/u16:1+events_unbound21:46:566
1541429993432,2cyclictest2079128-21kworker/u16:0+flush-8:023:30:434
1541429993432,2cyclictest2003534-21kworker/u16:2+flush-8:022:44:164
1541429993432,2cyclictest2003534-21kworker/u16:2+flush-8:022:44:164
1541429993432,2cyclictest1838242-21kworker/u16:1+events_unbound23:24:594
1541429993432,2cyclictest1838242-21kworker/u16:1+events_unbound23:24:594
1541443993331,1cyclictest2042262-21ssh22:57:207
1541443993327,5cyclictest1574202-21latency_hist19:23:317
1541438993331,2cyclictest1838242-21kworker/u16:1+flush-8:022:48:036
1541438993331,2cyclictest1838242-21kworker/u16:1+flush-8:022:48:036
1541438993331,2cyclictest1838242-21kworker/u16:1+flush-8:022:41:446
1541438993330,2cyclictest1718966-21kworker/u16:0+flush-8:020:53:336
1541429993331,2cyclictest2235183-21kworker/u16:1+flush-8:000:30:274
1541429993331,2cyclictest2235183-21kworker/u16:1+events_unbound00:35:324
1541429993331,2cyclictest2150288-21kworker/u16:3+flush-8:023:48:084
1541429993331,2cyclictest2079128-21kworker/u16:0+events_unbound23:17:594
1541429993331,2cyclictest2003534-21kworker/u16:2+flush-8:022:42:364
1541429993331,2cyclictest2003534-21kworker/u16:2+flush-8:000:12:114
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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