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2025-12-11 - 19:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Thu Dec 11, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1608128995651,4cyclictest2055914-21latency_hist19:02:157
160764525443,8sleep40-21swapper/415:20:204
160762825343,7sleep60-21swapper/615:20:066
1608128994944,4cyclictest2015561-21latency_hist18:42:157
160764624737,7sleep50-21swapper/515:20:215
1608120994644,2cyclictest2096251-21kworker/u16:1+events_unbound19:43:476
1608119994541,3cyclictest1702649-21kworker/u16:0+flush-8:016:57:155
1608119994541,3cyclictest1702649-21kworker/u16:0+flush-8:016:57:155
160812899420,40cyclictest1874293-21latency_hist17:32:157
1608120994240,2cyclictest2178095-21kworker/u16:1+events_unbound20:44:466
1608112994239,2cyclictest2095830-21kworker/u16:0+flush-8:019:27:154
1608120994139,2cyclictest2015778-21kworker/u16:3+events_unbound19:20:266
1608128994035,4cyclictest1702830-21latency_hist16:07:157
1608120994038,2cyclictest2196815-21kworker/u16:0+events_unbound20:35:466
1608120994038,2cyclictest1702799-21kworker/u16:4+flush-8:019:09:466
1608120994038,2cyclictest1702799-21kworker/u16:4+flush-8:019:09:466
1608119994038,2cyclictest2196815-21kworker/u16:0+events_unbound20:36:455
1608119994037,3cyclictest2223216-21kworker/u16:2+flush-8:020:27:415
15982012403,31sleep70-21swapper/715:17:267
1608120993937,2cyclictest2178095-21kworker/u16:1+flush-8:020:37:506
1608120993937,2cyclictest2178095-21kworker/u16:1+flush-8:020:37:506
1608120993937,2cyclictest1929364-21kworker/u16:2+flush-8:018:08:036
1608120993937,2cyclictest1602630-21kworker/u16:0+flush-8:015:42:396
1608119993937,2cyclictest1702649-21kworker/u16:0+flush-8:016:07:425
1608119993937,2cyclictest1702649-21kworker/u16:0+flush-8:016:07:425
1608119993937,2cyclictest1557045-21kworker/u16:3+flush-8:015:22:455
1608119993937,2cyclictest1557045-21kworker/u16:3+flush-8:015:22:455
1608120993836,2cyclictest2186723-21kworker/u16:3+events_unbound20:10:266
1608120993836,2cyclictest1602630-21kworker/u16:0+events_unbound15:42:166
1608119993836,2cyclictest1631907-21kworker/u16:1+flush-8:015:42:465
1608120993735,2cyclictest2249164-21kworker/u16:2+events_unbound20:48:256
1608120993735,2cyclictest2096251-21kworker/u16:1+flush-8:019:32:446
1608120993735,2cyclictest1702799-21kworker/u16:4+flush-8:019:37:576
1608119993735,2cyclictest1929364-21kworker/u16:2+events_unbound18:23:445
1608119993735,2cyclictest1929364-21kworker/u16:2+events_unbound18:23:445
1608120993634,2cyclictest1904215-21kworker/u16:0+events_unbound18:44:466
1608120993634,2cyclictest1702649-21kworker/u16:0+flush-8:016:25:466
1608119993634,2cyclictest1929364-21kworker/u16:2+events_unbound18:44:445
1608119993634,2cyclictest1642057-21kworker/u16:3+events_unbound15:54:275
1608128993530,4cyclictest1823812-21latency_hist17:07:167
1608120993533,2cyclictest2166769-21kworker/u16:2+flush-8:020:02:156
1608120993533,2cyclictest2096252-21kworker/u16:5+events_unbound19:27:526
1608120993533,2cyclictest1702649-21kworker/u16:0+events_unbound16:07:436
1608120993533,2cyclictest1702649-21kworker/u16:0+events_unbound16:07:436
1608120993533,2cyclictest1607829-21kworker/u16:2+flush-8:016:12:416
1608119993533,2cyclictest2035811-21kworker/u16:1+flush-8:018:54:145
1608119993533,2cyclictest1904215-21kworker/u16:0+events_unbound18:12:145
1608119993532,2cyclictest1702799-21kworker/u16:4+events_unbound17:07:195
1608120993432,2cyclictest2207085-21kworker/u16:4+events_unbound20:16:496
1608120993432,2cyclictest1965133-21kworker/u16:1+events_unbound18:26:446
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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