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2026-07-10 - 22:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Fri Jul 10, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128466721000,1sleep50-21swapper/512:00:035
10212532980,1sleep71021254-21sh10:13:387
9284802970,1sleep7928483-21cut09:35:077
7688702970,1sleep7768871-21kthreadcore08:20:077
6140292830,6chrt0-21swapper/607:04:576
62298525419,30sleep70-21swapper/707:08:047
62301224636,7sleep50-21swapper/507:08:265
623394994341,2cyclictest1302695-21kworker/u16:0+events_unbound12:20:006
623394994239,2cyclictest1083121-21kworker/u16:2+events_unbound10:40:006
623394994037,2cyclictest785625-21kworker/u16:4+events_unbound08:40:166
623389994038,2cyclictest752714-21kworker/u16:2+events_unbound09:33:085
623394993937,2cyclictest922506-21kworker/u16:1+events_unbound09:54:036
623394993937,2cyclictest895343-21kworker/u16:0+events_unbound11:01:286
623389993937,2cyclictest960017-21kworker/u16:2+events_unbound09:57:535
623394993836,2cyclictest969092-21kworker/u16:3+events_unbound10:16:256
623394993836,2cyclictest895343-21kworker/u16:0+events_unbound10:24:446
623394993835,2cyclictest922506-21kworker/u16:1+events_unbound09:44:596
623394993835,2cyclictest922506-21kworker/u16:1+events_unbound09:44:596
623389993836,2cyclictest922506-21kworker/u16:1+events_unbound09:48:405
623389993836,2cyclictest922506-21kworker/u16:1+events_unbound09:48:405
623389993836,2cyclictest895343-21kworker/u16:0+events_unbound10:31:325
623394993735,2cyclictest972340-21kworker/u16:5+events_unbound10:00:286
623394993735,2cyclictest895343-21kworker/u16:0+events_unbound11:52:486
623394993735,2cyclictest895343-21kworker/u16:0+events_unbound11:52:486
623394993735,2cyclictest895343-21kworker/u16:0+events_unbound11:36:396
623394993735,2cyclictest895343-21kworker/u16:0+events_unbound11:09:006
623394993735,2cyclictest785625-21kworker/u16:4+events_unbound09:25:486
623394993735,2cyclictest752714-21kworker/u16:2+events_unbound09:17:286
623394993735,2cyclictest752714-21kworker/u16:2+events_unbound09:10:166
623394993735,2cyclictest1231668-21kworker/u16:1+events_unbound12:02:526
623394993735,2cyclictest1182387-21kworker/u16:4+events_unbound11:34:126
623394993735,2cyclictest1009581-21kworker/u16:1+events_unbound10:28:236
623394993735,2cyclictest1009581-21kworker/u16:1+events_unbound10:28:236
623394993734,2cyclictest1231669-21kworker/u16:2+events_unbound11:55:196
623389993735,2cyclictest972340-21kworker/u16:5+events_unbound10:07:045
623389993735,2cyclictest969092-21kworker/u16:3+events_unbound10:04:365
623389993735,2cyclictest785625-21kworker/u16:4+flush-8:009:50:005
623389993735,2cyclictest1302695-21kworker/u16:0+events_unbound12:22:035
623389993735,2cyclictest1105810-21kworker/u16:3+events_unbound11:10:515
623394993634,2cyclictest972340-21kworker/u16:5+events_unbound10:09:006
623394993634,2cyclictest895343-21kworker/u16:0+events_unbound11:17:246
623394993634,2cyclictest895343-21kworker/u16:0+events_unbound11:11:486
623394993634,2cyclictest895343-21kworker/u16:0+events_unbound10:53:516
623394993634,2cyclictest785625-21kworker/u16:4+events_unbound09:22:136
623394993634,2cyclictest1302695-21kworker/u16:0+events_unbound12:07:166
623394993634,2cyclictest1231668-21kworker/u16:1+events_unbound12:13:436
623394993634,2cyclictest1231668-21kworker/u16:1+events_unbound11:49:196
623394993634,2cyclictest1009581-21kworker/u16:1+events_unbound10:48:286
623394993634,2cyclictest1009581-21kworker/u16:1+events_unbound10:32:276
623389993634,2cyclictest895343-21kworker/u16:0+events_unbound11:17:595
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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