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2025-12-08 - 08:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Dec 08, 2025 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3792846995853,4cyclictest76423-21latency_hist07:17:297
3792846995046,2cyclictest3846177-21ntpq03:43:007
379253824939,7sleep50-21swapper/503:22:235
3792841994745,2cyclictest237415-21kworker/u16:0+events_unbound08:41:316
379226224737,7sleep40-21swapper/403:18:374
3792846994443,0cyclictest0-21swapper/704:37:597
379251024333,7sleep60-21swapper/603:22:006
3792841994139,2cyclictest3816923-21kworker/u16:3+events_unbound03:43:046
3792840994036,3cyclictest4098547-21kworker/u16:2+flush-8:006:57:455
37925312395,30sleep70-21swapper/703:22:177
3792846993837,0cyclictest0-21swapper/706:44:067
379284699380,36cyclictest36149-21latency_hist06:57:297
3792841993835,2cyclictest3846972-21kworker/u16:4+flush-8:005:22:556
3792846993730,5cyclictest589235-21systemd-journal05:52:297
379284699370,35cyclictest589235-21systemd-journal08:51:387
3792841993735,2cyclictest4168955-21kworker/u16:3+events_unbound06:36:406
3792846993635,0cyclictest0-21swapper/706:24:557
3792840993635,1cyclictest3370647-21kworker/u16:8+events_unbound03:32:465
3792846993534,0cyclictest0-21swapper/707:38:397
3792846993534,0cyclictest0-21swapper/706:27:397
3792846993433,0cyclictest0-21swapper/704:31:497
3792841993432,2cyclictest4068465-21kworker/u16:1+flush-8:005:42:316
3792841993432,2cyclictest3846972-21kworker/u16:4+events_unbound05:18:596
3792846993332,0cyclictest0-21swapper/708:42:577
3792846993332,0cyclictest0-21swapper/704:32:407
3792841993331,2cyclictest3846911-21kworker/u16:2+flush-8:003:47:576
3792841993331,2cyclictest227204-21kworker/u16:1+events_unbound08:36:266
3792841993331,2cyclictest207157-21kworker/u16:3+flush-8:008:31:556
3792846993231,0cyclictest0-21swapper/707:05:127
3792846993231,0cyclictest0-21swapper/703:24:467
3792841993230,2cyclictest4138846-21kworker/u16:1+events_unbound06:10:486
3792846993130,0cyclictest0-21swapper/706:47:317
3792841993129,2cyclictest86339-21kworker/u16:0+events_unbound07:41:396
3792841993129,2cyclictest5313-21kworker/u16:1+events_unbound07:58:026
3792841993129,2cyclictest4168955-21kworker/u16:3+events_unbound07:26:056
3792841993129,2cyclictest4098547-21kworker/u16:2+events_unbound06:56:446
3792841993129,2cyclictest4027913-21kworker/u16:0+events_unbound06:06:446
3792841993129,2cyclictest3877082-21kworker/u16:1+flush-8:004:15:316
3792841993129,2cyclictest3816827-21kworker/u16:1+events_unbound03:32:196
3792841993129,2cyclictest186906-21kworker/u16:2+flush-8:008:19:206
3792840993129,2cyclictest4098547-21kworker/u16:2+flush-8:005:57:555
3792840993129,2cyclictest3947682-21kworker/u16:2+flush-8:004:37:455
3792846993029,0cyclictest0-21swapper/708:32:307
3792841993028,2cyclictest86339-21kworker/u16:0+flush-8:007:34:436
3792841993028,2cyclictest5313-21kworker/u16:1+flush-8:006:48:596
3792841993028,2cyclictest4168955-21kworker/u16:3+events_unbound06:32:076
3792841993028,2cyclictest4098547-21kworker/u16:2+events_unbound07:11:556
3792841993028,2cyclictest4098547-21kworker/u16:2+events_unbound05:49:446
3792841993028,2cyclictest4038693-21kworker/u16:6+events_unbound05:42:076
3792841993028,2cyclictest4027913-21kworker/u16:0+events_unbound06:19:116
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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