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2026-05-03 - 11:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sun May 03, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27055725747,7sleep50-21swapper/519:04:395
27085425645,8sleep40-21swapper/419:08:474
271147994744,2cyclictest733972-21kworker/u16:4+events_unbound23:08:474
271158994443,0cyclictest0-21swapper/722:04:217
271158994439,4cyclictest601161-21latency_hist21:48:477
2707712432,36sleep70-21swapper/719:07:387
271158993833,3cyclictest610203-21ntpq21:49:137
271158993433,0cyclictest0-21swapper/721:28:457
271158993432,1cyclictest0-21swapper/721:21:017
271153993432,2cyclictest888046-21kworker/u16:1+flush-8:000:03:476
271152993432,2cyclictest187891-21kworker/u16:2+events_unbound19:24:025
271147993431,2cyclictest217282-21kworker/u16:3+flush-8:019:43:484
271158993332,0cyclictest0-21swapper/722:43:507
271158993331,1cyclictest504802-21diskmemload22:36:467
271158993331,1cyclictest504802-21diskmemload22:36:467
271158993231,0cyclictest0-21swapper/719:13:497
271158993230,1cyclictest671581-21ssh22:15:027
271158993227,4cyclictest914541-21latency_hist23:58:477
271158993227,4cyclictest914541-21latency_hist23:58:477
271153993228,3cyclictest938773-21kworker/u16:5+flush-8:000:28:476
271158993130,0cyclictest0-21swapper/721:09:027
271158993129,1cyclictest0-21swapper/723:26:057
27115899310,29cyclictest890415-21latency_hist23:48:487
271158993029,0cyclictest0-21swapper/723:50:097
271158993027,2cyclictest961941-21ssh00:17:017
271152993027,2cyclictest328920-21kworker/u16:4+flush-8:019:53:495
271158992928,0cyclictest0-21swapper/721:59:487
271158992928,0cyclictest0-21swapper/700:08:577
271158992927,1cyclictest577028-21ssh21:38:397
271158992927,1cyclictest0-21swapper/722:56:547
271152992927,2cyclictest904238-21kworker/u16:0+flush-8:000:14:035
271147992927,2cyclictest597797-21kworker/u16:2+flush-8:022:04:024
271158992827,0cyclictest0-21swapper/700:00:457
271158992826,1cyclictest0-21swapper/722:42:347
271158992826,1cyclictest0-21swapper/700:26:527
271153992826,2cyclictest456885-21kworker/u16:0+events_unbound21:09:096
271152992826,2cyclictest866699-21kworker/u16:2+events_unbound00:09:025
271147992827,1cyclictest597797-21kworker/u16:2+events_unbound21:46:054
271147992824,3cyclictest733972-21kworker/u16:4+flush-8:000:18:524
271158992725,1cyclictest0-21swapper/721:15:227
271152992725,2cyclictest445013-21kworker/u16:3+flush-8:021:48:485
271152992725,2cyclictest418574-21kworker/u16:2+flush-8:020:41:055
271147992725,2cyclictest733972-21kworker/u16:4+flush-8:023:59:574
271147992725,2cyclictest456885-21kworker/u16:0+flush-8:021:09:454
27056722717,7sleep60-21swapper/619:04:486
271158992625,0cyclictest0-21swapper/723:34:457
271158992625,0cyclictest0-21swapper/722:10:297
271158992625,0cyclictest0-21swapper/721:29:177
271153992624,2cyclictest904238-21kworker/u16:0+flush-8:000:18:476
271152992624,2cyclictest682581-21kworker/u16:0+events_unbound22:29:145
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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