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2025-09-04 - 06:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Thu Sep 04, 2025 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
156283126049,8sleep40-21swapper/403:24:454
156285025848,7sleep50-21swapper/503:25:025
1563453995347,5cyclictest1704225-21latency_hist04:38:507
156345399530,51cyclictest1606345-21latency_hist03:48:507
156345399530,51cyclictest1606345-21latency_hist03:48:507
156294725320,29sleep70-21swapper/703:26:247
1563441995149,1cyclictest1738737-21kworker/u16:3+flush-8:006:09:054
1563453994944,4cyclictest1841430-21latency_hist05:48:497
1563448994944,2cyclictest1508590-21kworker/u16:4+flush-8:004:04:055
1563441994947,2cyclictest2095968-21kworker/u16:3+flush-8:008:19:244
1563441994947,2cyclictest2095968-21kworker/u16:3+flush-8:008:19:244
1563441994947,2cyclictest2095968-21kworker/u16:3+events_unbound08:14:244
1563453994843,4cyclictest1939262-21latency_hist06:38:497
1563441994845,2cyclictest2007487-21kworker/u16:0+events_unbound07:24:014
1563441994543,2cyclictest1738737-21kworker/u16:3+events_unbound05:15:044
1563441994442,2cyclictest2007487-21kworker/u16:0+events_unbound07:14:204
1563441994442,2cyclictest1841118-21kworker/u16:1+events_unbound05:58:254
1563441994442,2cyclictest1684503-21kworker/u16:5+events_unbound04:29:164
1563441994441,2cyclictest1585997-21kworker/u16:2+events_unbound05:24:054
1563448994341,2cyclictest1585997-21kworker/u16:2+events_unbound04:34:195
1563453994034,5cyclictest2115673-21latency_hist08:08:497
1563441994037,2cyclictest1585997-21kworker/u16:2+flush-8:004:14:054
1563448993937,2cyclictest2095968-21kworker/u16:3+events_unbound08:14:085
1563448993937,2cyclictest1909561-21kworker/u16:2+events_unbound06:49:195
1563441993937,2cyclictest1880220-21kworker/u16:5+events_unbound06:38:254
1563441993937,2cyclictest1801944-21kworker/u16:0+events_unbound06:05:134
1563453993833,4cyclictest1831678-21latency_hist05:43:507
1563448993836,2cyclictest1880220-21kworker/u16:5+events_unbound06:29:065
1563448993835,2cyclictest1948957-21kworker/u16:0+events_unbound06:44:035
1563441993836,2cyclictest2163832-21kworker/u16:0+events_unbound08:48:244
1563441993836,2cyclictest2017361-21kworker/u16:4+flush-8:007:34:194
1563441993836,2cyclictest2017361-21kworker/u16:4+flush-8:007:34:194
1563441993836,2cyclictest1801944-21kworker/u16:0+flush-8:005:29:244
1563441993836,2cyclictest1683611-21kworker/u16:3+events_unbound04:35:254
1563441993836,2cyclictest1585997-21kworker/u16:2+events_unbound04:05:254
1563448993735,2cyclictest2017361-21kworker/u16:4+events_unbound07:29:175
1563448993735,2cyclictest1801944-21kworker/u16:0+events_unbound05:33:245
1563448993735,2cyclictest1585997-21kworker/u16:2+flush-8:004:29:065
1563448993734,2cyclictest1640243-21kworker/u16:3+flush-8:004:09:035
1563441993735,2cyclictest2164488-21kworker/u16:5+flush-8:008:37:404
1563441993735,2cyclictest1508590-21kworker/u16:4+events_unbound04:09:534
1563453993634,1cyclictest0-21swapper/706:49:077
1563453993629,5cyclictest589235-21systemd-journal08:28:497
1563448993634,2cyclictest2066715-21kworker/u16:2+events_unbound07:54:225
1563448993634,2cyclictest1738737-21kworker/u16:3+flush-8:006:04:205
1563441993634,2cyclictest2135024-21kworker/u16:4+flush-8:008:54:194
1563441993634,2cyclictest1585997-21kworker/u16:2+flush-8:005:04:164
1563441993633,2cyclictest1655462-21kworker/u16:1+flush-8:004:59:074
156306323626,7sleep60-21swapper/603:27:596
1563448993533,2cyclictest2095968-21kworker/u16:3+events_unbound08:19:175
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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