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2026-04-26 - 05:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sun Apr 26, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
384464325947,8sleep50-21swapper/519:04:205
3854080994236,5cyclictest328098-21latency_hist00:09:157
38482912403,30sleep70-21swapper/719:04:387
385357623625,8sleep40-21swapper/419:06:114
385408099350,33cyclictest304048-21latency_hist23:59:157
3854073993533,2cyclictest374626-21kworker/u16:1+events_unbound00:27:495
3854073993331,2cyclictest4040065-21kworker/u16:4+events_unbound21:22:545
3854073993331,2cyclictest361937-21kworker/u16:0+events_unbound00:22:405
3854069993330,2cyclictest4160495-21kworker/u16:4+flush-8:023:19:154
3854078993230,2cyclictest219738-21kworker/u16:3+flush-8:023:52:256
3854073993230,2cyclictest4029572-21kworker/u16:2+events_unbound21:14:565
3854078993129,2cyclictest4029572-21kworker/u16:2+flush-8:020:54:156
3854073993028,2cyclictest4160495-21kworker/u16:4+events_unbound22:36:005
3854073993028,2cyclictest136723-21kworker/u16:2+flush-8:022:52:535
3854080992928,0cyclictest0-21swapper/723:09:297
3854073992927,2cyclictest4160495-21kworker/u16:4+events_unbound23:03:085
3854073992927,2cyclictest4145740-21kworker/u16:2+flush-8:021:39:405
3854073992927,2cyclictest39076-21kworker/u16:5+flush-8:022:13:265
3854073992927,2cyclictest39076-21kworker/u16:5+flush-8:022:13:265
3854073992927,2cyclictest374626-21kworker/u16:1+events_unbound00:36:565
3854073992927,2cyclictest219738-21kworker/u16:3+events_unbound00:17:125
3854073992927,2cyclictest219738-21kworker/u16:3+events_unbound00:17:125
3854078992826,2cyclictest99303-21kworker/u16:0+flush-8:022:49:456
3854073992826,2cyclictest219738-21kworker/u16:3+events_unbound00:05:525
3854073992826,2cyclictest136723-21kworker/u16:2+flush-8:022:57:485
3854073992826,2cyclictest136723-21kworker/u16:2+flush-8:022:57:485
3854073992825,2cyclictest4001614-21kworker/u16:3+events_unbound20:29:185
3854078992725,2cyclictest3815746-21kworker/u16:0+events_unbound19:14:336
3854073992725,2cyclictest99303-21kworker/u16:0+events_unbound22:47:395
3854073992725,2cyclictest4124355-21kworker/u16:3+flush-8:021:26:065
3854073992725,2cyclictest4077940-21kworker/u16:1+flush-8:021:01:455
3854073992725,2cyclictest3982391-21kworker/u16:1+events_unbound20:28:545
3854073992725,2cyclictest136723-21kworker/u16:2+flush-8:023:04:305
3854073992725,2cyclictest121021-21kworker/u16:2+flush-8:022:41:575
3854078992624,2cyclictest3915136-21kworker/u16:3+flush-8:019:39:386
3854073992624,2cyclictest4160495-21kworker/u16:4+events_unbound22:24:575
3854073992624,2cyclictest302750-21kworker/u16:2+events_unbound23:57:555
3854073992624,2cyclictest219738-21kworker/u16:3+flush-8:000:12:405
3854073992624,2cyclictest171715-21kworker/u16:0+events_unbound23:45:385
385365422616,7sleep60-21swapper/619:07:186
3854080992521,3cyclictest3915559-21sed19:39:167
3854078992522,2cyclictest4160495-21kworker/u16:4+flush-8:022:24:406
3854073992523,2cyclictest4160495-21kworker/u16:4+flush-8:023:20:285
3854073992523,2cyclictest4124355-21kworker/u16:3+events_unbound21:36:225
3854073992523,2cyclictest4049855-21kworker/u16:0+flush-8:021:11:565
3854073992523,2cyclictest3943861-21kworker/u16:1+events_unbound19:56:435
3854073992523,2cyclictest39075-21kworker/u16:1+flush-8:022:32:025
3854073992523,2cyclictest3853797-21kworker/u16:2+flush-8:019:29:025
3854073992523,2cyclictest243789-21kworker/u16:1+events_unbound23:53:085
3854073992523,2cyclictest243789-21kworker/u16:1+events_unbound00:00:495
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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