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2026-08-15 - 13:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sat Aug 15, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
353849622950,13sleep60-21swapper/607:03:156
397507021010,1sleep73975071-21kthreadcore10:23:177
41775382990,1sleep74177539-21cut11:48:137
354396925419,30sleep70-21swapper/707:04:057
354409424722,7sleep50-21swapper/507:05:485
3544537994644,2cyclictest3657003-21kworker/u16:0+flush-8:008:28:245
3544537994643,2cyclictest3597051-21kworker/u16:3+flush-8:008:43:115
3544537994643,2cyclictest3597051-21kworker/u16:3+flush-8:008:43:115
3544544994542,2cyclictest3832799-21iostat09:28:117
3544544994241,0cyclictest0-21swapper/709:58:287
354454499420,40cyclictest648-21systemd-journal10:57:537
3544544994139,1cyclictest0-21swapper/711:37:567
3544537994139,2cyclictest3714476-21kworker/u16:4+flush-8:008:33:115
3544537994139,2cyclictest3597051-21kworker/u16:3+flush-8:010:08:245
3544537994138,3cyclictest4151278-21kworker/u16:3+flush-8:011:53:155
3544544994037,2cyclictest3959348-21kthreadcore10:18:167
3544537994038,2cyclictest3657003-21kworker/u16:0+flush-8:008:08:245
3544529993937,2cyclictest3644864-21kworker/u16:1+flush-8:008:28:204
3544544993837,0cyclictest0-21swapper/707:23:237
3544537993836,2cyclictest4089878-21kworker/u16:0+flush-8:011:48:095
3544537993735,2cyclictest3597051-21kworker/u16:3+events_unbound10:03:095
3544537993634,2cyclictest4065383-21kworker/u16:4+flush-8:011:03:255
3544529993634,2cyclictest3490308-21kworker/u16:5+events_unbound08:03:104
354411123625,8sleep40-21swapper/407:06:034
3544542993533,2cyclictest4027150-21kworker/u16:0+events_unbound10:58:086
3544542993533,2cyclictest3277196-21kworker/u16:4+flush-8:007:48:096
3544542993532,2cyclictest3714476-21kworker/u16:4+flush-8:008:33:096
3544544993430,3cyclictest125-21kswapd008:16:527
3544537993432,2cyclictest4089878-21kworker/u16:0+flush-8:011:13:235
3544537993432,2cyclictest4050185-21kworker/u16:3+flush-8:011:18:285
3544537993432,2cyclictest4027150-21kworker/u16:0+flush-8:011:02:535
3544537993431,2cyclictest66655-21kworker/u16:1+events_unbound12:32:555
3544537993431,2cyclictest66655-21kworker/u16:1+events_unbound12:32:555
3544529993432,2cyclictest3644864-21kworker/u16:1+events_unbound08:13:274
3544544993330,2cyclictest4172226-21ntpq11:43:217
3544537993331,2cyclictest3856061-21kworker/u16:4+events_unbound09:43:275
3544537993230,2cyclictest3277196-21kworker/u16:4+flush-8:007:13:095
3544537993229,2cyclictest3774575-21kworker/u16:0+flush-8:009:08:115
3544537993229,2cyclictest3490308-21kworker/u16:5+flush-8:007:33:115
3544544993130,0cyclictest0-21swapper/710:49:197
3544544993128,2cyclictest3818817-21ssh09:22:157
3544544993127,2cyclictest4061768-21sh10:58:197
3544542993129,2cyclictest4089878-21kworker/u16:0+flush-8:011:32:486
3544542993129,2cyclictest3760339-21kworker/u16:2+events_unbound09:08:246
3544542993129,2cyclictest3597051-21kworker/u16:3+events_unbound08:51:286
3544537993129,2cyclictest3760339-21kworker/u16:2+flush-8:010:38:205
3544544993028,1cyclictest3903730-21sh09:55:197
3544544993024,5cyclictest4077222-21latency_hist11:07:547
354454499300,28cyclictest4026942-21sh10:45:497
3544542993028,2cyclictest3684625-21kworker/u16:2+events_unbound08:25:286
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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