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2025-12-04 - 08:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Thu Dec 04, 2025 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3426716996052,7cyclictest589235-21systemd-journal03:33:227
342637225747,7sleep50-21swapper/503:22:275
342619925746,8sleep40-21swapper/403:20:014
342671699530,51cyclictest589235-21systemd-journal03:47:457
342612524838,7sleep60-21swapper/603:18:596
342671699470,45cyclictest3843582-21latency_hist06:47:457
3426711994543,2cyclictest3984611-21kworker/u16:3+flush-8:008:13:125
3426707994542,2cyclictest3984611-21kworker/u16:3+events_unbound08:13:154
3426716994135,5cyclictest4055269-21latency_hist08:32:457
3426716994135,5cyclictest4055269-21latency_hist08:32:457
34175082413,32sleep70-21swapper/703:18:047
3426707994037,3cyclictest3521217-21kworker/u16:0+flush-8:004:12:454
3426711993937,2cyclictest3682091-21kworker/u16:1+flush-8:005:53:115
3426707993836,2cyclictest3884305-21kworker/u16:1+events_unbound07:26:274
3426711993735,2cyclictest3823142-21kworker/u16:3+events_unbound06:53:125
3426707993735,2cyclictest3733219-21kworker/u16:2+flush-8:005:59:254
3426707993734,2cyclictest3984611-21kworker/u16:3+events_unbound08:35:014
3426716993631,4cyclictest3914204-21latency_hist07:22:457
3426715993634,2cyclictest3733219-21kworker/u16:2+events_unbound06:18:156
3426707993634,2cyclictest3772863-21kworker/u16:3+events_unbound06:16:274
3426707993634,2cyclictest3772863-21kworker/u16:3+events_unbound06:16:274
3426707993633,2cyclictest3934712-21kworker/u16:4+events_unbound07:37:264
36627912350,1sleep70-21swapper/705:17:587
3426711993533,2cyclictest3884305-21kworker/u16:1+events_unbound07:52:265
3426707993533,2cyclictest3823142-21kworker/u16:3+events_unbound06:56:564
3426707993533,2cyclictest3733219-21kworker/u16:2+flush-8:006:08:124
3426707993533,2cyclictest3591548-21kworker/u16:2+flush-8:004:47:454
3426707993533,2cyclictest3591548-21kworker/u16:2+flush-8:004:47:454
3426707993533,2cyclictest3433742-21kworker/u16:2+flush-8:004:03:124
3426707993532,2cyclictest3974439-21kworker/u16:0+events_unbound07:52:484
3426711993432,2cyclictest3682091-21kworker/u16:1+events_unbound06:19:565
3426707993432,2cyclictest4004467-21kworker/u16:2+events_unbound08:46:484
3426707993432,2cyclictest3823142-21kworker/u16:3+events_unbound07:01:264
3426707993432,2cyclictest3823142-21kworker/u16:3+events_unbound07:01:264
3426707993432,2cyclictest3692936-21kworker/u16:5+events_unbound05:34:204
3426707993432,2cyclictest3571575-21kworker/u16:1+events_unbound05:04:244
3426711993331,2cyclictest3884305-21kworker/u16:1+flush-8:008:02:485
3426711993331,2cyclictest3521217-21kworker/u16:0+events_unbound04:19:085
3426707993331,2cyclictest3601938-21kworker/u16:4+events_unbound04:52:214
3426711993230,2cyclictest3682091-21kworker/u16:1+events_unbound06:02:255
3426711993230,2cyclictest3631343-21kworker/u16:0+flush-8:005:41:245
3426707993230,2cyclictest3541560-21kworker/u16:3+events_unbound04:18:134
3426711993129,2cyclictest3884305-21kworker/u16:1+flush-8:007:47:265
3426711993129,2cyclictest3884305-21kworker/u16:1+flush-8:007:47:265
3426711993129,2cyclictest3772863-21kworker/u16:3+events_unbound06:24:265
3426711993129,2cyclictest3682092-21kworker/u16:4+events_unbound05:36:165
3426711993129,2cyclictest3521217-21kworker/u16:0+events_unbound04:11:565
3426707993129,2cyclictest3884305-21kworker/u16:1+events_unbound07:46:484
3426707993129,2cyclictest3884305-21kworker/u16:1+events_unbound07:46:484
3426707993129,2cyclictest3803496-21kworker/u16:0+events_unbound06:47:264
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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