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2026-04-20 - 02:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Apr 20, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2540562960,1sleep7254057-21kthreadcore19:55:037
158003994441,2cyclictest119608-21kworker/u16:2+flush-8:019:29:394
158003994441,2cyclictest119608-21kworker/u16:2+flush-8:019:29:394
15756724333,7sleep50-21swapper/519:07:345
1493042413,31sleep70-21swapper/719:04:557
158011994037,2cyclictest824648-21kworker/u16:2+events_unbound00:24:566
158011994037,2cyclictest824648-21kworker/u16:2+events_unbound00:24:566
158009994039,1cyclictest476199-21kworker/u16:0+flush-8:022:19:395
15801699390,37cyclictest621348-21latency_hist22:44:397
158011993932,2cyclictest754850-21kworker/u16:1+events_unbound23:49:536
158016993836,1cyclictest180937-21latency_hist19:19:397
158011993836,2cyclictest363104-21kworker/u16:2+events_unbound22:05:576
158011993735,2cyclictest754850-21kworker/u16:1+events_unbound00:14:546
158011993735,2cyclictest754850-21kworker/u16:1+events_unbound00:08:256
158011993735,2cyclictest524671-21kworker/u16:1+events_unbound22:50:296
158011993735,2cyclictest476199-21kworker/u16:0+events_unbound22:47:216
158011993735,2cyclictest476199-21kworker/u16:0+events_unbound22:43:096
158011993735,2cyclictest438720-21kworker/u16:3+events_unbound22:02:486
15754723727,7sleep40-21swapper/419:07:174
158016993634,1cyclictest0-21swapper/723:50:097
15801699360,34cyclictest635-21systemd-journal22:24:397
15801699360,34cyclictest635-21systemd-journal22:24:397
158011993634,2cyclictest718182-21kworker/u16:4+flush-8:023:27:296
158011993634,2cyclictest633620-21kworker/u16:3+events_unbound23:20:136
158011993634,2cyclictest476199-21kworker/u16:0+events_unbound22:33:016
158011993634,2cyclictest476199-21kworker/u16:0+events_unbound21:52:386
158011993634,2cyclictest438720-21kworker/u16:3+events_unbound22:16:136
158011993533,2cyclictest839072-21kworker/u16:0+events_unbound00:22:336
158011993533,2cyclictest824648-21kworker/u16:2+events_unbound00:13:266
158011993533,2cyclictest633620-21kworker/u16:3+events_unbound23:03:386
158011993533,2cyclictest633620-21kworker/u16:3+events_unbound23:03:386
158011993533,2cyclictest438720-21kworker/u16:3+events_unbound21:32:566
158011993533,2cyclictest362943-21kworker/u16:1+events_unbound21:23:176
158003993533,2cyclictest476199-21kworker/u16:0+events_unbound22:30:214
158003993533,2cyclictest363104-21kworker/u16:2+flush-8:022:09:394
15745723525,7sleep60-21swapper/619:05:596
158011993432,2cyclictest839209-21kworker/u16:4+events_unbound00:32:246
158011993432,2cyclictest524671-21kworker/u16:1+events_unbound23:08:576
158011993432,2cyclictest363104-21kworker/u16:2+events_unbound22:21:246
158011993432,2cyclictest363104-21kworker/u16:2+events_unbound22:21:246
158011993431,2cyclictest363104-21kworker/u16:2+events_unbound21:41:026
4778302330,1chrt477831-21irqcore21:44:577
158011993331,2cyclictest718182-21kworker/u16:4+events_unbound23:47:016
158011993331,2cyclictest633620-21kworker/u16:3+flush-8:000:00:386
158011993331,2cyclictest438720-21kworker/u16:3+events_unbound21:47:536
158011993331,2cyclictest3639029-21kworker/u16:0+flush-8:019:14:456
158011993331,2cyclictest363104-21kworker/u16:2+events_unbound21:58:536
158011993331,2cyclictest362943-21kworker/u16:1+events_unbound21:17:416
158011993331,2cyclictest157775-21kworker/u16:3+flush-8:019:20:016
158011993230,2cyclictest416330-21kworker/u16:0+events_unbound21:26:216
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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