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2026-07-09 - 22:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Thu Jul 09, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41631062960,1sleep50-21swapper/512:30:105
37904262960,1sleep73790427-21cat10:00:097
342442927262,7sleep50-21swapper/507:06:045
36750242620,1sleep73675025-21cat09:14:497
342463826048,7sleep40-21swapper/407:09:004
342466125823,30sleep70-21swapper/707:09:197
3424982994339,4cyclictest4058194-21kworker/u16:3+flush-8:011:54:495
342499499420,40cyclictest4120030-21latency_hist12:14:487
3424986994240,2cyclictest3922454-21kworker/u16:2+events_unbound11:24:396
3424986994037,2cyclictest3661585-21kworker/u16:5+events_unbound09:35:036
3424986993937,2cyclictest3814484-21kworker/u16:2+events_unbound10:26:236
3424994993832,5cyclictest3623536-21latency_hist08:49:497
3424986993836,2cyclictest3814484-21kworker/u16:2+events_unbound10:18:386
3424986993735,2cyclictest4058194-21kworker/u16:3+events_unbound12:07:146
3424986993735,2cyclictest3996430-21kworker/u16:4+events_unbound11:47:276
3424986993735,2cyclictest3661585-21kworker/u16:5+events_unbound09:18:116
3424986993734,2cyclictest3506390-21kworker/u16:2+flush-8:008:45:046
3424986993734,2cyclictest2677098-21kworker/u16:3+events_unbound07:19:516
3424986993634,2cyclictest4114882-21kworker/u16:2+events_unbound12:28:066
3424986993634,2cyclictest4058194-21kworker/u16:3+events_unbound11:59:196
3424986993634,2cyclictest4045163-21kworker/u16:1+events_unbound12:20:396
3424986993634,2cyclictest3833007-21kworker/u16:1+events_unbound10:49:116
3424986993634,2cyclictest3459255-21kworker/u16:1+events_unbound09:43:436
40536412340,1sleep40-21swapper/411:45:134
3424994993432,1cyclictest3943557-21ssh11:00:147
3424986993432,2cyclictest3860334-21kworker/u16:3+events_unbound11:31:436
3424986993432,2cyclictest3786106-21kworker/u16:4+events_unbound10:52:236
3424986993432,2cyclictest3633509-21kworker/u16:3+events_unbound09:10:396
36964872330,5chrt3696481-21ssh09:20:187
3424986993331,2cyclictest4154627-21kworker/u16:0+events_unbound12:32:036
3424986993331,2cyclictest3956865-21kworker/u16:0+events_unbound11:07:266
3424986993331,2cyclictest3661585-21kworker/u16:5+events_unbound09:23:266
342461323310,8sleep60-21swapper/607:08:376
3424986993230,2cyclictest3459255-21kworker/u16:1+events_unbound09:00:226
3424986993129,2cyclictest3487549-21kworker/u16:3+events_unbound07:39:516
3424986993129,2cyclictest3459255-21kworker/u16:1+events_unbound10:01:326
37014632300,1chrt3701464-21kthreadcore09:25:077
342499499300,28cyclictest908-21dbus-daemon07:29:497
3424986993028,2cyclictest4154627-21kworker/u16:0+events_unbound12:36:296
3424986993028,2cyclictest3956865-21kworker/u16:0+flush-8:012:11:586
3424986993028,2cyclictest3922454-21kworker/u16:2+flush-8:011:00:306
3424986993028,2cyclictest3860334-21kworker/u16:3+events_unbound11:29:426
3424986993028,2cyclictest3595571-21kworker/u16:0+events_unbound08:40:126
37627462290,1chrt3762748-21irqcore09:50:087
36411532290,1chrt3641154-21kthreadcore08:55:107
3424986992927,2cyclictest3956865-21kworker/u16:0+flush-8:012:00:236
3424986992927,2cyclictest3833007-21kworker/u16:1+flush-8:010:24:066
3424986992927,2cyclictest3786106-21kworker/u16:4+events_unbound10:10:166
3424986992927,2cyclictest3699477-21kworker/u16:2+events_unbound09:27:286
3424986992927,2cyclictest3661585-21kworker/u16:5+flush-8:009:31:276
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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