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2026-08-04 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Tue Aug 04, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3871962994843,4cyclictest192838-21latency_hist23:03:377
3871954994745,2cyclictest4193296-21kworker/u16:2+events_unbound22:01:245
38664732452,31sleep70-21swapper/719:04:017
387159024419,7sleep40-21swapper/419:07:434
3871949994341,2cyclictest4050749-21kworker/u16:2+flush-8:021:18:404
3871962994240,1cyclictest4108717-21diskmemload22:54:047
3871958994240,2cyclictest4050749-21kworker/u16:2+events_unbound21:24:126
3871958994239,2cyclictest3842432-21kworker/u16:1+events_unbound20:48:406
3871949994240,2cyclictest313468-21kworker/u16:2+events_unbound23:58:394
3871949994138,2cyclictest4108758-21kworker/u16:3+events_unbound21:33:404
387146624130,8sleep50-21swapper/519:06:005
3871949994037,2cyclictest4108758-21kworker/u16:3+events_unbound22:33:404
3871962993936,2cyclictest120296-21ssh22:33:237
3871954993937,2cyclictest4108758-21kworker/u16:3+flush-8:022:43:405
387160123929,7sleep60-21swapper/619:07:546
3871958993735,2cyclictest4108758-21kworker/u16:3+flush-8:022:18:406
3871954993734,2cyclictest3904434-21kworker/u16:3+flush-8:019:38:405
3871949993735,2cyclictest265616-21kworker/u16:5+flush-8:023:38:554
3871954993634,2cyclictest409924-21kworker/u16:1+events_unbound00:36:205
3871949993634,2cyclictest3842432-21kworker/u16:1+events_unbound21:26:404
3871962993534,0cyclictest0-21swapper/721:47:087
3871958993533,2cyclictest4108758-21kworker/u16:3+events_unbound22:28:006
3871954993533,2cyclictest325866-21kworker/u16:4+events_unbound00:25:475
3871949993532,2cyclictest265616-21kworker/u16:5+events_unbound23:57:074
3871958993432,2cyclictest4193296-21kworker/u16:2+events_unbound23:06:246
3871958993432,2cyclictest4108758-21kworker/u16:3+flush-8:021:50:566
3871958993432,2cyclictest4108758-21kworker/u16:3+flush-8:021:50:566
3871958993432,2cyclictest166859-21kworker/u16:3+events_unbound23:21:556
3871954993432,2cyclictest4108758-21kworker/u16:3+flush-8:021:43:355
3871962993332,0cyclictest0-21swapper/722:11:197
3871962993331,1cyclictest4108717-21diskmemload00:04:527
3871958993331,2cyclictest4193296-21kworker/u16:2+events_unbound23:32:006
3871958993331,2cyclictest4178909-21kworker/u16:0+flush-8:022:37:316
3871958993331,2cyclictest4050749-21kworker/u16:2+flush-8:021:33:216
3871958993331,2cyclictest313468-21kworker/u16:2+flush-8:023:59:166
3871954993331,2cyclictest4193296-21kworker/u16:2+flush-8:022:53:385
3871954993331,2cyclictest4178909-21kworker/u16:0+events_unbound22:26:245
3871954993331,2cyclictest4178909-21kworker/u16:0+events_unbound21:56:485
3871949993331,2cyclictest4193296-21kworker/u16:2+flush-8:022:53:594
3871949993331,2cyclictest4178909-21kworker/u16:0+events_unbound22:07:134
3871949993331,2cyclictest4050749-21kworker/u16:2+events_unbound21:12:404
3871949993331,2cyclictest3842432-21kworker/u16:1+flush-8:021:32:404
3871949993331,2cyclictest362120-21kworker/u16:0+events_unbound00:27:194
3871949993331,2cyclictest166859-21kworker/u16:3+events_unbound23:44:274
3871949993331,2cyclictest166859-21kworker/u16:3+events_unbound23:14:564
3871962993231,0cyclictest0-21swapper/721:23:097
3871962993231,0cyclictest0-21swapper/700:27:237
3871958993230,2cyclictest4178909-21kworker/u16:0+events_unbound22:30:566
3871958993230,2cyclictest4108758-21kworker/u16:3+events_unbound22:12:446
3871958993230,2cyclictest265616-21kworker/u16:5+events_unbound00:20:486
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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