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2026-05-27 - 10:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Wed May 27, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
239869025746,8sleep50-21swapper/519:05:045
2399130995452,2cyclictest2603737-21kworker/u16:3+events_unbound20:52:395
2399130995452,2cyclictest2603737-21kworker/u16:3+events_unbound20:52:395
239875525327,8sleep40-21swapper/419:05:594
2399130994947,2cyclictest3020941-21kworker/u16:4+events_unbound23:57:425
2399130994441,2cyclictest2705583-21kworker/u16:0+events_unbound21:42:145
23972192403,31sleep70-21swapper/719:02:417
2399135993937,2cyclictest2984405-21kworker/u16:3+events_unbound00:27:266
2399130993937,2cyclictest2832540-21kworker/u16:0+events_unbound23:29:435
2399130993836,2cyclictest3018553-21kworker/u16:1+events_unbound23:42:585
2399130993836,2cyclictest2705583-21kworker/u16:0+events_unbound21:53:555
2399130993735,2cyclictest3018553-21kworker/u16:1+events_unbound00:23:185
2399130993735,2cyclictest3018553-21kworker/u16:1+events_unbound00:08:425
2399130993735,2cyclictest2936238-21kworker/u16:3+events_unbound23:12:155
2399130993735,2cyclictest2766799-21kworker/u16:2+events_unbound22:42:105
2399130993735,2cyclictest2730439-21kworker/u16:1+events_unbound22:29:185
2399130993735,2cyclictest2682291-21kworker/u16:3+events_unbound21:58:315
2399139993631,4cyclictest2778874-21latency_hist22:07:127
2399130993634,2cyclictest2730439-21kworker/u16:1+events_unbound22:13:475
2399130993634,2cyclictest2730439-21kworker/u16:1+events_unbound22:13:475
2399130993533,2cyclictest3118071-21kworker/u16:0+events_unbound00:29:025
2399130993533,2cyclictest3018553-21kworker/u16:1+events_unbound00:17:105
2399130993533,2cyclictest3018553-21kworker/u16:1+events_unbound00:17:105
2399130993533,2cyclictest2984405-21kworker/u16:3+events_unbound23:33:515
2399130993533,2cyclictest2984405-21kworker/u16:3+events_unbound23:33:515
2399130993533,2cyclictest2888364-21kworker/u16:1+events_unbound23:12:105
2399130993533,2cyclictest2832540-21kworker/u16:0+events_unbound23:39:435
2399130993533,2cyclictest2832540-21kworker/u16:0+events_unbound23:03:265
2399130993533,2cyclictest2832540-21kworker/u16:0+events_unbound22:59:515
2399130993533,2cyclictest2766799-21kworker/u16:2+flush-8:022:07:435
2399130993533,2cyclictest2766799-21kworker/u16:2+events_unbound23:25:275
2399130993533,2cyclictest2730439-21kworker/u16:1+events_unbound22:19:105
2399130993532,2cyclictest2984405-21kworker/u16:3+events_unbound23:49:315
2399130993532,2cyclictest2832540-21kworker/u16:0+events_unbound23:52:155
2399130993432,2cyclictest2851566-21kworker/u16:3+events_unbound22:49:185
2399130993432,2cyclictest2682291-21kworker/u16:3+events_unbound21:41:035
2399130993432,2cyclictest2682291-21kworker/u16:3+events_unbound21:27:585
2399130993432,2cyclictest2643791-21kworker/u16:1+flush-8:021:35:515
2399130993432,2cyclictest2643791-21kworker/u16:1+flush-8:021:35:515
239860823424,7sleep60-21swapper/619:03:526
2399139993332,0cyclictest0-21swapper/721:37:507
2399130993331,2cyclictest2832540-21kworker/u16:0+flush-8:022:52:465
2399130993331,2cyclictest2832540-21kworker/u16:0+flush-8:022:52:465
2399130993330,2cyclictest2730439-21kworker/u16:1+flush-8:022:22:225
2399126993331,2cyclictest2682291-21kworker/u16:3+events_unbound21:42:354
2399130993230,2cyclictest3118071-21kworker/u16:0+flush-8:000:35:235
2399130993230,2cyclictest2984405-21kworker/u16:3+events_unbound00:18:545
2399130993230,2cyclictest2766799-21kworker/u16:2+events_unbound23:21:035
2399130993230,2cyclictest2766799-21kworker/u16:2+events_unbound22:46:185
2399130993230,2cyclictest2766799-21kworker/u16:2+events_unbound22:06:515
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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