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2026-03-13 - 04:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Fri Mar 13, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
120999925948,8sleep40-21swapper/419:00:124
121001125848,7sleep50-21swapper/519:00:215
121023825040,7sleep60-21swapper/619:03:356
1210542994442,2cyclictest1488844-21kworker/u16:5+events_unbound21:32:035
1210542994240,2cyclictest1753092-21kworker/u16:2+events_unbound23:41:265
1210542994240,2cyclictest1539264-21kworker/u16:2+events_unbound22:22:585
121054899400,38cyclictest1801004-21latency_hist23:33:567
1210542994038,2cyclictest1517252-21kworker/u16:1+events_unbound22:31:425
1210547993937,2cyclictest1848978-21kworker/u16:5+events_unbound00:16:296
1210542993937,2cyclictest1848978-21kworker/u16:5+events_unbound00:13:335
1210542993936,2cyclictest1738366-21kworker/u16:0+events_unbound23:25:265
1210542993936,2cyclictest1262098-21kworker/u16:2+events_unbound21:24:055
1210542993935,3cyclictest1394655-21kworker/u16:3+flush-8:021:19:015
1210539993937,2cyclictest1738366-21kworker/u16:0+flush-8:023:33:564
12100492395,30sleep70-21swapper/719:00:557
1210547993836,2cyclictest1488844-21kworker/u16:5+events_unbound21:48:506
1210542993836,2cyclictest1778863-21kworker/u16:1+events_unbound00:00:215
1210547993735,2cyclictest1488844-21kworker/u16:5+events_unbound23:19:386
1210542993735,2cyclictest1753092-21kworker/u16:2+events_unbound23:35:095
1210542993735,2cyclictest1694275-21kworker/u16:1+events_unbound23:08:265
1210542993735,2cyclictest1658449-21kworker/u16:3+events_unbound23:00:495
1210542993735,2cyclictest1658449-21kworker/u16:3+events_unbound22:46:215
1210542993735,2cyclictest1539264-21kworker/u16:2+events_unbound22:25:545
1210542993735,2cyclictest1517252-21kworker/u16:1+events_unbound21:41:505
1210542993735,2cyclictest1488844-21kworker/u16:5+events_unbound23:15:135
1210542993735,2cyclictest1262098-21kworker/u16:2+events_unbound21:15:115
1210542993634,2cyclictest1848978-21kworker/u16:5+events_unbound00:27:535
1210542993634,2cyclictest1694275-21kworker/u16:1+events_unbound23:12:465
1210542993634,2cyclictest1488844-21kworker/u16:5+events_unbound21:46:275
1210542993634,2cyclictest1262098-21kworker/u16:2+events_unbound21:04:595
1210542993634,2cyclictest1262098-21kworker/u16:2+events_unbound21:04:595
1210542993633,2cyclictest1848978-21kworker/u16:5+events_unbound00:19:095
1210542993533,2cyclictest1738366-21kworker/u16:0+events_unbound23:32:055
15148522340,0sleep71514853-21sh21:33:357
1210547993432,2cyclictest1738366-21kworker/u16:0+events_unbound23:07:456
1210547993432,2cyclictest1539264-21kworker/u16:2+events_unbound22:09:336
1210542993432,2cyclictest1846322-21kworker/u16:3+events_unbound23:51:085
1210542993432,2cyclictest1846322-21kworker/u16:3+events_unbound23:51:085
1210542993432,2cyclictest1753092-21kworker/u16:2+events_unbound23:57:535
1210542993432,2cyclictest1753092-21kworker/u16:2+events_unbound23:23:275
1210542993432,2cyclictest1658404-21kworker/u16:0+events_unbound22:42:135
1210542993432,2cyclictest1517252-21kworker/u16:1+events_unbound21:52:175
1210542993432,2cyclictest1488844-21kworker/u16:5+events_unbound22:16:515
1210542993432,2cyclictest1488844-21kworker/u16:5+events_unbound21:36:535
1210547993331,2cyclictest1517252-21kworker/u16:1+events_unbound22:23:376
1210542993331,2cyclictest1778863-21kworker/u16:1+events_unbound23:47:535
1210542993331,2cyclictest1658449-21kworker/u16:3+events_unbound22:49:425
1210542993331,2cyclictest1517252-21kworker/u16:1+events_unbound22:08:155
1210539993330,2cyclictest1738366-21kworker/u16:0+flush-8:023:23:564
1210547993230,2cyclictest1488844-21kworker/u16:5+flush-8:021:29:356
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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