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2026-04-13 - 06:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Apr 13, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
396366721460,1sleep73963665-21ntpq22:27:197
37543712960,1sleep50-21swapper/521:02:135
3516624995351,2cyclictest3833954-21kworker/u16:1+events_unbound21:37:194
3516624995250,2cyclictest3870198-21kworker/u16:4+events_unbound22:42:234
3516624995249,2cyclictest3488210-21kworker/u16:3+events_unbound19:17:074
3516624995149,2cyclictest3870198-21kworker/u16:4+events_unbound22:17:074
3516624995149,2cyclictest3488210-21kworker/u16:3+events_unbound19:52:084
3516624995048,2cyclictest3833954-21kworker/u16:1+flush-8:021:47:094
3516624995048,2cyclictest3488210-21kworker/u16:3+events_unbound21:22:084
351632625040,7sleep50-21swapper/519:01:395
3516624994948,1cyclictest3918456-21kworker/u16:0+events_unbound22:32:104
351631824838,7sleep60-21swapper/619:01:326
3516624994746,1cyclictest3488210-21kworker/u16:3+flush-8:021:27:094
3516624994745,2cyclictest4181857-21kworker/u16:2+events_unbound00:27:164
3516624994745,2cyclictest4112196-21kworker/u16:5+events_unbound23:46:554
3516624994744,2cyclictest3783457-21kworker/u16:2+events_unbound21:17:074
3516624994644,2cyclictest3991360-21kworker/u16:3+events_unbound23:56:554
3516624994643,2cyclictest3488210-21kworker/u16:3+events_unbound20:02:084
3516624994543,2cyclictest4015507-21kworker/u16:2+events_unbound23:31:114
3516624994543,2cyclictest3870198-21kworker/u16:4+events_unbound22:07:244
3516624994543,2cyclictest3673122-21kworker/u16:1+flush-8:021:11:534
3516624994543,2cyclictest3606316-21kworker/u16:4+events_unbound20:47:234
3516624994543,2cyclictest3488210-21kworker/u16:3+flush-8:020:07:214
3516624994543,2cyclictest3488210-21kworker/u16:3+flush-8:020:07:214
3516624994442,2cyclictest3783457-21kworker/u16:2+events_unbound21:52:084
3516624994341,2cyclictest4181857-21kworker/u16:2+events_unbound00:17:284
3516624994341,2cyclictest3870198-21kworker/u16:4+flush-8:021:57:194
3516624994240,2cyclictest4181857-21kworker/u16:2+events_unbound00:11:114
3516624994240,2cyclictest3673122-21kworker/u16:1+events_unbound21:05:204
3516633994137,3cyclictest124-21kswapd000:17:077
3516624994139,2cyclictest3966856-21kworker/u16:1+events_unbound22:48:314
3516624994139,2cyclictest3783457-21kworker/u16:2+events_unbound21:15:594
3516624994139,2cyclictest14274-21kworker/u16:0+events_unbound00:22:214
351633424130,8sleep40-21swapper/419:01:474
3516624994038,2cyclictest4061270-21kworker/u16:0+events_unbound23:18:114
3516624994038,2cyclictest3870198-21kworker/u16:4+events_unbound22:23:084
3516624994038,2cyclictest3606316-21kworker/u16:4+flush-8:020:17:214
3516624994038,2cyclictest3488210-21kworker/u16:3+events_unbound22:14:404
3516624994038,2cyclictest3488210-21kworker/u16:3+events_unbound22:14:404
3516624994037,2cyclictest4061270-21kworker/u16:0+events_unbound23:24:114
3516624994037,2cyclictest3991360-21kworker/u16:3+flush-8:023:12:094
35160802403,31sleep70-21swapper/718:58:137
3516629993937,2cyclictest4112156-21kworker/u16:4+flush-8:023:32:236
3516629993937,2cyclictest4112156-21kworker/u16:4+flush-8:023:32:236
3516629993937,2cyclictest3488210-21kworker/u16:3+flush-8:022:12:246
3516629993937,2cyclictest3488210-21kworker/u16:3+flush-8:022:12:246
3516629993936,2cyclictest3488210-21kworker/u16:3+flush-8:021:26:486
3516624993937,2cyclictest4015507-21kworker/u16:2+flush-8:023:02:254
3516624993937,2cyclictest3991360-21kworker/u16:3+events_unbound23:46:514
3516624993937,2cyclictest3991360-21kworker/u16:3+events_unbound23:38:234
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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