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2026-01-01 - 18:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Thu Jan 01, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
334123425544,8sleep40-21swapper/407:08:084
334102925319,30sleep70-21swapper/707:05:157
334118024938,7sleep60-21swapper/607:07:226
333202124937,8sleep50-21swapper/507:03:445
3341561994741,5cyclictest3801006-21latency_hist11:03:397
3341548994442,2cyclictest3312678-21kworker/u16:3+flush-8:007:33:404
3341548994239,2cyclictest3539507-21kworker/u16:1+events_unbound09:03:544
3341548994239,2cyclictest3312678-21kworker/u16:3+flush-8:009:38:554
3341561993938,0cyclictest0-21swapper/712:18:557
3341548993836,2cyclictest3287418-21kworker/u16:1+events_unbound07:13:544
3341548993835,2cyclictest3481218-21kworker/u16:1+events_unbound08:18:534
3341561993736,0cyclictest0-21swapper/712:26:227
3341548993735,2cyclictest2634675-21kworker/u16:0+events_unbound07:43:544
3341548993734,2cyclictest3781296-21kworker/u16:2+events_unbound11:14:074
3341548993533,2cyclictest3781296-21kworker/u16:2+events_unbound10:59:104
3341548993533,2cyclictest3704100-21kworker/u16:0+events_unbound11:38:584
3341548993532,2cyclictest3791688-21kworker/u16:1+flush-8:011:04:064
3341548993532,2cyclictest3665631-21kworker/u16:1+flush-8:009:59:114
3341548993532,2cyclictest3539507-21kworker/u16:1+flush-8:009:23:554
3341561993433,0cyclictest0-21swapper/709:06:247
3341548993432,2cyclictest3685958-21kworker/u16:3+events_unbound10:09:104
3341561993332,0cyclictest0-21swapper/711:29:087
3341548993331,2cyclictest3675147-21kworker/u16:4+events_unbound10:54:114
3341548993331,2cyclictest3539507-21kworker/u16:1+events_unbound09:29:164
36885812320,0chrt3688583-21kthreadcore10:03:587
3341561993130,0cyclictest0-21swapper/708:27:517
3341548993129,2cyclictest3704100-21kworker/u16:0+events_unbound10:44:114
3341548993128,2cyclictest3927373-21kworker/u16:1+events_unbound12:28:544
3341548993128,2cyclictest3312678-21kworker/u16:3+flush-8:007:33:594
3341561993029,0cyclictest0-21swapper/712:12:317
3341561993029,0cyclictest0-21swapper/711:44:237
3341561993029,0cyclictest0-21swapper/711:36:227
3341548993028,2cyclictest3539507-21kworker/u16:1+flush-8:008:59:234
3341548993027,2cyclictest3781296-21kworker/u16:2+events_unbound11:28:514
3341548993027,2cyclictest3685958-21kworker/u16:3+flush-8:010:33:504
3341548993027,2cyclictest3539507-21kworker/u16:1+events_unbound08:53:544
3341561992928,0cyclictest0-21swapper/711:08:237
3341561992928,0cyclictest0-21swapper/710:18:277
3341561992928,0cyclictest0-21swapper/709:46:307
3341557992927,2cyclictest3916018-21kworker/u16:5+events_unbound12:15:416
3341557992927,2cyclictest3727642-21kworker/u16:1+flush-8:010:48:556
3341557992927,2cyclictest3665631-21kworker/u16:1+events_unbound09:59:286
3341557992927,2cyclictest3287418-21kworker/u16:1+flush-8:007:19:356
3341557992927,2cyclictest2634675-21kworker/u16:0+events_unbound08:02:036
3341548992927,2cyclictest3312678-21kworker/u16:3+events_unbound09:08:594
3341561992827,0cyclictest0-21swapper/711:52:227
3341561992827,0cyclictest0-21swapper/710:01:067
3341561992827,0cyclictest0-21swapper/709:37:237
3341561992825,2cyclictest3363731-21ntpq07:14:077
3341557992826,2cyclictest3312678-21kworker/u16:3+events_unbound07:56:366
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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