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2025-11-06 - 01:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Thu Nov 06, 2025 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7013525949,7sleep40-21swapper/403:23:074
7012825848,7sleep60-21swapper/603:23:016
7021325645,8sleep50-21swapper/503:24:135
7012025320,29sleep70-21swapper/703:22:547
70614994845,2cyclictest266226-21cut04:59:377
7061499450,43cyclictest80543-21latency_hist03:29:377
70614994439,4cyclictest306457-21latency_hist05:19:377
70612994442,2cyclictest386955-21kworker/u16:3+events_unbound06:12:355
70612994341,2cyclictest80230-21kworker/u16:1+flush-8:003:35:075
70612994341,2cyclictest80230-21kworker/u16:1+flush-8:003:35:075
70612994341,2cyclictest619642-21kworker/u16:4+events_unbound08:07:595
70612994341,2cyclictest619642-21kworker/u16:4+events_unbound08:07:595
70612994341,2cyclictest457952-21kworker/u16:4+events_unbound06:45:235
70613994240,2cyclictest19503-21kworker/u16:0+flush-8:003:35:056
70613994240,2cyclictest19503-21kworker/u16:0+flush-8:003:35:056
70612994240,2cyclictest255869-21kworker/u16:3+flush-8:005:10:065
70613994038,2cyclictest558511-21kworker/u16:1+events_unbound07:30:036
70613994038,2cyclictest348488-21kworker/u16:4+flush-8:005:55:026
70612994038,2cyclictest135112-21kworker/u16:0+events_unbound04:59:365
70614993935,2cyclictest639430-21latency_hist08:04:367
70612993735,2cyclictest618921-21kworker/u16:3+events_unbound07:57:305
70612993735,2cyclictest135112-21kworker/u16:0+events_unbound06:54:325
70613993634,2cyclictest659285-21kworker/u16:2+events_unbound08:25:096
70613993634,2cyclictest236964-21kworker/u16:1+events_unbound05:35:006
70612993634,2cyclictest386955-21kworker/u16:3+events_unbound06:34:345
70613993533,2cyclictest684591-21kworker/u16:0+events_unbound08:36:476
70613993533,2cyclictest457952-21kworker/u16:4+flush-8:007:15:316
70612993533,2cyclictest3591342-21kworker/u16:3+flush-8:003:52:335
70612993533,2cyclictest316919-21kworker/u16:4+flush-8:005:26:355
70613993432,2cyclictest588810-21kworker/u16:1+flush-8:007:58:396
70612993432,2cyclictest348488-21kworker/u16:4+flush-8:005:55:015
70612993432,2cyclictest236964-21kworker/u16:1+events_unbound06:01:485
70612993432,2cyclictest135112-21kworker/u16:0+flush-8:004:20:105
70612993432,2cyclictest135112-21kworker/u16:0+flush-8:004:20:105
70614993328,4cyclictest255991-21latency_hist04:54:377
70613993331,2cyclictest236964-21kworker/u16:1+events_unbound05:34:356
70613993331,2cyclictest135112-21kworker/u16:0+events_unbound06:44:586
70612993331,2cyclictest588810-21kworker/u16:1+events_unbound08:26:335
70612993331,2cyclictest457952-21kworker/u16:4+flush-8:006:35:035
70612993331,2cyclictest457952-21kworker/u16:4+flush-8:006:35:035
70612993331,2cyclictest386955-21kworker/u16:3+flush-8:006:18:475
70612993331,2cyclictest255869-21kworker/u16:3+events_unbound05:01:355
70612993331,2cyclictest175607-21kworker/u16:2+flush-8:004:50:485
70612993331,2cyclictest135112-21kworker/u16:0+flush-8:004:30:065
70614993231,0cyclictest0-21swapper/708:14:587
70613993230,2cyclictest80230-21kworker/u16:1+flush-8:004:06:236
70613993230,2cyclictest285287-21kworker/u16:4+flush-8:005:08:386
70613993230,2cyclictest285287-21kworker/u16:4+flush-8:005:08:386
70612993230,2cyclictest659285-21kworker/u16:2+events_unbound08:23:085
70612993230,2cyclictest578638-21kworker/u16:2+events_unbound07:50:345
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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