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2026-08-22 - 22:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sat Aug 22, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10705225948,7sleep40-21swapper/407:04:484
10718225722,30sleep70-21swapper/707:06:367
107550994843,4cyclictest662157-21latency_hist11:17:267
107550994742,4cyclictest649869-21latency_hist11:12:277
107546994541,3cyclictest660557-21kworker/u16:0+events_unbound11:16:196
10723624535,7sleep50-21swapper/507:07:225
107550994029,1cyclictest772114-21ssh12:02:257
107550993934,4cyclictest344413-21diskmemload11:49:527
107539993936,2cyclictest53191-21kworker/u16:0+events_unbound07:27:294
107550993836,1cyclictest344413-21diskmemload09:29:417
107550993836,1cyclictest0-21swapper/711:37:167
107550993834,3cyclictest794791-21ssh12:09:137
107539993836,2cyclictest796970-21kworker/u16:4+events_unbound12:34:084
107550993736,0cyclictest0-21swapper/710:47:287
107546993735,2cyclictest562590-21kworker/u16:1+events_unbound10:46:126
107546993735,2cyclictest562590-21kworker/u16:1+events_unbound10:46:126
107546993735,2cyclictest188811-21kworker/u16:3+events_unbound08:02:286
107539993634,2cyclictest661562-21kworker/u16:5+events_unbound11:50:534
107550993534,0cyclictest0-21swapper/710:55:097
107546993533,2cyclictest562590-21kworker/u16:1+events_unbound10:41:056
107546993533,2cyclictest442653-21kworker/u16:4+events_unbound10:24:226
107542993533,2cyclictest587664-21kworker/u16:2+flush-8:010:52:525
107542993533,2cyclictest542176-21kworker/u16:0+events_unbound10:47:445
107542993533,2cyclictest405486-21kworker/u16:2+flush-8:009:47:225
107539993533,2cyclictest818585-21kworker/u16:0+events_unbound12:32:054
107539993533,2cyclictest587664-21kworker/u16:2+events_unbound10:59:214
107539993533,2cyclictest562590-21kworker/u16:1+events_unbound10:48:524
107539993533,2cyclictest405486-21kworker/u16:2+events_unbound10:07:284
107539993533,2cyclictest405486-21kworker/u16:2+events_unbound09:58:424
107539993532,2cyclictest711613-21kworker/u16:3+events_unbound12:02:274
107539993532,2cyclictest711613-21kworker/u16:3+events_unbound12:02:274
107539993532,2cyclictest661562-21kworker/u16:5+flush-8:011:29:454
107539993532,2cyclictest149837-21kworker/u16:2+flush-8:007:37:294
107550993433,0cyclictest0-21swapper/711:03:537
107542993432,2cyclictest661561-21kworker/u16:4+events_unbound11:20:245
107539993432,2cyclictest587664-21kworker/u16:2+events_unbound10:53:004
107539993432,2cyclictest526293-21kworker/u16:2+events_unbound10:29:494
107539993432,2cyclictest442652-21kworker/u16:3+flush-8:009:55:334
107550993332,0cyclictest0-21swapper/711:20:167
107550993332,0cyclictest0-21swapper/710:58:137
107550993332,0cyclictest0-21swapper/709:40:017
107550993331,1cyclictest783132-21ssh12:05:137
107550993331,1cyclictest783132-21ssh12:05:137
107539993331,2cyclictest769936-21kworker/u16:2+events_unbound12:09:054
107539993331,2cyclictest735687-21kworker/u16:1+events_unbound11:59:214
107539993331,2cyclictest711613-21kworker/u16:3+events_unbound12:15:484
107539993331,2cyclictest709289-21kworker/u16:0+events_unbound11:37:044
107539993331,2cyclictest660557-21kworker/u16:0+events_unbound11:25:444
107539993331,2cyclictest660557-21kworker/u16:0+events_unbound11:25:444
107539993331,2cyclictest542176-21kworker/u16:0+events_unbound10:36:534
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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