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2026-03-18 - 00:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Tue Mar 17, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
84502625948,7sleep60-21swapper/607:00:426
845523995351,2cyclictest1321146-21kworker/u16:4+events_unbound11:13:395
845536995044,5cyclictest887382-21latency_hist07:23:397
845519995046,3cyclictest1415128-21kworker/u16:3+flush-8:011:43:384
845536994842,5cyclictest954297-21latency_hist07:58:387
84521424737,7sleep50-21swapper/507:03:225
845528994543,2cyclictest762722-21kworker/u16:2+flush-8:007:43:396
845528994543,2cyclictest1440001-21kworker/u16:1+events_unbound11:33:136
84520224535,7sleep40-21swapper/407:03:134
845528994442,2cyclictest1475411-21kworker/u16:1+events_unbound12:05:116
845528994442,2cyclictest1475411-21kworker/u16:1+events_unbound12:05:116
845536994341,1cyclictest1078773-21diskmemload09:14:167
845523994341,2cyclictest1452971-21kworker/u16:2+events_unbound12:16:015
845523994341,2cyclictest1415128-21kworker/u16:3+events_unbound11:30:005
845523994341,2cyclictest1342347-21kworker/u16:5+events_unbound11:02:405
845523994341,2cyclictest1321146-21kworker/u16:4+flush-8:010:54:055
845523994341,2cyclictest1031293-21kworker/u16:0+events_unbound09:21:325
845528994240,2cyclictest1296090-21kworker/u16:2+events_unbound10:35:016
845528994240,2cyclictest1126116-21kworker/u16:2+events_unbound09:31:326
845528994240,2cyclictest1011445-21kworker/u16:1+events_unbound09:12:336
845523994240,2cyclictest1200044-21kworker/u16:0+events_unbound10:28:035
845523994240,2cyclictest1200044-21kworker/u16:0+events_unbound09:59:565
845523994240,2cyclictest1163462-21kworker/u16:2+events_unbound09:52:485
845523994240,2cyclictest1151115-21kworker/u16:1+events_unbound09:54:365
845519994239,2cyclictest1499618-21kworker/u16:4+events_unbound12:18:554
845536994140,0cyclictest0-21swapper/711:32:197
845536994140,0cyclictest0-21swapper/710:59:487
845536994136,4cyclictest1021300-21latency_hist08:33:387
845528994139,2cyclictest1440001-21kworker/u16:1+events_unbound11:36:486
845528994139,2cyclictest1296090-21kworker/u16:2+events_unbound11:08:286
845528994139,2cyclictest1163462-21kworker/u16:2+events_unbound10:25:016
845523994139,2cyclictest1415128-21kworker/u16:3+events_unbound11:34:125
845523994139,2cyclictest1296090-21kworker/u16:2+events_unbound10:35:445
845523994139,2cyclictest1151115-21kworker/u16:1+events_unbound09:47:125
845523994139,2cyclictest1011445-21kworker/u16:1+events_unbound09:17:445
845536994038,1cyclictest1537787-21ssh12:13:007
845536994038,1cyclictest1078773-21diskmemload10:54:367
845536994035,4cyclictest1381265-21latency_hist11:08:387
845528994038,2cyclictest1151115-21kworker/u16:1+events_unbound10:20:296
845528994038,2cyclictest1151115-21kworker/u16:1+events_unbound09:51:156
845523994038,2cyclictest1415128-21kworker/u16:3+events_unbound11:42:035
845523994038,2cyclictest1296090-21kworker/u16:2+events_unbound11:10:165
845536993937,1cyclictest1404664-21ssh11:17:167
845536993937,1cyclictest1186876-21ssh09:47:087
845528993937,2cyclictest1452971-21kworker/u16:2+events_unbound11:40:006
845528993937,2cyclictest1163462-21kworker/u16:2+events_unbound09:44:326
845528993937,2cyclictest1151115-21kworker/u16:1+events_unbound09:37:326
845528993937,2cyclictest1031293-21kworker/u16:0+events_unbound09:20:326
845523993937,2cyclictest1499618-21kworker/u16:4+events_unbound12:07:595
845523993937,2cyclictest1499618-21kworker/u16:4+events_unbound12:07:595
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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