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2026-03-21 - 10:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sat Mar 21, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
337696325141,7sleep60-21swapper/619:02:496
337696325141,7sleep60-21swapper/619:02:496
337674425141,7sleep50-21swapper/518:59:435
337674425141,7sleep50-21swapper/518:59:435
337699024838,7sleep40-21swapper/419:03:114
337699024838,7sleep40-21swapper/419:03:114
3377311994641,4cyclictest3693561-21latency_hist21:38:247
3377311994641,4cyclictest3693561-21latency_hist21:38:247
3377311994136,4cyclictest3872075-21latency_hist22:53:247
33686662402,32sleep70-21swapper/718:58:417
33686662402,32sleep70-21swapper/718:58:417
3377308993735,2cyclictest3824567-21kworker/u16:3+events_unbound23:13:536
37533432330,1chrt0-21swapper/622:03:256
3377311993330,2cyclictest902-21dbus-daemon23:28:247
36339432300,1sleep60-21swapper/621:13:246
3377311993029,0cyclictest0-21swapper/722:18:467
3377311993023,5cyclictest650-21systemd-journal21:58:257
3377308993028,2cyclictest3657848-21kworker/u16:4+events_unbound21:38:466
3377308993026,3cyclictest3349714-21kworker/u16:0+events_unbound20:18:376
3377302993027,2cyclictest3824567-21kworker/u16:3+events_unbound23:23:394
3377308992927,2cyclictest3967230-21kworker/u16:2+events_unbound23:33:496
3377308992927,2cyclictest3967230-21kworker/u16:2+events_unbound23:33:496
3377308992926,2cyclictest3824567-21kworker/u16:3+flush-8:022:43:406
3377311992823,4cyclictest3919746-21latency_hist23:13:247
3377302992825,2cyclictest4048422-21kworker/u16:4+flush-8:000:13:234
3377311992725,1cyclictest0-21swapper/722:08:427
3377311992724,2cyclictest3429793-21hddtemp_smartct19:28:397
3377308992725,2cyclictest3848480-21kworker/u16:1+events_unbound22:58:466
3377308992725,2cyclictest3572211-21kworker/u16:1+flush-8:022:04:376
337731199260,24cyclictest3485930-21latency_hist19:58:247
3377308992623,2cyclictest4048422-21kworker/u16:4+flush-8:000:13:396
3377308992622,3cyclictest3943441-21kworker/u16:0+flush-8:000:28:426
3377302992623,3cyclictest3349714-21kworker/u16:0+events_unbound19:43:504
3377308992524,1cyclictest3349714-21kworker/u16:0+events_unbound21:34:056
3377308992524,1cyclictest3349714-21kworker/u16:0+events_unbound21:34:056
3377302992523,2cyclictest3505379-21kworker/u16:2+events_unbound20:38:504
3377308992422,2cyclictest3505379-21kworker/u16:2+flush-8:020:13:406
3377308992420,3cyclictest3943441-21kworker/u16:0+flush-8:000:18:296
3377302992422,2cyclictest3349714-21kworker/u16:0+events_unbound21:38:374
3377311992322,0cyclictest0-21swapper/719:13:427
3377311992322,0cyclictest0-21swapper/700:03:407
3377311992321,1cyclictest0-21swapper/721:08:417
3377308992320,2cyclictest3728156-21kworker/u16:3+flush-8:021:53:246
3377311992222,0cyclictest0-21swapper/723:58:457
3377311992221,0cyclictest0-21swapper/723:28:447
3377311992219,2cyclictest3941131-21ssh23:18:537
3377308992220,2cyclictest3349714-21kworker/u16:0+events_unbound19:43:386
3377308992219,2cyclictest3715400-21kworker/u16:2+flush-8:021:48:246
3377302992220,2cyclictest3801198-21kworker/u16:1+events_unbound22:23:394
3377311992119,1cyclictest0-21swapper/720:28:257
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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