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2026-04-24 - 08:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Fri Apr 24, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122660825646,7sleep40-21swapper/419:07:014
1227081994945,3cyclictest1725722-21kworker/u16:0+flush-8:000:14:226
1227081994541,3cyclictest1521667-21kworker/u16:4+flush-8:022:09:236
12183752423,32sleep70-21swapper/719:04:397
1227083994135,5cyclictest1593928-21latency_hist22:04:237
1227078994037,2cyclictest1725722-21kworker/u16:0+events_unbound00:26:305
1227078993734,2cyclictest1725722-21kworker/u16:0+flush-8:000:19:055
1227078993734,2cyclictest1725722-21kworker/u16:0+flush-8:000:19:055
1227081993634,2cyclictest1518260-21kworker/u16:0+events_unbound22:09:386
1227078993634,2cyclictest1787342-21kworker/u16:1+events_unbound23:50:305
122658723627,6sleep50-21swapper/519:06:465
1227081993533,2cyclictest1326446-21kworker/u16:0+flush-8:020:24:246
1227078993533,2cyclictest1772831-21kworker/u16:4+events_unbound00:08:145
1227078993533,2cyclictest1725722-21kworker/u16:0+events_unbound23:02:025
1227078993533,2cyclictest1606135-21kworker/u16:3+flush-8:022:15:425
1227078993533,2cyclictest1521667-21kworker/u16:4+events_unbound22:06:545
1227081993430,3cyclictest1653810-21kworker/u16:1+flush-8:022:39:246
1227078993432,2cyclictest1954350-21kworker/u16:1+flush-8:000:37:415
1227078993432,2cyclictest1772831-21kworker/u16:4+flush-8:023:24:495
1227078993432,2cyclictest1772831-21kworker/u16:4+events_unbound00:10:175
1227078993432,2cyclictest1700275-21kworker/u16:3+events_unbound23:12:105
1227078993432,2cyclictest1653810-21kworker/u16:1+events_unbound22:39:095
1227078993432,2cyclictest1569856-21kworker/u16:1+events_unbound22:04:105
1227078993432,2cyclictest1518260-21kworker/u16:0+events_unbound22:25:305
1227078993331,2cyclictest1810783-21kworker/u16:2+flush-8:000:00:175
1227078993331,2cyclictest1810783-21kworker/u16:2+events_unbound23:57:505
1227078993331,2cyclictest1772831-21kworker/u16:4+events_unbound23:38:235
1227078993331,2cyclictest1772831-21kworker/u16:4+events_unbound23:38:235
1227078993331,2cyclictest1739404-21kworker/u16:2+events_unbound23:21:575
1227078993331,2cyclictest1725722-21kworker/u16:0+events_unbound23:06:385
1227078993331,2cyclictest1518260-21kworker/u16:0+flush-8:022:12:505
1227078993331,2cyclictest1518260-21kworker/u16:0+events_unbound21:58:145
1227078993331,2cyclictest1461286-21kworker/u16:3+events_unbound21:38:555
1227078993331,2cyclictest1461286-21kworker/u16:3+events_unbound21:10:585
1227078993331,2cyclictest1336082-21kworker/u16:1+events_unbound21:31:145
1227078993230,2cyclictest1954350-21kworker/u16:1+events_unbound00:32:395
1227078993230,2cyclictest1810783-21kworker/u16:2+events_unbound00:23:095
1227078993230,2cyclictest1725722-21kworker/u16:0+events_unbound23:43:095
1227078993230,2cyclictest1700275-21kworker/u16:3+flush-8:022:49:225
1227078993230,2cyclictest1666380-21kworker/u16:2+events_unbound22:53:215
1227078993230,2cyclictest1521667-21kworker/u16:4+flush-8:021:44:105
1227078993230,2cyclictest1518260-21kworker/u16:0+flush-8:021:53:035
1227078993230,2cyclictest1518260-21kworker/u16:0+flush-8:021:48:345
1227078993230,2cyclictest1461286-21kworker/u16:3+flush-8:021:22:505
1227083993130,0cyclictest0-21swapper/700:29:027
1227078993129,2cyclictest1810783-21kworker/u16:2+events_unbound23:46:385
1227078993129,2cyclictest1739404-21kworker/u16:2+events_unbound23:17:115
1227078993129,2cyclictest1521667-21kworker/u16:4+flush-8:022:40:035
1227078993129,2cyclictest1521667-21kworker/u16:4+events_unbound22:24:025
1227078993129,2cyclictest1336082-21kworker/u16:1+events_unbound21:28:105
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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