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2026-05-13 - 18:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Wed May 13, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41503772660,0sleep60-21swapper/611:43:356
3529332995350,2cyclictest3640386-21kworker/u16:4+flush-8:008:18:314
352902025343,7sleep40-21swapper/407:08:004
3529337994947,2cyclictest3619693-21kworker/u16:3+flush-8:008:03:205
3529332994846,2cyclictest3735231-21kworker/u16:1+flush-8:010:43:214
3529332994846,2cyclictest3590327-21kworker/u16:2+events_unbound10:53:324
3529332994442,2cyclictest54808-21kworker/u16:4+flush-8:012:28:314
3529332994441,2cyclictest4139905-21kworker/u16:1+flush-8:011:43:194
3529332994441,2cyclictest3590327-21kworker/u16:2+flush-8:009:48:074
3529332994341,2cyclictest3958351-21kworker/u16:3+events_unbound11:33:404
3529337994240,2cyclictest3763845-21kworker/u16:4+events_unbound09:13:315
3529332994139,2cyclictest4111123-21kworker/u16:4+flush-8:012:03:354
35287172416,30sleep70-21swapper/707:03:457
3529332994038,2cyclictest4111123-21kworker/u16:4+events_unbound11:50:154
3529332994038,2cyclictest3735231-21kworker/u16:1+events_unbound09:22:284
3529332993937,2cyclictest3590327-21kworker/u16:2+events_unbound10:43:034
3529332993937,2cyclictest32020-21kworker/u16:2+events_unbound12:18:234
3529332993937,2cyclictest32020-21kworker/u16:2+events_unbound12:18:234
3529332993936,2cyclictest54808-21kworker/u16:4+events_unbound12:33:384
3529332993936,2cyclictest4153428-21kworker/u16:3+events_unbound11:58:084
3529332993836,2cyclictest3590327-21kworker/u16:2+events_unbound11:23:074
3529332993835,2cyclictest3735231-21kworker/u16:1+events_unbound11:18:334
3529332993735,2cyclictest4030756-21kworker/u16:4+events_unbound11:05:514
3529332993734,2cyclictest54808-21kworker/u16:4+events_unbound12:27:444
3529332993734,2cyclictest3958351-21kworker/u16:3+flush-8:010:31:074
352934599360,34cyclictest827-21dbus-daemon12:18:057
3529332993634,2cyclictest7553-21kworker/u16:0+events_unbound12:17:314
3529332993634,2cyclictest4111123-21kworker/u16:4+flush-8:012:08:314
3529332993633,2cyclictest4030756-21kworker/u16:4+events_unbound10:58:084
3529332993633,2cyclictest3763845-21kworker/u16:4+events_unbound09:36:564
3529332993633,2cyclictest3590327-21kworker/u16:2+events_unbound09:28:084
3529332993533,2cyclictest3735231-21kworker/u16:1+events_unbound09:56:074
3529332993532,2cyclictest3958351-21kworker/u16:3+events_unbound10:36:284
3529341993431,2cyclictest3735231-21kworker/u16:1+events_unbound10:23:196
3529332993432,2cyclictest3763845-21kworker/u16:4+events_unbound09:41:374
352872723423,8sleep60-21swapper/607:03:526
352934599330,31cyclictest3735001-21latency_hist08:53:067
3529337993331,2cyclictest3590327-21kworker/u16:2+events_unbound10:28:305
3529332993331,2cyclictest4153428-21kworker/u16:3+flush-8:011:56:074
3529332993331,2cyclictest4103126-21kworker/u16:0+events_unbound11:28:244
3529332993331,2cyclictest3763846-21kworker/u16:5+events_unbound10:10:234
3529332993331,2cyclictest3763845-21kworker/u16:4+flush-8:009:43:514
3529332993330,2cyclictest3763845-21kworker/u16:4+events_unbound09:24:124
352934599320,30cyclictest4019548-21latency_hist10:53:057
352874423222,7sleep50-21swapper/507:04:075
3529345993126,4cyclictest3849173-21latency_hist09:43:067
3529332993129,2cyclictest3763846-21kworker/u16:5+events_unbound10:00:274
3529332993129,2cyclictest3590327-21kworker/u16:2+events_unbound11:10:114
3529332993129,2cyclictest3590327-21kworker/u16:2+events_unbound10:48:354
38684682300,1chrt0-21swapper/509:48:255
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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