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2026-05-05 - 17:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Tue May 05, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1456471995654,2cyclictest1781090-21kworker/u16:1+events_unbound10:14:006
1456467995654,2cyclictest1839405-21kworker/u16:2+events_unbound10:29:045
145595825545,7sleep40-21swapper/407:05:494
17068472540,0sleep71706850-21cut09:13:567
1456471995452,2cyclictest1613264-21kworker/u16:3+events_unbound08:59:076
1456471995451,2cyclictest1479493-21kworker/u16:4+events_unbound07:38:536
1456467995451,2cyclictest1768290-21kworker/u16:0+flush-8:011:13:525
1456467995351,2cyclictest1768290-21kworker/u16:0+events_unbound11:59:085
1456467995250,2cyclictest1768290-21kworker/u16:0+events_unbound10:19:085
1456467995249,2cyclictest1986607-21kworker/u16:1+flush-8:012:13:535
1456467995249,2cyclictest1565991-21kworker/u16:4+flush-8:008:13:535
145593225141,7sleep50-21swapper/507:05:265
1456471995047,2cyclictest1768290-21kworker/u16:0+events_unbound11:13:506
1456467995047,2cyclictest2034686-21kworker/u16:3+events_unbound12:09:085
1456467994845,2cyclictest1662357-21kworker/u16:1+flush-8:009:24:065
1456467994845,2cyclictest1613264-21kworker/u16:3+flush-8:008:58:525
1456471994644,2cyclictest1768290-21kworker/u16:0+flush-8:011:29:036
1456471994644,2cyclictest1768290-21kworker/u16:0+events_unbound10:39:106
1456471994644,2cyclictest1768290-21kworker/u16:0+events_unbound10:39:106
1456467994644,2cyclictest2034686-21kworker/u16:3+flush-8:012:34:055
1456471994543,2cyclictest1768290-21kworker/u16:0+events_unbound11:54:116
1456467994543,2cyclictest1662357-21kworker/u16:1+events_unbound09:13:525
1456471994442,2cyclictest1728495-21kworker/u16:4+flush-8:009:34:086
1456471994442,2cyclictest1585079-21kworker/u16:1+events_unbound08:29:076
1456471994442,2cyclictest1522023-21kworker/u16:0+events_unbound07:54:086
1456467994441,2cyclictest1585079-21kworker/u16:1+flush-8:008:38:535
1456467994441,2cyclictest1454527-21kworker/u16:1+events_unbound07:49:075
1456467994441,2cyclictest1454527-21kworker/u16:1+events_unbound07:49:075
1456467994441,2cyclictest1193014-21kworker/u16:3+events_unbound07:28:535
1456472994341,1cyclictest1848512-21ssh10:24:097
1456472994340,2cyclictest1564951-21ntpq07:59:057
1456472994339,2cyclictest2105955-21ssh12:09:067
1456471994341,2cyclictest1839405-21kworker/u16:2+events_unbound11:04:116
1456467994341,2cyclictest2109265-21kworker/u16:4+flush-8:012:19:085
1456467994339,4cyclictest1768290-21kworker/u16:0+flush-8:011:03:385
1456472994239,2cyclictest1594218-21smart_sda08:14:067
145647299420,40cyclictest2170568-21latency_hist12:38:377
1456467994240,2cyclictest1986607-21kworker/u16:1+events_unbound11:33:575
1456471994138,2cyclictest1715090-21kworker/u16:2+events_unbound09:18:536
1456467994139,2cyclictest1986607-21kworker/u16:1+events_unbound11:39:045
14473582413,31sleep70-21swapper/707:03:527
1456472994039,0cyclictest0-21swapper/707:44:067
1456471994038,2cyclictest1768290-21kworker/u16:0+flush-8:010:44:066
1456467994038,2cyclictest1537187-21kworker/u16:2+events_unbound07:59:385
1456467994038,2cyclictest1479493-21kworker/u16:4+events_unbound07:34:065
1456472993938,0cyclictest0-21swapper/710:45:577
1456471993937,2cyclictest2034686-21kworker/u16:3+events_unbound12:35:296
1456471993937,2cyclictest2034686-21kworker/u16:3+events_unbound12:24:036
1456471993937,2cyclictest1986607-21kworker/u16:1+events_unbound12:17:446
1456471993937,2cyclictest1839405-21kworker/u16:2+events_unbound10:35:416
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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