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2026-06-03 - 13:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Wed Jun 03, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
142815525747,7sleep40-21swapper/407:05:064
142796824922,8sleep50-21swapper/507:02:265
1428558994845,2cyclictest1566072-21kworker/u16:2+flush-8:008:26:426
1428551994139,2cyclictest1820729-21kworker/u16:3+flush-8:010:42:084
14273232402,31sleep70-21swapper/707:02:127
1428554993836,2cyclictest1442202-21kworker/u16:0+events_unbound09:42:395
142856099370,35cyclictest124-21kswapd012:06:577
1428554993735,2cyclictest1820729-21kworker/u16:3+events_unbound10:42:065
1428554993432,2cyclictest2086959-21kworker/u16:4+events_unbound12:07:045
1428560993328,4cyclictest1808498-21latency_hist10:06:427
1428558993229,2cyclictest1932149-21kworker/u16:0+events_unbound11:11:426
1428554993230,2cyclictest2124381-21kworker/u16:3+events_unbound12:32:095
1428554993230,2cyclictest1820729-21kworker/u16:3+events_unbound10:37:095
142804323222,7sleep60-21swapper/607:03:326
1428560993126,4cyclictest1499456-21latency_hist07:41:437
1428558993129,2cyclictest1442202-21kworker/u16:0+flush-8:009:42:076
1428554993129,2cyclictest2124382-21kworker/u16:4+events_unbound12:29:585
1428554993129,2cyclictest1932149-21kworker/u16:0+events_unbound12:04:345
1428554993129,2cyclictest1905831-21kworker/u16:4+events_unbound10:47:385
1428554993129,2cyclictest1735445-21kworker/u16:1+events_unbound09:52:555
1428554993129,2cyclictest1409157-21kworker/u16:3+events_unbound07:18:415
1428551993129,2cyclictest1675457-21kworker/u16:4+events_unbound09:17:074
1428558993028,2cyclictest1735445-21kworker/u16:1+flush-8:010:02:216
1428558993028,2cyclictest1653755-21kworker/u16:2+events_unbound09:07:076
1428554993028,2cyclictest1932149-21kworker/u16:0+events_unbound12:21:185
1428554993028,2cyclictest1841811-21kworker/u16:0+events_unbound10:30:475
1428554993028,2cyclictest1841811-21kworker/u16:0+events_unbound10:25:075
1428554993028,2cyclictest1735445-21kworker/u16:1+events_unbound10:17:015
1428554993028,2cyclictest1442202-21kworker/u16:0+flush-8:010:10:555
1428554993028,2cyclictest1442202-21kworker/u16:0+events_unbound09:10:385
1428554992927,2cyclictest1932149-21kworker/u16:0+events_unbound11:28:175
1428554992927,2cyclictest1932149-21kworker/u16:0+events_unbound11:25:385
1428554992927,2cyclictest1566072-21kworker/u16:2+events_unbound08:39:165
1428554992927,2cyclictest1499647-21kworker/u16:1+events_unbound07:51:175
1428554992927,2cyclictest1442202-21kworker/u16:0+events_unbound08:28:255
1428554992927,2cyclictest1409158-21kworker/u16:4+events_unbound07:32:105
1428551992927,2cyclictest1442202-21kworker/u16:0+flush-8:008:12:124
20623452280,1chrt2062346-21ssh11:51:017
1428554992826,2cyclictest2124382-21kworker/u16:4+events_unbound12:24:535
1428554992826,2cyclictest1987095-21kworker/u16:3+flush-8:012:01:055
1428554992826,2cyclictest1987095-21kworker/u16:3+events_unbound11:41:505
1428554992826,2cyclictest1987095-21kworker/u16:3+events_unbound11:33:335
1428554992826,2cyclictest1987095-21kworker/u16:3+events_unbound11:33:335
1428554992826,2cyclictest1932149-21kworker/u16:0+events_unbound11:20:305
1428554992826,2cyclictest1820729-21kworker/u16:3+events_unbound10:12:375
1428554992826,2cyclictest1735445-21kworker/u16:1+events_unbound09:57:385
1428554992826,2cyclictest1653755-21kworker/u16:2+events_unbound10:03:065
1428554992826,2cyclictest1566072-21kworker/u16:2+events_unbound08:18:255
1428554992826,2cyclictest1409157-21kworker/u16:3+events_unbound07:24:255
1428554992825,2cyclictest1409158-21kworker/u16:4+events_unbound07:41:475
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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