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2026-05-17 - 22:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sun May 17, 2026 12:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
93412721010,1sleep70-21swapper/711:03:097
93412721010,1sleep70-21swapper/711:03:097
107381921010,1sleep71073818-21ssh11:58:477
416330995452,2cyclictest967092-21kworker/u16:4+events_unbound11:48:154
416330994846,2cyclictest583748-21kworker/u16:2+events_unbound08:33:154
416330994745,2cyclictest563272-21kworker/u16:4+events_unbound09:13:164
41583124736,7sleep50-21swapper/507:05:005
416342994641,4cyclictest918072-21latency_hist10:57:497
416342994641,3cyclictest1051853-21latency_hist11:52:507
628089450,38rtkit-daemon0-21swapper/407:05:204
416342994539,5cyclictest583507-21latency_hist08:32:507
416330994341,2cyclictest1004958-21kworker/u16:3+events_unbound11:44:154
416330994341,2cyclictest1004958-21kworker/u16:3+events_unbound11:44:154
4068192403,31sleep70-21swapper/707:02:537
416330993937,2cyclictest902998-21kworker/u16:2+events_unbound10:57:404
416330993937,2cyclictest784580-21kworker/u16:4+flush-8:010:33:054
416330993936,2cyclictest967092-21kworker/u16:4+events_unbound11:36:434
416330993836,2cyclictest747975-21kworker/u16:3+events_unbound10:00:364
416330993836,2cyclictest667068-21kworker/u16:0+flush-8:009:44:234
416330993836,2cyclictest667068-21kworker/u16:0+flush-8:009:44:234
416330993735,2cyclictest967092-21kworker/u16:4+flush-8:011:26:474
416330993735,2cyclictest699342-21kworker/u16:1+events_unbound09:40:404
416330993731,6cyclictest954990-21kworker/u16:0+events_unbound11:22:354
416342993630,5cyclictest564285-21latency_hist08:22:507
416330993634,2cyclictest967092-21kworker/u16:4+events_unbound12:02:524
416330993634,2cyclictest929569-21kworker/u16:1+events_unbound11:32:354
416330993634,2cyclictest915654-21kworker/u16:0+events_unbound11:01:444
416330993634,2cyclictest882091-21kworker/u16:0+events_unbound10:46:594
416330993634,2cyclictest782039-21kworker/u16:1+events_unbound10:24:404
416330993634,2cyclictest782039-21kworker/u16:1+events_unbound10:24:404
416330993634,2cyclictest747975-21kworker/u16:3+events_unbound10:28:564
416330993634,2cyclictest722782-21kworker/u16:2+events_unbound10:39:554
416330993634,2cyclictest722782-21kworker/u16:2+events_unbound09:52:434
416330993634,2cyclictest583748-21kworker/u16:2+events_unbound09:24:564
416330993634,2cyclictest1124631-21kworker/u16:1+flush-8:012:32:494
416330993634,2cyclictest1004957-21kworker/u16:2+flush-8:012:25:404
416330993633,2cyclictest784580-21kworker/u16:4+events_unbound10:12:124
416330993533,2cyclictest942415-21kworker/u16:3+events_unbound11:09:004
416330993432,2cyclictest967092-21kworker/u16:4+events_unbound11:53:554
416330993432,2cyclictest1076083-21kworker/u16:3+events_unbound12:14:034
416330993432,2cyclictest1004957-21kworker/u16:2+events_unbound12:10:124
41597423411,7sleep60-21swapper/607:07:016
416330993331,2cyclictest967092-21kworker/u16:4+events_unbound11:41:364
416330993331,2cyclictest782039-21kworker/u16:1+events_unbound10:06:454
416330993331,2cyclictest747975-21kworker/u16:3+events_unbound10:49:594
416330993331,2cyclictest699342-21kworker/u16:1+events_unbound09:29:554
416330993331,2cyclictest672451-21kworker/u16:3+events_unbound09:20:074
416330993331,2cyclictest1051854-21kworker/u16:1+events_unbound12:02:154
416330993331,2cyclictest1004957-21kworker/u16:2+events_unbound12:37:304
416330993331,2cyclictest1004957-21kworker/u16:2+events_unbound12:19:514
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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