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2024-04-19 - 23:01

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot2s.osadl.org (updated Fri Apr 19, 2024 12:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107568699447446,1cyclictest1222714-21kworker/9:2+events11:51:399
107568699447446,1cyclictest1209287-21kworker/9:0+events11:27:229
107568699447446,1cyclictest1205154-21kworker/9:2+events11:18:039
107568699447446,1cyclictest1166258-21kworker/9:2+events10:39:449
107568699447446,1cyclictest1150157-21kworker/9:0+events09:42:469
107568699447446,1cyclictest1133547-21kworker/9:2+events08:59:189
107568699447446,1cyclictest1089128-21kworker/9:1+events07:41:379
107568699447446,1cyclictest1075180-21kworker/9:1+events07:14:519
107568699447445,2cyclictest1196240-21kworker/9:1+events11:20:429
107568699446445,1cyclictest1233164-21kworker/9:0+events12:38:279
107568699446445,1cyclictest1233164-21kworker/9:0+events12:18:599
107568699446445,1cyclictest1225391-21kworker/9:1+events12:11:179
107568699446445,1cyclictest1225391-21kworker/9:1+events12:03:259
107568699446445,1cyclictest1225391-21kworker/9:1+events11:59:079
107568699446445,1cyclictest1196240-21kworker/9:1+events11:11:259
107568699446445,1cyclictest1188206-21kworker/9:0+events11:00:429
107568699446445,1cyclictest1166258-21kworker/9:2+events10:28:029
107568699446445,1cyclictest1166258-21kworker/9:2+events10:08:479
107568699446445,1cyclictest1158203-21kworker/9:1+events10:17:579
107568699446445,1cyclictest1158203-21kworker/9:1+events10:02:159
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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