You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-05 - 12:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa [ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot3.osadl.org (updated Thu Feb 05, 2026 00:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
406271099399399,0cyclictest0-21swapper/123:44:591
406271099399399,0cyclictest0-21swapper/122:27:591
40622402388369,13sleep80-21swapper/819:06:4414
40623122364321,15sleep70-21swapper/719:07:4613
40622192363324,32sleep60-21swapper/619:06:2512
40624312360322,32sleep150-21swapper/1519:09:167
40622902347326,14sleep40-21swapper/419:07:2710
40624692346306,13sleep90-21swapper/919:09:4215
40622062346328,12sleep100-21swapper/1019:06:132
40624052341321,14sleep120-21swapper/1219:08:564
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional