You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-21 - 13:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa [ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot3.osadl.org (updated Wed Jan 21, 2026 00:45:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
167512999395395,0cyclictest0-21swapper/1123:52:003
167512999395395,0cyclictest0-21swapper/1121:06:593
16747002354315,13sleep110-21swapper/1119:07:043
16748392351311,13sleep40-21swapper/419:09:0510
16743582350329,14sleep120-21swapper/1219:05:284
16747822349332,11sleep20-21swapper/219:08:158
16746322346325,14sleep150-21swapper/1519:06:037
16745982346327,13sleep60-21swapper/619:05:3812
16747432345304,14sleep00-21swapper/019:07:410
16717182345326,13sleep80-21swapper/819:05:0714
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional