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2026-08-08 - 13:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot3.osadl.org (updated Sat Aug 08, 2026 12:45:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38754822384365,13sleep120-21swapper/1207:05:284
38755852360353,5sleep00-21swapper/007:06:520
38757742351331,13sleep70-21swapper/707:09:2413
38754632346327,13sleep80-21swapper/807:05:2414
38726412346307,32sleep60-21swapper/607:05:0612
38756262344306,14sleep20-21swapper/207:07:268
38756222344325,13sleep150-21swapper/1507:07:247
38755912343324,13sleep50-21swapper/507:06:5811
38755572343326,11sleep100-21swapper/1007:06:312
38756282341321,14sleep30-21swapper/307:07:279
38756012341322,13sleep140-21swapper/1407:07:076
38755982340320,14sleep110-21swapper/1107:07:043
38755902338319,13sleep40-21swapper/407:06:5610
38757632336316,14sleep130-21swapper/1307:09:145
38743012336328,5sleep10-21swapper/107:05:161
38755212335310,14sleep90-21swapper/907:05:5715
387603999286282,4cyclictest2172-21Xorg11:07:005
387604099284281,3cyclictest2172-21Xorg09:40:006
3876034992840,284cyclictest0-21swapper/812:34:5814
387604099282279,3cyclictest2172-21Xorg09:51:006
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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