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2026-02-08 - 21:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa [ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot3.osadl.org (updated Sun Feb 08, 2026 12:45:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27687932374351,17sleep00-21swapper/007:08:070
276915999355354,1cyclictest0-21swapper/1410:52:596
27689102355314,14sleep70-21swapper/707:09:3513
27659162351310,14sleep150-21swapper/1507:05:107
27689162350313,13sleep120-21swapper/1207:09:404
27687632348311,14sleep80-21swapper/807:07:4414
27687782346325,14sleep50-21swapper/507:07:5611
27686122345324,14sleep60-21swapper/607:05:3212
27688222343323,14sleep90-21swapper/907:08:3315
27688632342323,13sleep100-21swapper/1007:09:062
27687342342317,14sleep130-21swapper/1307:07:175
27686782342321,14sleep140-21swapper/1407:06:306
27686492340319,14sleep40-21swapper/407:06:0410
27687012338319,13sleep30-21swapper/307:06:519
27688152335315,14sleep20-21swapper/207:08:268
27688142332313,13sleep10-21swapper/107:08:241
27686562330310,14sleep110-21swapper/1107:06:103
276915799284281,3cyclictest2211-21Xorg08:03:594
276915799283280,3cyclictest2211-21Xorg08:28:004
276915699283281,2cyclictest3272-21gnome-shell08:32:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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