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2025-07-01 - 15:06

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot3s.osadl.org (updated Thu Jun 05, 2025 00:44:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18709432255233,14sleep10-21swapper/119:05:411
18710302254234,13sleep70-21swapper/719:06:527
18712252251243,5sleep40-21swapper/419:09:294
18709772247212,13sleep60-21swapper/619:06:106
18711012241206,27sleep00-21swapper/019:07:490
18710762240231,6sleep20-21swapper/219:07:262
18712082238222,9sleep50-21swapper/519:09:145
18709452236217,12sleep30-21swapper/319:05:423
187155799360,35cyclictest0-21swapper/622:09:336
1871554993632,3cyclictest1391-21snmpd23:03:525
1871561993535,0cyclictest1835852-21kworker/7:2+events21:04:177
1871561993521,13cyclictest1835852-21kworker/7:2+events20:57:137
1871561993521,13cyclictest1835852-21kworker/7:2+events19:47:357
187155799350,1cyclictest0-21swapper/623:16:506
187154699350,34cyclictest0-21swapper/321:52:383
1871561993432,2cyclictest1977313-21cat22:20:167
187155799340,33cyclictest0-21swapper/620:56:256
187154699340,13cyclictest0-21swapper/322:37:093
1871561993333,0cyclictest1835852-21kworker/7:2+events20:33:177
1871542993332,1cyclictest1391-21snmpd20:05:332
1871542993332,1cyclictest1391-21snmpd20:05:322
1871546993131,0cyclictest0-21swapper/322:09:113
1871537993130,1cyclictest0-21swapper/020:02:260
1871551993029,1cyclictest1391-21snmpd20:27:114
1871551993029,1cyclictest1391-21snmpd00:01:424
1871542993030,0cyclictest0-21swapper/223:06:232
1871542993030,0cyclictest0-21swapper/219:25:052
1871542993030,0cyclictest0-21swapper/200:27:332
187154299300,30cyclictest0-21swapper/221:29:312
1871554992928,1cyclictest0-21swapper/519:17:155
1871551992928,1cyclictest1391-21snmpd23:28:024
1871542992929,0cyclictest0-21swapper/222:19:322
1871542992929,0cyclictest0-21swapper/221:53:412
1871542992929,0cyclictest0-21swapper/221:19:362
187154299290,0cyclictest0-21swapper/220:20:252
1871540992928,1cyclictest1391-21snmpd00:06:041
1871561992827,1cyclictest1935015-21kworker/7:1+events21:35:207
1871554992827,1cyclictest0-21swapper/523:54:245
1871546992826,1cyclictest1391-21snmpd00:35:403
1871542992828,0cyclictest0-21swapper/223:54:302
1871542992828,0cyclictest0-21swapper/221:36:402
1871542992828,0cyclictest0-21swapper/220:52:562
1871542992828,0cyclictest0-21swapper/220:01:492
1871542992828,0cyclictest0-21swapper/200:17:052
1871546992726,0cyclictest0-21swapper/300:27:173
1871542992727,0cyclictest0-21swapper/219:17:342
187154299270,27cyclictest0-21swapper/219:35:292
187154299270,27cyclictest0-21swapper/200:08:062
1871561992626,0cyclictest1986908-21kworker/7:2+events23:59:077
1871561992626,0cyclictest0-21swapper/700:36:347
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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