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2025-08-30 - 01:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot4.osadl.org (updated Sat Aug 30, 2025 00:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36938239954852,495cyclictest0-21swapper/721:20:2213
36938399954749,497cyclictest0-21swapper/1222:43:414
36938339954111,529cyclictest0-21swapper/1019:45:422
36938499954024,515cyclictest0-21swapper/1519:38:527
36938109953029,499cyclictest0-21swapper/322:35:329
36938109952831,496cyclictest0-21swapper/322:33:549
36938239952729,0cyclictest0-21swapper/719:45:4213
36938239952612,513cyclictest0-21swapper/719:52:5813
36938139952525,500cyclictest0-21swapper/423:33:4310
36938139952424,500cyclictest0-21swapper/423:58:4310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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