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2025-10-20 - 18:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot4.osadl.org (updated Mon Oct 20, 2025 00:46:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25475822387365,14sleep50-21swapper/519:05:5511
25477222363319,14sleep20-21swapper/219:07:468
25476212361312,15sleep80-21swapper/819:06:3014
25477682360315,15sleep140-21swapper/1419:08:296
25478972359312,15sleep150-21swapper/1519:09:527
25478562356338,7sleep100-21swapper/1019:09:312
25477772356313,15sleep00-21swapper/019:08:310
25476322356314,14sleep110-21swapper/1119:06:343
25477332355313,14sleep130-21swapper/1319:07:565
25477262354311,34sleep60-21swapper/619:07:5012
25476952354311,34sleep10-21swapper/119:07:281
25477122347337,7sleep120-21swapper/1219:07:394
25477072345321,15sleep70-21swapper/719:07:3513
25477242341318,14sleep40-21swapper/419:07:4710
25476032340317,15sleep90-21swapper/919:06:1515
25443112340315,17sleep30-21swapper/319:05:059
254830299318318,0cyclictest0-21swapper/520:20:1811
254830299318318,0cyclictest0-21swapper/520:20:1811
254828999307306,1cyclictest311rcuc/122:50:181
254831799230229,1cyclictest2740074-21nodev-device-ev22:50:1715
254832999210209,1cyclictest2624586-21nodev-device-ev20:35:185
254832999177176,1cyclictest2611775-21nodev-device-ev20:20:175
254832999177176,1cyclictest2611775-21nodev-device-ev20:20:175
254830299151151,0cyclictest0-21swapper/520:35:1811
2548319999998,1cyclictest0-21swapper/1023:15:202
2548332999291,1cyclictest2560457-21nodev-device-ev19:20:196
2548322998886,1cyclictest2568994-21nodev-device-ev19:30:183
2548329998786,1cyclictest2607514-21nodev-device-ev20:15:225
2548329998786,1cyclictest2607514-21nodev-device-ev20:15:215
2548302998786,1cyclictest0-21swapper/522:25:1911
2548307998584,1cyclictest2799944-21nodev-device-ev00:00:1812
2548319998479,2cyclictest2714423-21nodev-device-ev22:20:202
2548307998483,1cyclictest2795681-21nodev-device-ev23:55:2112
2548292998281,1cyclictest2808532-21nodev-device-ev00:10:208
2548325997170,1cyclictest2693031-21nodev-device-ev21:55:194
2548307997170,1cyclictest0-21swapper/622:45:1812
2548332997069,1cyclictest2658830-21nodev-device-ev21:15:216
2548292996968,1cyclictest0-21swapper/223:05:188
2548302996766,1cyclictest2633136-21nodev-device-ev20:45:1811
2548289996564,1cyclictest0-21swapper/119:25:191
2548297996362,1cyclictest0-21swapper/319:30:189
2548329996261,1cyclictest0-21swapper/1319:55:175
2548299996261,1cyclictest0-21swapper/421:55:1910
2548309995955,0cyclictest0-21swapper/722:52:0713
2548302995655,1cyclictest0-21swapper/521:40:1911
2548312995554,1cyclictest2620324-21nodev-device-ev20:30:1714
2548334995453,1cyclictest0-21swapper/1523:40:197
2548309995345,4cyclictest0-21swapper/721:28:5413
2548309995345,4cyclictest0-21swapper/721:02:0613
2548334995251,1cyclictest2641690-21nodev-device-ev20:55:207
2548309995248,0cyclictest0-21swapper/720:35:3813
2548322995150,1cyclictest0-21swapper/1121:10:193
2548309995049,1cyclictest2782835-21nodev-device-ev23:40:1813
2548309994945,4cyclictest0-21swapper/700:02:3013
2548309994847,1cyclictest0-21swapper/720:55:2013
2548309994844,0cyclictest0-21swapper/722:04:2313
254830999456,1cyclictest201rcu_preempt20:45:2213
2548309994436,4cyclictest0-21swapper/700:07:5813
2548329994343,0cyclictest0-21swapper/1322:29:235
2548329994343,0cyclictest0-21swapper/1320:06:235
2548329994343,0cyclictest0-21swapper/1319:40:105
2548329994242,0cyclictest0-21swapper/1322:40:105
2548309994238,4cyclictest0-21swapper/721:37:5913
2548309994219,23cyclictest0-21swapper/723:06:5913
2548329994141,0cyclictest0-21swapper/1322:58:525
254830999417,34cyclictest0-21swapper/722:42:4313
254830999415,36cyclictest0-21swapper/723:47:1413
2548309994118,23cyclictest0-21swapper/721:20:3813
254830999411,1cyclictest861ktimers/722:59:5513
254830999402,34cyclictest87-21ksoftirqd/719:49:5913
2548325993939,0cyclictest0-21swapper/1200:10:274
2548329993838,0cyclictest0-21swapper/1319:35:325
2548329993838,0cyclictest0-21swapper/1300:33:555
254830999383,35cyclictest0-21swapper/723:14:3913
254830999383,35cyclictest0-21swapper/722:17:1613
254830999383,0cyclictest0-21swapper/721:13:5013
2548329993737,0cyclictest0-21swapper/1319:49:025
2548325993737,0cyclictest0-21swapper/1219:55:144
2548325993736,1cyclictest2829915-21kworker/12:0-mm_percpu_wq00:35:474
254830999379,0cyclictest0-21swapper/721:47:4113
254830999374,33cyclictest0-21swapper/723:56:5213
254830999373,34cyclictest0-21swapper/723:21:5113
254830999373,34cyclictest0-21swapper/723:21:5113
2548329993636,0cyclictest0-21swapper/1323:25:415
2548329993636,0cyclictest0-21swapper/1323:25:405
2548329993636,0cyclictest0-21swapper/1323:23:165
2548329993636,0cyclictest0-21swapper/1323:23:165
2548329993636,0cyclictest0-21swapper/1323:02:265
2548329993636,0cyclictest0-21swapper/1322:00:445
2548329993636,0cyclictest0-21swapper/1321:40:585
2548329993636,0cyclictest0-21swapper/1320:27:335
2548329993636,0cyclictest0-21swapper/1320:10:455
2548329993636,0cyclictest0-21swapper/1320:10:445
2548329993636,0cyclictest0-21swapper/1300:29:155
2548325993636,0cyclictest0-21swapper/1221:36:124
2548325993636,0cyclictest0-21swapper/1220:55:014
254830999362,0cyclictest0-21swapper/721:15:4813
254830999361,35cyclictest87-21ksoftirqd/719:32:5513
254830999360,0cyclictest0-21swapper/722:47:3313
254832999350,35cyclictest0-21swapper/1319:52:065
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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