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2025-11-25 - 11:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot4.osadl.org (updated Tue Nov 25, 2025 00:46:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18000142362316,14sleep80-21swapper/819:07:4114
18000882357313,14sleep50-21swapper/519:08:4211
18000022356312,15sleep20-21swapper/219:07:358
18001012353310,14sleep10-21swapper/119:08:541
17998802353307,15sleep00-21swapper/019:05:560
18000872349308,14sleep40-21swapper/419:08:4110
17999652349306,14sleep70-21swapper/719:07:0813
17999532348323,16sleep120-21swapper/1219:06:574
18001592346335,7sleep60-21swapper/619:09:3212
17998892344321,15sleep90-21swapper/919:06:0515
18000702343321,14sleep100-21swapper/1019:08:312
17999982343320,15sleep150-21swapper/1519:07:327
17999542343318,16sleep130-21swapper/1319:06:585
17999002342319,15sleep30-21swapper/319:06:159
17979312340332,5sleep110-21swapper/1119:05:193
17998942339316,15sleep140-21swapper/1419:06:106
180058799162162,0cyclictest0-21swapper/1321:15:195
180056199139138,1cyclictest1911258-21nodev-device-ev21:15:1911
18005939910099,1cyclictest1877034-21nodev-device-ev20:35:187
1800553999594,1cyclictest2065138-21nodev-device-ev00:15:189
180054699930,93cyclictest0-21swapper/221:20:188
1800567999291,1cyclictest0-21swapper/722:30:1613
1800570999190,1cyclictest0-21swapper/822:20:1714
1800543999190,1cyclictest0-21swapper/121:05:181
1800564998887,1cyclictest1919808-21nodev-device-ev21:25:1812
1800540998584,1cyclictest0-21swapper/019:40:190
1800593997776,1cyclictest0-21swapper/1519:55:177
1800593997674,1cyclictest0-21swapper/1523:10:177
1800589996564,1cyclictest0-21swapper/1400:30:206
1800583996563,1cyclictest1924069-21nodev-device-ev21:30:194
1800557996564,1cyclictest0-21swapper/421:30:1910
1800553996261,1cyclictest2013844-21nodev-device-ev23:15:199
1800570996160,1cyclictest1838388-21nodev-device-ev19:50:1914
1800593995756,1cyclictest0-21swapper/1523:05:177
1800546995554,1cyclictest0-21swapper/223:35:208
1800553994847,1cyclictest0-21swapper/320:10:189
1800553994140,1cyclictest1817025-21nodev-device-ev19:25:189
1800546994140,1cyclictest2069421-21nodev-device-ev00:20:208
1800579993939,0cyclictest0-21swapper/1100:17:493
1800567993837,1cyclictest0-21swapper/719:30:1913
1800587993433,1cyclictest0-21swapper/1319:15:005
1800546993430,2cyclictest1197-21dbus-daemon21:40:208
1800579993330,3cyclictest0-21swapper/1119:10:383
1800564993332,1cyclictest2077975-21nodev-device-ev00:30:1912
1800546993331,2cyclictest1912612-21kworker/2:2-mm_percpu_wq00:38:498
1800540993332,1cyclictest0-21swapper/021:40:190
1800540993320,13cyclictest0-21swapper/023:50:160
1800546993229,0cyclictest0-21swapper/222:55:198
1800546993221,2cyclictest201rcu_preempt21:35:208
180054699320,29cyclictest0-21swapper/220:05:188
1800579993131,0cyclictest0-21swapper/1100:00:033
1800546993128,3cyclictest1986040-21kworker/u32:4-events_unbound22:45:268
1800546993127,2cyclictest1916739-21kworker/u32:1+flush-259:021:25:248
1800546993126,3cyclictest1881641-21ntpq20:40:228
1800579993026,2cyclictest123-21ksoftirqd/1121:15:173
180057999300,26cyclictest0-21swapper/1123:01:033
1800546993028,2cyclictest0-21swapper/223:10:008
1800546993028,2cyclictest0-21swapper/200:25:218
1800546993028,0cyclictest0-21swapper/223:15:238
1800546993026,2cyclictest0-21swapper/222:35:168
180059399290,28cyclictest0-21swapper/1521:40:177
180058799291,27cyclictest1907011-21kworker/13:2-mm_percpu_wq22:40:185
1800579992923,3cyclictest0-21swapper/1121:50:143
1800546992927,2cyclictest0-21swapper/221:08:368
1800546992927,2cyclictest0-21swapper/220:50:188
1800546992927,2cyclictest0-21swapper/220:15:008
1800546992926,3cyclictest0-21swapper/220:20:278
1800546992925,2cyclictest0-21swapper/220:15:268
1800546992924,5cyclictest1967322-21sendmail_mailqu22:20:228
1800546992923,3cyclictest2056141-21expr00:05:158
1800593992827,1cyclictest2045-21snmpd21:48:177
1800593992827,1cyclictest0-21swapper/1522:07:427
1800593992827,1cyclictest0-21swapper/1522:07:427
1800593992827,1cyclictest0-21swapper/1522:01:547
180059399280,27cyclictest0-21swapper/1519:27:497
180059399280,27cyclictest0-21swapper/1500:16:377
180058999280,27cyclictest0-21swapper/1421:58:056
1800587992827,1cyclictest2045-21snmpd19:40:405
1800587992827,1cyclictest2045-21snmpd00:06:035
180058799280,28cyclictest0-21swapper/1323:34:565
180058799280,27cyclictest0-21swapper/1322:33:575
180058799280,1cyclictest0-21swapper/1319:26:405
1800579992828,0cyclictest0-21swapper/1121:32:363
1800579992828,0cyclictest0-21swapper/1120:17:443
1800579992827,1cyclictest2045-21snmpd00:10:333
1800579992827,1cyclictest2045-21snmpd00:06:003
1800579992827,1cyclictest0-21swapper/1120:47:483
180057999281,27cyclictest1221ktimers/1119:20:343
180057999281,26cyclictest1221ktimers/1121:29:443
180057999280,27cyclictest0-21swapper/1122:13:413
180057999280,27cyclictest0-21swapper/1122:13:413
1800577992823,2cyclictest0-21swapper/1020:25:162
1800574992827,1cyclictest2045-21snmpd23:16:1715
1800574992827,1cyclictest0-21swapper/919:29:2515
1800570992827,1cyclictest2045-21snmpd20:12:3814
1800570992827,1cyclictest0-21swapper/823:55:1614
1800567992827,1cyclictest2045-21snmpd22:10:1213
1800567992827,1cyclictest2045-21snmpd22:10:1113
180056799280,27cyclictest0-21swapper/722:25:1713
180056799280,27cyclictest0-21swapper/721:48:3813
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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