You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-05-03 - 01:46
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot4.osadl.org (updated Sat May 03, 2025 00:46:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14312852417395,14sleep50-21swapper/519:06:3611
14315232394372,14sleep20-21swapper/219:09:478
14313982361316,14sleep80-21swapper/819:08:0014
14279512361353,5sleep140-21swapper/1419:05:096
14314472360318,15sleep30-21swapper/319:08:439
14279472355311,15sleep100-21swapper/1019:05:052
14313822349340,6sleep150-21swapper/1519:07:517
14314532348308,13sleep90-21swapper/919:08:4915
14313412347324,15sleep130-21swapper/1319:07:175
14314882345323,14sleep40-21swapper/419:09:1610
14314902344321,15sleep60-21swapper/619:09:1812
14312122344321,15sleep120-21swapper/1219:05:544
14312602342319,15sleep70-21swapper/719:06:2213
14315342339318,13sleep110-21swapper/1119:09:563
14312242336314,14sleep00-21swapper/019:05:590
14312002336314,14sleep10-21swapper/119:05:441
143194699328327,1cyclictest0-21swapper/1223:00:194
143195699276275,1cyclictest0-21swapper/1523:55:197
143195699276275,1cyclictest0-21swapper/1523:55:197
143191499248247,1cyclictest1572485-21nodev-device-ev21:50:218
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional