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2025-10-20 - 15:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot4.osadl.org (updated Mon Oct 20, 2025 00:46:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25475822387365,14sleep50-21swapper/519:05:5511
25477222363319,14sleep20-21swapper/219:07:468
25476212361312,15sleep80-21swapper/819:06:3014
25477682360315,15sleep140-21swapper/1419:08:296
25478972359312,15sleep150-21swapper/1519:09:527
25478562356338,7sleep100-21swapper/1019:09:312
25477772356313,15sleep00-21swapper/019:08:310
25476322356314,14sleep110-21swapper/1119:06:343
25477332355313,14sleep130-21swapper/1319:07:565
25477262354311,34sleep60-21swapper/619:07:5012
25476952354311,34sleep10-21swapper/119:07:281
25477122347337,7sleep120-21swapper/1219:07:394
25477072345321,15sleep70-21swapper/719:07:3513
25477242341318,14sleep40-21swapper/419:07:4710
25476032340317,15sleep90-21swapper/919:06:1515
25443112340315,17sleep30-21swapper/319:05:059
254830299318318,0cyclictest0-21swapper/520:20:1811
254830299318318,0cyclictest0-21swapper/520:20:1811
254828999307306,1cyclictest311rcuc/122:50:181
254831799230229,1cyclictest2740074-21nodev-device-ev22:50:1715
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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