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2025-09-16 - 20:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot4.osadl.org (updated Tue Sep 16, 2025 00:46:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15498132361314,15sleep50-21swapper/519:05:4411
15500662357312,35sleep150-21swapper/1519:09:077
15498432353310,14sleep110-21swapper/1119:06:053
15498412351310,15sleep90-21swapper/919:06:0415
15499002350341,6sleep70-21swapper/719:06:5013
15500702349339,6sleep10-21swapper/119:09:091
15501142346324,14sleep80-21swapper/819:09:4814
15498142346323,15sleep60-21swapper/619:05:4512
15500472343320,15sleep130-21swapper/1319:08:495
15499682343332,7sleep00-21swapper/019:07:480
15499322343320,15sleep40-21swapper/419:07:1910
15501092339315,15sleep30-21swapper/319:09:439
15499612339316,15sleep100-21swapper/1019:07:422
15498632337315,14sleep120-21swapper/1219:06:234
15498842336313,15sleep140-21swapper/1419:06:416
15498102336313,15sleep20-21swapper/219:05:408
155053699216216,0cyclictest0-21swapper/300:20:189
155053699213213,0cyclictest0-21swapper/323:05:209
155052799195194,1cyclictest1614026-21nodev-device-ev20:20:170
155055399191190,1cyclictest0-21swapper/820:20:1714
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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