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2025-06-28 - 23:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot4.osadl.org (updated Sat Jun 28, 2025 00:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39972772377352,17sleep150-21swapper/1519:09:357
39969932353308,14sleep140-21swapper/1419:05:496
39971752350342,5sleep90-21swapper/919:08:0915
39971312348324,15sleep70-21swapper/719:07:3413
39972102345321,15sleep80-21swapper/819:08:4014
39970902345322,15sleep30-21swapper/319:06:589
39969882344321,15sleep110-21swapper/1119:05:463
39971682343321,14sleep20-21swapper/219:08:028
39970972343301,14sleep100-21swapper/1019:07:052
39970422343321,14sleep10-21swapper/119:06:241
39971972342319,15sleep130-21swapper/1319:08:295
39969732340317,15sleep60-21swapper/619:05:4112
39971792339316,14sleep120-21swapper/1219:08:124
39970682339316,15sleep40-21swapper/419:06:4310
39970692338315,15sleep50-21swapper/519:06:4411
39972792337315,14sleep00-21swapper/019:09:360
399774299211211,0cyclictest0-21swapper/620:25:2112
399776999172171,1cyclictest4065438-21nodev-device-ev20:25:216
39977229910199,1cyclictest4108176-21nodev-device-ev21:15:180
3997729999594,1cyclictest4099622-21nodev-device-ev21:05:208
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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