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2026-07-06 - 20:39

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot4s.osadl.org (updated Mon Jul 06, 2026 00:46:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4941002367323,14sleep70-21swapper/719:05:5713
4942682365356,6sleep20-21swapper/219:08:178
4941982363342,14sleep90-21swapper/919:07:2015
4941062358319,14sleep130-21swapper/1319:06:035
4941152354333,14sleep50-21swapper/519:06:1111
4940812353332,13sleep100-21swapper/1019:05:442
4943782352332,13sleep60-21swapper/619:09:2512
4940712352332,13sleep10-21swapper/119:05:351
4942062351331,13sleep140-21swapper/1419:07:256
4941282351331,13sleep150-21swapper/1519:06:217
4941302350330,13sleep00-21swapper/019:06:220
4941652349329,13sleep120-21swapper/1219:06:504
4942402348328,13sleep80-21swapper/819:07:5114
4940822348329,12sleep110-21swapper/1119:05:463
4944302347327,13sleep30-21swapper/319:09:559
4941742346324,14sleep40-21swapper/419:07:0010
494844996260,2cyclictest624486-21kworker/u32:4+events_unbound00:27:188
494862996158,2cyclictest755810-21kworker/u32:0+flush-259:023:30:4014
494862996158,2cyclictest755810-21kworker/u32:0+flush-259:023:30:3914
494844995750,7cyclictest0-21swapper/220:10:138
494844995352,1cyclictest731459-21ssh22:54:558
494860995250,2cyclictest549953-21kworker/u32:0+events_unbound21:22:5913
494844995147,0cyclictest0-21swapper/223:40:238
494844995147,0cyclictest0-21swapper/223:40:238
494844995047,3cyclictest0-21swapper/222:00:218
494844995014,30cyclictest0-21swapper/219:10:018
494844994945,0cyclictest0-21swapper/223:32:468
494844994945,0cyclictest0-21swapper/223:32:458
494844994941,6cyclictest211rcu_preempt21:23:018
494844994928,17cyclictest615992-21kworker/2:2-events21:35:178
494844994848,0cyclictest0-21swapper/223:10:218
494844994844,4cyclictest0-21swapper/223:07:288
494844994844,4cyclictest0-21swapper/221:17:018
494844994842,6cyclictest0-21swapper/200:37:448
494844994842,2cyclictest624486-21kworker/u32:4-nfsiod21:43:218
494844994743,4cyclictest43-21ksoftirqd/223:21:098
494844994743,4cyclictest0-21swapper/222:47:358
494844994743,4cyclictest0-21swapper/222:25:108
494844994743,4cyclictest0-21swapper/222:22:238
494844994740,7cyclictest624486-21kworker/u32:4+events_unbound23:52:578
494844994739,4cyclictest0-21swapper/222:10:538
494844994734,4cyclictest211rcu_preempt00:00:298
494844994726,19cyclictest0-21swapper/200:07:018
49484499470,43cyclictest615992-21kworker/2:2+mm_percpu_wq22:15:178
494844994643,0cyclictest731018-21kworker/2:0-events23:47:528
494844994642,4cyclictest0-21swapper/221:26:138
494844994638,4cyclictest731018-21kworker/2:0-events23:15:018
494844994637,2cyclictest211rcu_preempt22:44:488
494844994625,17cyclictest0-21swapper/222:34:098
49484499460,42cyclictest684701-21kworker/2:0+events22:39:098
494844994541,4cyclictest0-21swapper/223:37:518
494844994541,4cyclictest0-21swapper/223:37:518
494844994541,4cyclictest0-21swapper/221:52:248
494844994541,0cyclictest0-21swapper/221:58:238
494844994539,6cyclictest0-21swapper/200:10:078
494844994532,4cyclictest211rcu_preempt22:09:468
494844994524,17cyclictest833159-21kworker/2:2+mm_percpu_wq00:24:158
494844994524,17cyclictest731018-21kworker/2:0-events23:02:138
494844994524,17cyclictest0-21swapper/221:34:488
494844994524,17cyclictest0-21swapper/200:31:098
49484499450,41cyclictest0-21swapper/223:56:098
494871994444,0cyclictest0-21swapper/1123:47:513
494871994444,0cyclictest0-21swapper/1100:13:523
494844994440,4cyclictest540074-21kworker/u32:2-events_unbound20:15:128
494844994440,0cyclictest0-21swapper/220:23:358
494844994439,5cyclictest485920-21kworker/u32:3+flush-259:019:15:278
494844994428,12cyclictest0-21swapper/200:15:188
494875994336,4cyclictest557060-21kworker/u32:4+events_unbound20:26:404
494875994336,4cyclictest557060-21kworker/u32:4+events_unbound20:26:394
494844994342,1cyclictest0-21swapper/222:55:198
494844994341,0cyclictest0-21swapper/220:55:138
494844994339,0cyclictest0-21swapper/223:29:068
494844994336,3cyclictest0-21swapper/221:06:318
494844994318,16cyclictest211rcu_preempt21:14:238
494844994234,4cyclictest0-21swapper/220:43:358
494844994234,4cyclictest0-21swapper/219:50:178
494844994221,17cyclictest411rcuc/221:45:538
494876994138,3cyclictest703384-21kworker/u32:3+events_unbound22:34:405
494851994141,0cyclictest0-21swapper/421:27:1810
494844994137,4cyclictest0-21swapper/220:52:458
494844994137,4cyclictest0-21swapper/220:07:098
494844994137,0cyclictest0-21swapper/219:45:178
494844994133,4cyclictest0-21swapper/219:31:178
494871994039,1cyclictest702361-21processes22:30:213
494851994040,0cyclictest0-21swapper/423:08:5310
494851994040,0cyclictest0-21swapper/421:08:3210
494844994032,4cyclictest0-21swapper/220:35:148
494844994032,4cyclictest0-21swapper/219:59:538
494844994019,17cyclictest0-21swapper/221:00:238
494871993939,0cyclictest0-21swapper/1122:50:083
494844993935,4cyclictest0-21swapper/219:20:158
494844993923,12cyclictest0-21swapper/219:43:368
494844993919,16cyclictest549953-21kworker/u32:0-writeback20:25:218
494844993919,16cyclictest549953-21kworker/u32:0-writeback20:25:218
494875993836,2cyclictest549953-21kworker/u32:0+flush-259:021:02:104
494871993838,0cyclictest0-21swapper/1123:53:183
494856993835,2cyclictest624486-21kworker/u32:4+flush-259:022:18:5812
494851993838,0cyclictest0-21swapper/423:51:5810
494851993838,0cyclictest0-21swapper/422:39:3610
494851993838,0cyclictest0-21swapper/422:13:5110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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