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2026-01-10 - 16:57

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot4s.osadl.org (updated Sat Jan 10, 2026 00:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9770122408387,13sleep130-21swapper/1319:06:165
9770042385379,4sleep50-21swapper/519:06:0811
9770432371351,13sleep40-21swapper/419:06:3910
9769752369362,4sleep120-21swapper/1219:05:434
9770462359342,10sleep70-21swapper/719:06:4313
9738272353334,12sleep30-21swapper/319:05:039
9770102351332,12sleep110-21swapper/1119:06:153
9772452349337,8sleep80-21swapper/819:09:0914
9772422347325,14sleep60-21swapper/619:09:0612
9749482347336,7sleep140-21swapper/1419:05:136
9769992346327,12sleep00-21swapper/019:06:030
9772992345325,13sleep10-21swapper/119:09:511
9770182345324,14sleep20-21swapper/219:06:228
9770092345325,13sleep100-21swapper/1019:06:142
9769722344323,13sleep90-21swapper/919:05:4115
9769592343322,13sleep150-21swapper/1519:05:317
977720995151,0cyclictest0-21swapper/1221:16:384
977720995050,0cyclictest0-21swapper/1220:42:134
977705994745,2cyclictest0-21swapper/722:45:3213
977720994646,0cyclictest0-21swapper/1219:31:394
977705994646,0cyclictest0-21swapper/720:25:4313
977705994544,1cyclictest1210967-21ntpq22:50:2013
977705994444,0cyclictest0-21swapper/721:52:3013
977705994444,0cyclictest0-21swapper/721:52:2913
977720994343,0cyclictest0-21swapper/1223:47:324
977720994343,0cyclictest0-21swapper/1223:08:524
977720994343,0cyclictest0-21swapper/1222:05:424
977720994343,0cyclictest0-21swapper/1221:45:484
977720994343,0cyclictest0-21swapper/1221:45:484
977720994343,0cyclictest0-21swapper/1220:36:064
977720994342,0cyclictest211rcu_preempt22:57:104
977705994343,0cyclictest0-21swapper/722:26:5213
977705994342,1cyclictest1226098-21ssh23:02:4813
977705994342,1cyclictest1103286-21ssh21:27:5813
977705994337,6cyclictest0-21swapper/722:30:5213
977705994337,6cyclictest0-21swapper/722:20:0813
977705994241,1cyclictest1926-21arpwatch23:35:1713
977705994240,0cyclictest211rcu_preempt00:24:3813
977705994236,6cyclictest0-21swapper/721:35:3213
977720994141,0cyclictest0-21swapper/1222:10:514
977705994141,0cyclictest0-21swapper/722:18:0513
977705994141,0cyclictest0-21swapper/700:28:5413
977705994140,1cyclictest1926-21arpwatch23:13:5713
977705994137,4cyclictest1246727-21kworker/7:1+mm_percpu_wq23:44:2413
977705994137,4cyclictest0-21swapper/722:55:2413
977705994137,4cyclictest0-21swapper/721:18:3813
977705994137,4cyclictest0-21swapper/721:10:5313
977705994137,4cyclictest0-21swapper/720:30:1613
977705994137,4cyclictest0-21swapper/700:34:1413
977705994137,4cyclictest0-21swapper/700:03:4213
977705994135,6cyclictest0-21swapper/723:31:2213
977705994133,6cyclictest0-21swapper/700:05:2013
977705994133,4cyclictest1317105-21ssh00:13:4113
977705994113,24cyclictest0-21swapper/723:08:3713
977705994113,24cyclictest0-21swapper/722:14:2113
977720994040,0cyclictest0-21swapper/1223:22:024
977705994040,0cyclictest0-21swapper/721:57:5013
977705994040,0cyclictest0-21swapper/721:57:4913
977705994040,0cyclictest0-21swapper/719:30:2213
977705994040,0cyclictest0-21swapper/700:36:2713
977705994039,1cyclictest1246727-21kworker/7:1+mm_percpu_wq23:47:0813
977705994036,4cyclictest0-21swapper/722:44:0713
977705994036,4cyclictest0-21swapper/721:22:2413
977705994036,4cyclictest0-21swapper/700:18:2213
977705994034,6cyclictest0-21swapper/723:51:5013
977705994034,6cyclictest0-21swapper/722:38:4513
977705994032,6cyclictest861rcuc/721:40:1913
977705994032,4cyclictest0-21swapper/722:06:5013
977705994017,23cyclictest0-21swapper/723:56:2913
977705994016,24cyclictest0-21swapper/723:28:1213
977720993939,0cyclictest0-21swapper/1222:16:054
977720993939,0cyclictest0-21swapper/1220:56:324
977705993939,0cyclictest0-21swapper/723:15:1613
977705993935,4cyclictest0-21swapper/721:48:2413
977705993935,4cyclictest0-21swapper/721:48:2413
977705993935,4cyclictest0-21swapper/721:31:2613
977705993933,6cyclictest0-21swapper/719:42:3413
977705993931,4cyclictest0-21swapper/723:21:0613
977705993931,4cyclictest0-21swapper/722:03:2213
977705993929,10cyclictest1060337-21kworker/u32:1+events_unbound20:50:5513
977720993838,0cyclictest0-21swapper/1222:04:124
977720993838,0cyclictest0-21swapper/1221:42:234
977720993838,0cyclictest0-21swapper/1221:30:504
977720993838,0cyclictest0-21swapper/1220:48:534
977705993832,6cyclictest0-21swapper/720:15:1213
977705993832,4cyclictest0-21swapper/720:36:0613
977705993830,4cyclictest0-21swapper/720:03:1713
977720993737,0cyclictest0-21swapper/1220:22:304
977720993737,0cyclictest0-21swapper/1220:04:314
97770599378,24cyclictest0-21swapper/719:25:1313
977705993731,0cyclictest0-21swapper/719:20:1613
977705993729,4cyclictest0-21swapper/720:57:4013
977705993729,4cyclictest0-21swapper/720:46:3113
977705993710,24cyclictest993645-21kworker/7:2-events21:00:2013
977720993636,0cyclictest1007469-21kworker/u32:4-writeback20:25:434
977720993636,0cyclictest0-21swapper/1220:31:204
977720993636,0cyclictest0-21swapper/1219:21:454
977705993633,3cyclictest0-21swapper/721:05:3613
977705993633,0cyclictest0-21swapper/720:40:2113
977705993632,0cyclictest0-21swapper/719:19:5513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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