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2026-07-13 - 04:21

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot4s.osadl.org (updated Mon Jul 13, 2026 00:46:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9845932383348,27sleep30-21swapper/319:05:589
9848772382363,12sleep70-21swapper/719:09:4613
9846582361326,28sleep60-21swapper/619:06:4812
9847762360341,12sleep50-21swapper/519:08:2411
9847482358320,14sleep00-21swapper/019:08:030
9846282357316,14sleep130-21swapper/1319:06:235
9846712354334,13sleep20-21swapper/219:07:018
9847632353333,13sleep150-21swapper/1519:08:187
9846772353333,13sleep80-21swapper/819:07:0714
9846562353333,13sleep40-21swapper/419:06:4710
9846792352340,8sleep100-21swapper/1019:07:092
9814262351332,12sleep140-21swapper/1419:05:046
9848822349330,13sleep120-21swapper/1219:09:514
9846702348329,13sleep10-21swapper/119:07:001
9845612345325,13sleep110-21swapper/1119:05:343
9847402344323,14sleep90-21swapper/919:07:5715
985337995352,1cyclictest1110510-21kworker/u32:1+flush-259:021:40:524
985342995227,0cyclictest1142031-21ssh21:51:146
985300994947,1cyclictest1110510-21kworker/u32:1+events_unbound21:41:340
985333994847,0cyclictest0-21swapper/1122:50:143
985345994544,0cyclictest0-21swapper/1522:50:157
985306994413,2cyclictest1323794-21kworker/u32:0+flush-259:000:21:148
985312994238,3cyclictest1168038-21kworker/u32:3+flush-259:022:15:2610
985342994139,2cyclictest1168038-21kworker/u32:3+flush-259:022:51:166
985327994038,2cyclictest1086100-21kworker/u32:3+flush-259:021:29:5815
985327993937,1cyclictest1035911-21kworker/u32:5+events_unbound20:45:1615
985345993833,4cyclictest0-21swapper/1520:25:207
985342993814,11cyclictest0-21swapper/1419:50:246
985333993837,1cyclictest0-21swapper/1121:40:153
985345993736,0cyclictest0-21swapper/1523:24:527
98534299371,11cyclictest0-21swapper/1421:40:146
985345993533,1cyclictest0-21swapper/1522:10:177
985345993532,0cyclictest211rcu_preempt23:49:437
985339993534,0cyclictest0-21swapper/1323:05:295
985306993513,1cyclictest1302675-21kworker/u32:1+flush-259:000:06:398
985333993433,1cyclictest976204-21kworker/u32:0+flush-259:019:10:283
985345993333,0cyclictest0-21swapper/1522:17:447
985345993332,0cyclictest0-21swapper/1520:30:207
985339993333,0cyclictest0-21swapper/1323:10:275
985339993333,0cyclictest0-21swapper/1322:54:125
985339993333,0cyclictest0-21swapper/1321:25:125
985333993333,0cyclictest0-21swapper/1122:26:163
98532799330,30cyclictest1104363-21ssh21:22:4115
985321993333,0cyclictest0-21swapper/720:30:2013
98530499330,30cyclictest0-21swapper/121:35:161
985300993332,1cyclictest1303142-21kworker/u32:3+events_unbound00:07:300
985345993232,0cyclictest0-21swapper/1500:05:217
985339993232,0cyclictest0-21swapper/1321:15:025
98533999320,1cyclictest0-21swapper/1300:20:155
985333993231,1cyclictest0-21swapper/1122:55:173
98532799320,30cyclictest0-21swapper/921:59:1715
98531699320,31cyclictest0-21swapper/520:55:1711
985306993230,2cyclictest1303142-21kworker/u32:3+flush-259:000:26:168
985345993131,0cyclictest0-21swapper/1522:00:197
985345993130,1cyclictest1347443-21kworker/u32:0+events_unbound00:35:157
98534299318,10cyclictest0-21swapper/1420:01:236
98534299317,11cyclictest0-21swapper/1423:08:076
98534299317,11cyclictest0-21swapper/1421:29:166
98534299317,11cyclictest0-21swapper/1400:14:016
985333993131,0cyclictest0-21swapper/1123:49:173
985333993131,0cyclictest0-21swapper/1121:15:013
985333993130,1cyclictest1774-21snmpd22:31:003
985333993130,1cyclictest1774-21snmpd00:00:243
985333993130,1cyclictest1206504-21kworker/u32:0+events_unbound23:15:233
985333993129,2cyclictest1206504-21kworker/u32:0+events_unbound23:12:453
98533199311,30cyclictest0-21swapper/1019:13:222
985327993128,3cyclictest1774-21snmpd21:09:0115
985327993123,8cyclictest1774-21snmpd23:37:5915
985324993130,1cyclictest1108338-21nodev-device-ev21:25:1714
98532499310,30cyclictest0-21swapper/822:26:0114
985321993129,2cyclictest0-21swapper/720:25:2013
98531899310,30cyclictest0-21swapper/621:06:3212
98531899310,30cyclictest0-21swapper/619:40:1612
98531899310,30cyclictest0-21swapper/619:35:1512
98531899310,30cyclictest0-21swapper/619:35:1412
98531899310,30cyclictest0-21swapper/619:30:1512
98531899310,30cyclictest0-21swapper/619:30:1412
985306993130,1cyclictest1774-21snmpd23:33:218
985306993130,1cyclictest1774-21snmpd23:04:478
98530699310,30cyclictest0-21swapper/223:07:048
985304993130,1cyclictest1774-21snmpd00:06:371
985345993030,0cyclictest0-21swapper/1522:41:177
985345993030,0cyclictest0-21swapper/1522:41:177
985345993030,0cyclictest0-21swapper/1521:45:187
985345993030,0cyclictest0-21swapper/1521:15:047
985345993029,1cyclictest160-21ksoftirqd/1522:26:167
985345993028,1cyclictest1189764-21kworker/15:0+mm_percpu_wq00:22:167
98534299306,11cyclictest0-21swapper/1420:45:196
985342993029,1cyclictest1774-21snmpd19:57:216
985342993029,1cyclictest1774-21snmpd00:04:156
98534299300,1cyclictest0-21swapper/1421:07:206
985339993030,0cyclictest0-21swapper/1323:50:305
985339993030,0cyclictest0-21swapper/1323:49:435
985339993030,0cyclictest0-21swapper/1323:42:415
985339993030,0cyclictest0-21swapper/1323:23:115
985339993030,0cyclictest0-21swapper/1322:17:455
985339993030,0cyclictest0-21swapper/1321:43:005
985339993030,0cyclictest0-21swapper/1300:09:355
985339993029,1cyclictest1086100-21kworker/u32:3+events_unbound21:22:415
985339993029,1cyclictest0-21swapper/1322:14:365
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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