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2026-02-19 - 16:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Thu Feb 19, 2026 00:46:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4813402370349,14sleep80-21swapper/819:08:3114
4814542366358,5sleep140-21swapper/1419:09:576
4811222361355,4sleep50-21swapper/519:05:4711
4779642359343,10sleep120-21swapper/1219:05:064
4812692358338,13sleep20-21swapper/219:07:378
4813742357340,11sleep40-21swapper/419:08:5910
4811042357335,15sleep60-21swapper/619:05:3212
4813422352332,13sleep100-21swapper/1019:08:342
4811742352332,13sleep150-21swapper/1519:06:297
4811402350330,13sleep30-21swapper/319:06:019
4814472349330,12sleep90-21swapper/919:09:5315
4812402349330,12sleep10-21swapper/119:07:191
4813332342322,13sleep70-21swapper/719:08:3013
4811942342324,11sleep110-21swapper/1119:06:413
4811722342322,13sleep130-21swapper/1319:06:275
4811372339319,13sleep00-21swapper/019:05:580
481892993734,2cyclictest475700-21kworker/u32:0+events_unbound19:15:000
48189899354,29cyclictest601879-21kworker/u32:0+events_unbound22:24:468
481900993229,3cyclictest569007-21ethtool20:50:149
481900993226,6cyclictest1774-21snmpd23:19:539
48190099320,31cyclictest0-21swapper/323:05:419
48190099320,31cyclictest0-21swapper/323:05:419
481898993229,1cyclictest782-21systemd-journal20:56:478
48189899320,29cyclictest0-21swapper/223:49:198
48189899320,29cyclictest0-21swapper/222:54:278
48189899320,29cyclictest0-21swapper/222:45:098
48189899320,29cyclictest0-21swapper/222:08:038
48189899320,29cyclictest0-21swapper/221:58:138
48189899320,29cyclictest0-21swapper/221:23:378
48189899320,29cyclictest0-21swapper/221:00:368
48189899320,29cyclictest0-21swapper/220:46:478
48189899320,29cyclictest0-21swapper/220:33:118
48189899320,29cyclictest0-21swapper/200:19:348
48189899320,29cyclictest0-21swapper/200:07:358
48194099310,30cyclictest0-21swapper/1523:42:257
48193899312,24cyclictest0-21swapper/1423:08:276
48193899312,24cyclictest0-21swapper/1423:08:276
48193899310,30cyclictest0-21swapper/1422:58:026
48193899310,30cyclictest0-21swapper/1419:15:146
48193899310,30cyclictest0-21swapper/1400:15:466
48193499310,30cyclictest0-21swapper/1322:10:145
48193499310,30cyclictest0-21swapper/1321:30:155
481929993130,1cyclictest1774-21snmpd21:40:004
48192499310,30cyclictest0-21swapper/1100:10:003
48192399310,30cyclictest0-21swapper/1023:05:442
48192399310,30cyclictest0-21swapper/1023:05:442
48191999310,30cyclictest0-21swapper/923:15:4115
48191999310,30cyclictest0-21swapper/922:04:3315
48191999310,30cyclictest0-21swapper/920:40:1515
48191999310,30cyclictest0-21swapper/900:29:0815
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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