You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-15 - 08:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Sun Feb 15, 2026 00:46:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2756812367361,4sleep70-21swapper/719:09:3113
2756192364357,5sleep100-21swapper/1019:08:462
2755932362354,5sleep10-21swapper/119:08:211
2753912362346,9sleep110-21swapper/1119:05:503
2754522359339,13sleep90-21swapper/919:06:3615
2754462359320,13sleep30-21swapper/319:06:309
2754782357337,13sleep130-21swapper/1319:06:565
2756352351332,12sleep50-21swapper/519:08:5711
2755692351331,14sleep20-21swapper/219:08:068
2756902347327,13sleep150-21swapper/1519:09:407
2754342347327,13sleep80-21swapper/819:06:2014
2756522346325,13sleep40-21swapper/419:09:1210
2756432344324,13sleep120-21swapper/1219:09:044
2754182344325,12sleep00-21swapper/019:06:120
2756372343323,13sleep60-21swapper/619:08:5812
2755892342322,13sleep140-21swapper/1419:08:186
276231994444,0cyclictest0-21swapper/1121:10:153
27624199426,11cyclictest0-21swapper/1421:45:206
276221994242,0cyclictest0-21swapper/819:10:1414
276221994040,0cyclictest196791-21kworker/8:2-events20:39:2814
27624199393,11cyclictest0-21swapper/1419:55:296
27624199382,11cyclictest0-21swapper/1421:34:216
276241993636,0cyclictest0-21swapper/1419:10:146
276221993636,0cyclictest0-21swapper/823:07:0614
276241993410,10cyclictest0-21swapper/1420:50:246
276228993432,2cyclictest409099-21kworker/u32:2+events_unbound21:40:192
276207993434,0cyclictest0-21swapper/319:10:149
276205993430,3cyclictest560811-21kworker/u32:2+flush-259:023:37:578
276241993320,13cyclictest0-21swapper/1419:22:326
276237993333,0cyclictest219595-21kworker/13:0+mm_percpu_wq19:10:145
276237993333,0cyclictest0-21swapper/1323:14:585
276221993333,0cyclictest0-21swapper/819:38:4014
27622199332,31cyclictest961ktimers/821:35:1414
276207993333,0cyclictest0-21swapper/322:53:229
276207993332,1cyclictest0-21swapper/300:37:479
276205993329,3cyclictest574224-21kworker/u32:1+events_unbound00:10:198
27620599330,30cyclictest1769-21arpwatch21:56:588
27624199328,11cyclictest0-21swapper/1421:01:236
276241993231,1cyclictest0-21swapper/1400:37:466
276237993232,0cyclictest0-21swapper/1323:41:205
276237993226,3cyclictest1769-21arpwatch00:04:165
276205993229,1cyclictest559501-21memory23:30:188
276205993228,4cyclictest782-21systemd-journal21:19:168
27620599320,29cyclictest0-21swapper/223:21:588
27620599320,29cyclictest0-21swapper/222:55:468
27620599320,29cyclictest0-21swapper/222:26:288
27620599320,29cyclictest0-21swapper/221:53:328
27620599320,29cyclictest0-21swapper/221:46:368
27620599320,29cyclictest0-21swapper/200:01:568
27624299310,30cyclictest0-21swapper/1500:23:317
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional