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2026-01-25 - 06:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Sun Jan 25, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13969952375368,5sleep40-21swapper/419:08:0910
13967742371364,5sleep30-21swapper/319:05:279
13969972370346,6sleep60-21swapper/619:08:1212
13970462351331,13sleep130-21swapper/1319:08:515
13969482350330,13sleep100-21swapper/1019:07:262
13970142349329,13sleep00-21swapper/019:08:210
13969652349326,14sleep90-21swapper/919:07:4115
13970272346326,13sleep110-21swapper/1119:08:323
13969442346326,13sleep80-21swapper/819:07:2414
13969042346326,13sleep120-21swapper/1219:06:574
13968062345324,14sleep20-21swapper/219:05:428
13971082344322,14sleep140-21swapper/1419:09:396
13969962344323,14sleep50-21swapper/519:08:1111
13968732343323,13sleep150-21swapper/1519:06:277
13969352342321,14sleep10-21swapper/119:07:171
13968632341320,14sleep70-21swapper/719:06:1913
1397614994910,25cyclictest0-21swapper/1419:47:236
139761499448,11cyclictest0-21swapper/1400:21:576
139761499437,11cyclictest0-21swapper/1423:27:036
139761499437,11cyclictest0-21swapper/1422:43:076
139761499437,11cyclictest0-21swapper/1422:32:076
139761499437,11cyclictest0-21swapper/1422:21:086
139761499427,11cyclictest0-21swapper/1400:10:586
139761499427,10cyclictest0-21swapper/1420:20:196
1397568994040,0cyclictest0-21swapper/022:50:470
139761499394,10cyclictest0-21swapper/1419:58:216
139756899386,32cyclictest0-21swapper/000:27:270
1397614993713,13cyclictest0-21swapper/1422:10:096
1397568993737,0cyclictest0-21swapper/019:12:410
1397607993535,0cyclictest0-21swapper/1219:10:254
1397568993535,0cyclictest0-21swapper/020:37:480
1397568993535,0cyclictest0-21swapper/020:37:470
1397580993426,8cyclictest1774-21snmpd21:34:3110
139761499327,25cyclictest0-21swapper/1420:31:186
139761499327,0cyclictest0-21swapper/1421:26:146
139759499320,30cyclictest0-21swapper/820:30:2514
139756899324,28cyclictest181ktimers/022:19:260
139761999310,30cyclictest0-21swapper/1520:54:547
139761999310,30cyclictest0-21swapper/1520:07:287
139761499317,24cyclictest0-21swapper/1421:59:106
139761499316,25cyclictest0-21swapper/1421:48:116
139761499316,25cyclictest0-21swapper/1420:42:186
139761499316,25cyclictest0-21swapper/1420:42:176
139761499316,0cyclictest0-21swapper/1419:36:246
1397612993129,1cyclictest1759228-21ethtool00:30:165
139760799310,30cyclictest0-21swapper/1221:22:434
139760199310,30cyclictest0-21swapper/1122:41:393
139760199310,30cyclictest0-21swapper/1100:21:003
139760199310,30cyclictest0-21swapper/1100:16:113
1397599993130,1cyclictest0-21swapper/1022:35:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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