You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-04 - 11:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Wed Mar 04, 2026 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11344482387329,12sleep150-21swapper/1519:05:567
11346862371365,4sleep100-21swapper/1019:09:052
11346342355334,14sleep20-21swapper/219:08:248
11346032353333,13sleep80-21swapper/819:07:5914
11347112352332,13sleep140-21swapper/1419:09:266
11347022352331,14sleep60-21swapper/619:09:1712
11346222352332,13sleep70-21swapper/719:08:1413
11344662352333,12sleep130-21swapper/1319:06:105
11344402352332,13sleep90-21swapper/919:05:5015
11346202351330,14sleep50-21swapper/519:08:1111
11345722351314,31sleep00-21swapper/019:07:350
11345552349329,13sleep30-21swapper/319:07:219
11346902347329,12sleep120-21swapper/1219:09:074
11346702347328,12sleep110-21swapper/1119:08:493
11345082347328,12sleep10-21swapper/119:06:471
11345172344322,14sleep40-21swapper/419:06:5010
113520999920,30cyclictest0-21swapper/020:22:020
1135215998929,30cyclictest0-21swapper/220:22:008
1135260998829,31cyclictest0-21swapper/1520:22:027
1135214998326,28cyclictest0-21swapper/120:22:001
1135250998022,28cyclictest0-21swapper/1220:22:024
1135234998021,28cyclictest0-21swapper/720:22:0113
113521799772,75cyclictest0-21swapper/320:22:009
113524099720,72cyclictest0-21swapper/920:22:0015
1135220996131,30cyclictest0-21swapper/420:22:0210
1135246995250,2cyclictest3318-21Xorg20:22:013
1135236994416,28cyclictest0-21swapper/820:22:0114
1135215994342,1cyclictest1473071-21kworker/u32:2+flush-259:000:27:218
1135244994240,2cyclictest3318-21Xorg20:22:012
1135223994139,2cyclictest0-21swapper/520:35:1411
1135215994037,3cyclictest1349006-21kworker/u32:3+events_unbound23:20:028
1135215993928,11cyclictest1769-21arpwatch23:18:378
1135260993834,4cyclictest0-21swapper/1500:32:427
113525599382,11cyclictest0-21swapper/1421:03:156
113525599382,11cyclictest0-21swapper/1419:24:256
1135215993830,8cyclictest0-21swapper/200:32:428
1135260993737,0cyclictest0-21swapper/1521:20:167
1135250993737,0cyclictest0-21swapper/1222:57:514
113521599370,2cyclictest1336580-21kworker/2:2-mm_percpu_wq22:33:078
1135255993636,0cyclictest0-21swapper/1422:00:386
113525599360,11cyclictest0-21swapper/1423:26:026
113525599360,11cyclictest0-21swapper/1421:47:116
113521599366,0cyclictest0-21swapper/223:00:218
113521599361,32cyclictest0-21swapper/220:45:208
113526099355,29cyclictest0-21swapper/1519:20:117
1135260993535,0cyclictest0-21swapper/1522:24:427
1135255993535,0cyclictest0-21swapper/1423:20:166
1135255993535,0cyclictest0-21swapper/1421:11:176
1135252993535,0cyclictest0-21swapper/1322:36:155
1135252993535,0cyclictest0-21swapper/1300:11:265
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional