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2026-03-13 - 19:16

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Fri Mar 13, 2026 00:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19256582398392,4sleep130-21swapper/1319:05:095
19256452370362,5sleep80-21swapper/819:05:0314
19290432364344,13sleep140-21swapper/1419:08:556
19287952353331,14sleep150-21swapper/1519:05:437
19288332352332,13sleep70-21swapper/719:06:0713
19288212352332,13sleep30-21swapper/319:06:039
19287832352332,13sleep40-21swapper/419:05:3310
19290172349328,14sleep60-21swapper/619:08:3112
19290222347327,13sleep110-21swapper/1119:08:363
19289842347327,13sleep120-21swapper/1219:08:064
19288652347327,13sleep20-21swapper/219:06:348
19290292346327,13sleep00-21swapper/019:08:410
19288312346326,13sleep50-21swapper/519:06:0611
19290392344323,14sleep100-21swapper/1019:08:512
19291192343323,13sleep90-21swapper/919:09:5415
19288192340321,13sleep10-21swapper/119:06:011
1929493994219,22cyclictest1984496-21kworker/u32:4+flush-259:021:30:188
1929523993938,1cyclictest2200187-21kworker/u32:2+events_unbound23:29:554
1929523993938,1cyclictest2200187-21kworker/u32:2+events_unbound23:29:544
1929493993527,7cyclictest1774-21snmpd22:35:528
1929532993434,0cyclictest0-21swapper/1523:09:297
1929523993434,0cyclictest0-21swapper/1223:44:134
1929523993333,0cyclictest0-21swapper/1222:14:054
1929523993332,0cyclictest0-21swapper/1200:39:024
192950299330,1cyclictest0-21swapper/521:58:1711
1929532993232,0cyclictest0-21swapper/1500:39:017
1929532993232,0cyclictest0-21swapper/1500:18:467
1929532993231,1cyclictest2239128-21ssh23:53:027
192949399320,1cyclictest0-21swapper/222:29:228
1929532993131,0cyclictest0-21swapper/1521:50:157
1929532993131,0cyclictest0-21swapper/1500:22:277
1929532993130,1cyclictest2071791-21kworker/u32:3+events_unbound22:25:187
192953099317,13cyclictest0-21swapper/1422:31:276
1929530993130,1cyclictest0-21swapper/1421:59:486
1929530993129,1cyclictest1774-21snmpd20:24:366
1929530993129,1cyclictest1774-21snmpd20:24:356
192952599310,30cyclictest0-21swapper/1322:45:165
192952599310,30cyclictest0-21swapper/1321:29:205
1929523993131,0cyclictest0-21swapper/1222:50:284
1929523993128,1cyclictest0-21swapper/1200:30:054
192952099310,30cyclictest0-21swapper/1122:10:093
192952099310,30cyclictest0-21swapper/1121:54:563
192952099310,30cyclictest0-21swapper/1119:50:023
1929516993130,1cyclictest2093103-21kworker/10:1+events22:28:222
1929511993130,1cyclictest1774-21snmpd23:34:5414
1929511993130,1cyclictest1774-21snmpd23:34:5314
192951199310,30cyclictest0-21swapper/820:55:3414
1929509993130,1cyclictest1774-21snmpd22:12:5013
192950999310,30cyclictest0-21swapper/720:44:4813
1929504993129,2cyclictest1774-21snmpd22:36:1212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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