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2026-07-07 - 08:01

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Tue Jul 07, 2026 00:46:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5494552373352,13sleep110-21swapper/1119:07:103
5493472368324,14sleep30-21swapper/319:05:429
5493482364321,13sleep40-21swapper/419:05:4310
5493452362317,14sleep10-21swapper/119:05:391
5493982351329,14sleep90-21swapper/919:06:1915
5495612349327,14sleep140-21swapper/1419:08:336
5495282349325,15sleep50-21swapper/519:08:0911
5493342349329,13sleep70-21swapper/719:05:2913
5495212348324,15sleep150-21swapper/1519:08:027
5493852348330,12sleep20-21swapper/219:06:128
5496322347326,14sleep80-21swapper/819:09:3114
5495152346325,14sleep100-21swapper/1019:07:572
5496062345322,15sleep60-21swapper/619:09:1412
5493402345324,14sleep130-21swapper/1319:05:365
5494982343321,14sleep120-21swapper/1219:07:444
5493442342320,15sleep00-21swapper/019:05:380
6046962580,0sleep140-21swapper/1420:15:196
550119993535,0cyclictest0-21swapper/823:14:2114
550119993535,0cyclictest0-21swapper/823:14:2014
550119993434,0cyclictest0-21swapper/800:31:1914
55012399330,30cyclictest0-21swapper/920:00:1415
550119993333,0cyclictest0-21swapper/820:30:2214
550119993332,1cyclictest1769-21arpwatch22:18:0714
550119993331,2cyclictest658503-21kworker/u32:3+flush-259:022:25:3014
550132993229,3cyclictest0-21swapper/1223:15:164
550132993229,3cyclictest0-21swapper/1223:15:154
550113993229,3cyclictest1774-21snmpd23:00:0312
55014499310,30cyclictest0-21swapper/1522:22:497
55013999310,30cyclictest0-21swapper/1423:10:056
55013999310,30cyclictest0-21swapper/1423:10:056
55013999310,30cyclictest0-21swapper/1422:22:046
55013999310,30cyclictest0-21swapper/1421:35:176
55013999310,30cyclictest0-21swapper/1419:37:126
55013499310,30cyclictest0-21swapper/1300:07:485
55013299310,30cyclictest0-21swapper/1219:35:564
550125993130,1cyclictest903777-21kworker/10:1+events00:33:232
550125993130,1cyclictest650694-21kworker/10:0+events21:48:382
550125993129,1cyclictest888092-21ethtool00:15:142
550125993129,1cyclictest541777-21kworker/10:1+events19:40:162
55012599310,30cyclictest0-21swapper/1022:35:142
55012399310,30cyclictest0-21swapper/923:20:1615
550119993131,0cyclictest0-21swapper/823:37:3114
550119993131,0cyclictest0-21swapper/822:58:4314
550119993131,0cyclictest0-21swapper/822:47:5814
550119993131,0cyclictest0-21swapper/822:32:3814
550119993131,0cyclictest0-21swapper/821:42:3114
550119993131,0cyclictest0-21swapper/800:15:5114
55011699310,30cyclictest0-21swapper/722:42:4013
55011099310,30cyclictest0-21swapper/520:55:0411
55011099310,30cyclictest0-21swapper/519:57:5311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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