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2026-01-29 - 09:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Thu Jan 29, 2026 00:46:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18289212393372,14sleep70-21swapper/719:07:3513
18288372376357,13sleep50-21swapper/519:06:4411
18287522372352,13sleep140-21swapper/1419:05:496
18289122371365,4sleep20-21swapper/219:07:308
18287692360319,33sleep80-21swapper/819:05:5914
18287632357337,13sleep30-21swapper/319:05:559
18255962356347,6sleep60-21swapper/619:05:0912
18289572353344,6sleep10-21swapper/119:08:011
18290952352332,13sleep100-21swapper/1019:09:302
18291202351331,13sleep150-21swapper/1519:09:527
18287822350331,13sleep00-21swapper/019:06:070
18288652349329,13sleep90-21swapper/919:07:0415
18287292349329,13sleep120-21swapper/1219:05:314
18287642347328,12sleep40-21swapper/419:05:5510
18287272347328,13sleep110-21swapper/1119:05:303
18287772346325,14sleep130-21swapper/1319:06:045
1829538993636,0cyclictest0-21swapper/1222:40:154
182950999364,32cyclictest2114657-21kworker/u32:4+flush-259:023:36:098
1829538993535,0cyclictest0-21swapper/1223:42:194
1829538993535,0cyclictest0-21swapper/1223:11:114
1829538993535,0cyclictest0-21swapper/1221:51:174
1829538993535,0cyclictest0-21swapper/1200:20:274
1829544993410,11cyclictest0-21swapper/1422:49:216
1829544993410,11cyclictest0-21swapper/1421:32:286
1829538993434,0cyclictest0-21swapper/1222:09:194
182954499339,11cyclictest0-21swapper/1420:26:346
182954499339,11cyclictest0-21swapper/1400:28:136
182954199330,32cyclictest0-21swapper/1322:07:485
182953899334,29cyclictest0-21swapper/1223:30:144
182953099330,32cyclictest0-21swapper/900:26:1815
182950999330,32cyclictest0-21swapper/223:51:348
182950999330,30cyclictest782-21systemd-journal20:45:418
1829506993333,0cyclictest0-21swapper/123:59:011
1829506993333,0cyclictest0-21swapper/121:13:571
1829506993332,1cyclictest0-21swapper/121:15:321
182954499329,10cyclictest0-21swapper/1419:53:376
1829538993232,0cyclictest0-21swapper/1200:26:214
182952799321,30cyclictest0-21swapper/823:43:4014
1829525993210,0cyclictest0-21swapper/721:46:1113
182952099320,1cyclictest0-21swapper/622:45:1412
182950999320,29cyclictest0-21swapper/221:05:398
182950999320,29cyclictest0-21swapper/221:01:168
182950999320,29cyclictest0-21swapper/220:17:468
182950999320,29cyclictest0-21swapper/220:11:458
182950999320,29cyclictest0-21swapper/220:09:548
182950999320,29cyclictest0-21swapper/220:09:538
182950999320,29cyclictest0-21swapper/219:56:198
182950999320,29cyclictest0-21swapper/219:56:198
182950999320,29cyclictest0-21swapper/219:10:298
1829506993232,0cyclictest0-21swapper/123:50:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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