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2026-03-22 - 10:56

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Sun Mar 22, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31193032406386,13sleep120-21swapper/1219:08:064
31192662385339,14sleep130-21swapper/1319:07:355
31192772364322,14sleep50-21swapper/519:07:4311
31192092364327,14sleep60-21swapper/619:06:5612
31191852359324,28sleep10-21swapper/119:06:361
31192722353332,14sleep20-21swapper/219:07:418
31194042352332,13sleep70-21swapper/719:09:2213
31194452351323,13sleep40-21swapper/419:09:5110
31191952351331,13sleep90-21swapper/919:06:4415
31191682349330,12sleep80-21swapper/819:06:2714
31194382348332,10sleep140-21swapper/1419:09:456
31191842347327,13sleep00-21swapper/019:06:340
31191302346326,13sleep100-21swapper/1019:05:562
31190332343323,13sleep150-21swapper/1519:05:297
31159642342321,14sleep110-21swapper/1119:05:083
31193612339318,14sleep30-21swapper/319:08:479
3119898995046,3cyclictest3135987-21kworker/u32:0+flush-259:020:10:178
311993799445,14cyclictest0-21swapper/1423:59:406
3119898993732,3cyclictest3482536-21kworker/u32:3+events_unbound00:31:258
3119898993732,3cyclictest3349472-21kworker/u32:1+flush-259:023:00:378
3119905993636,0cyclictest0-21swapper/421:34:0610
311993799341,32cyclictest0-21swapper/1421:42:526
3119937993410,11cyclictest0-21swapper/1423:48:426
3119928993428,6cyclictest1774-21snmpd22:52:374
3119905993434,0cyclictest0-21swapper/420:29:2910
3119905993434,0cyclictest0-21swapper/420:03:5410
3119928993329,4cyclictest3177700-21ethtool20:15:144
3119923993329,3cyclictest1774-21snmpd21:00:452
311992399330,32cyclictest0-21swapper/1020:32:472
311992399330,30cyclictest0-21swapper/1023:25:142
3119921993333,0cyclictest0-21swapper/900:24:5515
3119921993332,1cyclictest3140419-21kworker/u32:1+events_unbound19:45:1615
311991699330,32cyclictest0-21swapper/800:38:3714
311991199330,32cyclictest0-21swapper/620:39:3212
3119898993329,3cyclictest3200274-21kworker/u32:4+events_unbound22:41:548
311989899331,32cyclictest3402996-21kworker/u32:1+events_unbound23:37:218
311993799320,30cyclictest0-21swapper/1400:13:576
311992899320,1cyclictest0-21swapper/1219:26:574
3119916993230,2cyclictest0-21swapper/821:33:3614
3119905993232,0cyclictest0-21swapper/422:44:2110
3119905993232,0cyclictest0-21swapper/400:20:4610
3119905993229,3cyclictest601ktimers/400:13:1610
3119898993228,3cyclictest3208676-21kworker/u32:2+events_unbound20:55:138
3119898993228,2cyclictest3349472-21kworker/u32:1+flush-259:023:07:448
311989899322,1cyclictest3200274-21kworker/u32:4+events_unbound21:46:288
311989899320,29cyclictest0-21swapper/223:48:228
311989899320,29cyclictest0-21swapper/223:30:338
311989899320,29cyclictest0-21swapper/221:58:008
311989899320,29cyclictest0-21swapper/221:57:598
311989899320,29cyclictest0-21swapper/220:51:208
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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