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2025-12-05 - 10:48

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Fri Dec 05, 2025 00:46:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9602822361319,14sleep100-21swapper/1019:09:332
9602592361321,14sleep70-21swapper/719:09:1413
9601792360323,30sleep40-21swapper/419:08:0710
9602072357317,14sleep130-21swapper/1319:08:325
9602202354336,11sleep30-21swapper/319:08:389
9568602352316,28sleep10-21swapper/119:05:071
9601802351330,13sleep50-21swapper/519:08:0811
9601052351332,12sleep90-21swapper/919:07:0715
9601042351331,13sleep80-21swapper/819:07:0614
9600202351330,14sleep20-21swapper/219:05:568
9602232348327,14sleep60-21swapper/619:08:4112
9600332347326,14sleep150-21swapper/1519:06:097
9602052344323,14sleep110-21swapper/1119:08:303
9603092343322,14sleep140-21swapper/1419:09:546
9600472341320,14sleep120-21swapper/1219:06:224
9602952340320,13sleep00-21swapper/019:09:390
96073799467,14cyclictest0-21swapper/521:17:1111
960768994543,2cyclictest1223592-21kworker/u32:4+events_unbound00:25:297
960768994241,1cyclictest986363-21kworker/u32:3+events_unbound19:45:197
96075999331,31cyclictest726317-21chrome20:20:594
960747993332,1cyclictest956020-21kworker/u32:4+flush-259:019:40:1814
960732993330,3cyclictest1202913-21latency_hist00:00:009
960722993333,0cyclictest947691-1kworker/u33:1+i915_flip20:35:170
960768993232,0cyclictest0-21swapper/1523:20:217
960768993231,1cyclictest1198595-21kworker/u32:0+events_unbound00:05:187
960759993227,5cyclictest1082274-21latency_hist21:34:594
960768993130,1cyclictest1047144-21mii-tool20:50:187
960765993130,1cyclictest2395797-21snmpd20:43:526
96076399310,30cyclictest0-21swapper/1322:47:585
96076399310,30cyclictest0-21swapper/1321:23:505
96076399310,30cyclictest0-21swapper/1320:09:485
960759993128,3cyclictest2395797-21snmpd21:50:224
96075999310,30cyclictest0-21swapper/1223:56:144
96075999310,30cyclictest0-21swapper/1223:50:404
96075999310,30cyclictest0-21swapper/1223:43:044
96075999310,30cyclictest0-21swapper/1223:01:314
96075999310,30cyclictest0-21swapper/1222:41:354
96075999310,30cyclictest0-21swapper/1222:23:254
96075999310,30cyclictest0-21swapper/1221:58:104
96075999310,30cyclictest0-21swapper/1221:48:484
96075999310,30cyclictest0-21swapper/1221:27:434
96075999310,30cyclictest0-21swapper/1220:59:554
96075999310,30cyclictest0-21swapper/1220:11:374
96075999310,30cyclictest0-21swapper/1219:42:474
96075999310,30cyclictest0-21swapper/1219:33:554
96075999310,30cyclictest0-21swapper/1219:20:094
96075999310,30cyclictest0-21swapper/1219:10:374
96075999310,30cyclictest0-21swapper/1200:25:234
96075999310,30cyclictest0-21swapper/1200:15:194
96075399310,30cyclictest0-21swapper/1023:21:482
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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