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2025-08-30 - 02:47

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Sat Aug 30, 2025 00:46:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32930012393373,13sleep30-21swapper/319:09:509
32928352391384,5sleep100-21swapper/1019:07:482
32928692371339,25sleep10-21swapper/119:08:111
32929622364341,15sleep50-21swapper/519:09:2011
32927782355317,30sleep150-21swapper/1519:07:057
32929282354334,13sleep110-21swapper/1119:08:533
32927632354333,13sleep60-21swapper/619:06:5612
32929252353344,6sleep90-21swapper/919:08:5115
32928582352332,13sleep70-21swapper/719:08:0113
32929652351331,13sleep80-21swapper/819:09:2314
32929302351331,13sleep130-21swapper/1319:08:555
32928042350330,13sleep40-21swapper/419:07:2610
32929972347327,13sleep00-21swapper/019:09:470
32894922347327,13sleep120-21swapper/1219:05:094
32929592346327,12sleep20-21swapper/219:09:168
32894942346326,13sleep140-21swapper/1419:05:116
3293491997362,6cyclictest3410494-21kworker/u32:0+events_unbound22:10:185
3293491995150,0cyclictest0-21swapper/1322:35:165
3293476995050,0cyclictest0-21swapper/823:12:3414
329347699477,39cyclictest97-21ksoftirqd/823:43:0314
329347699457,25cyclictest0-21swapper/823:21:0414
329347699456,39cyclictest97-21ksoftirqd/821:42:1314
3293460994444,0cyclictest0-21swapper/320:18:599
329346099442,42cyclictest3322112-21kworker/3:1-events23:12:349
3293460994343,0cyclictest0-21swapper/322:53:469
3293460994241,0cyclictest0-21swapper/322:10:049
3293491994141,0cyclictest0-21swapper/1321:00:195
3293491994141,0cyclictest0-21swapper/1321:00:195
3293476994141,0cyclictest0-21swapper/819:27:0114
3293460994141,0cyclictest0-21swapper/322:44:529
3293476994040,0cyclictest0-21swapper/820:18:5914
329347699401,4cyclictest211rcu_preempt22:10:1814
3293476993938,1cyclictest3276385-21kworker/u32:0+flush-259:020:25:1814
329347699393,36cyclictest0-21swapper/822:01:3214
3293491993832,5cyclictest1411ktimers/1319:17:415
3293476993838,0cyclictest0-21swapper/820:47:5714
3293491993728,5cyclictest3515666-21kworker/u32:2+events_unbound00:31:065
3293491993713,24cyclictest0-21swapper/1319:37:475
3293476993737,0cyclictest0-21swapper/819:53:5514
3293474993733,2cyclictest3271986-21kworker/u32:2+flush-259:019:25:3713
3293460993737,0cyclictest0-21swapper/300:02:229
3293491993636,0cyclictest0-21swapper/1322:17:005
3293491993636,0cyclictest0-21swapper/1300:25:165
3293476993636,0cyclictest0-21swapper/822:42:0414
3293474993631,3cyclictest3456738-21kworker/u32:0+events_unbound23:37:0213
3293460993636,0cyclictest0-21swapper/322:00:069
329346099360,36cyclictest0-21swapper/319:17:149
3293491993535,0cyclictest0-21swapper/1323:09:405
3293491993535,0cyclictest0-21swapper/1323:01:485
3293491993535,0cyclictest0-21swapper/1322:50:205
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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