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2026-08-18 - 10:10

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Tue Aug 18, 2026 00:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
392037199110105,4cyclictest3890407-21kworker/u32:1+events_unbound19:12:255
392034999102100,1cyclictest4021461-21kworker/u32:4+events_unbound21:07:3711
391967526764,1sleep100-21swapper/1019:06:262
3920351996665,1cyclictest4076892-21kworker/u32:4+flush-259:022:45:1812
3920354996355,6cyclictest4065795-21kworker/u32:0+events_unbound21:46:0113
3920349996259,2cyclictest3831632-21kworker/u32:4+events_unbound19:20:1611
3920354996156,4cyclictest4171512-21kworker/u32:4+flush-259:023:31:0213
41426432590,0sleep20-21swapper/222:44:508
3920351995957,2cyclictest3918429-21kworker/u32:2+events_unbound19:24:0012
391959825755,1sleep40-21swapper/419:05:3210
391991225653,2sleep120-21swapper/1219:09:254
3920351995351,2cyclictest17106-21kworker/u32:3+events_unbound23:55:2612
3920373995250,2cyclictest3918429-21kworker/u32:2+flush-259:022:16:276
3920362995247,3cyclictest4052401-21kworker/u32:3+events_unbound21:39:202
392034199520,37cyclictest0-21swapper/319:15:019
3920351995048,2cyclictest4171512-21kworker/u32:4+events_unbound23:37:2712
3920351994948,1cyclictest3925161-21kworker/u32:3+events_unbound19:30:2112
3920362994847,1cyclictest3918429-21kworker/u32:2+events_unbound20:59:322
3920371994745,1cyclictest3831632-21kworker/u32:4+events_unbound19:40:145
3920371994644,2cyclictest4052401-21kworker/u32:3+flush-259:022:09:395
418998450,43rtkit-daemon0-21swapper/119:09:121
3920333994543,1cyclictest17106-21kworker/u32:3+events_unbound00:07:490
391968424543,1sleep20-21swapper/219:06:358
3920371994443,1cyclictest4173097-21kworker/u32:5+events_unbound23:20:055
3920371994441,2cyclictest3890407-21kworker/u32:1+events_unbound19:15:015
3920362994443,1cyclictest4065795-21kworker/u32:0+events_unbound21:50:132
3920371994342,1cyclictest61586-21kworker/u32:2+events_unbound00:14:515
3920368994342,1cyclictest4052401-21kworker/u32:3+flush-259:022:30:224
3920368994341,1cyclictest3907068-21kworker/u32:0+flush-259:019:10:144
3920365994341,2cyclictest4171512-21kworker/u32:4+events_unbound23:07:183
3920362994342,1cyclictest17106-21kworker/u32:3+flush-259:000:05:262
3920351994341,2cyclictest68538-21kworker/u32:3+events_unbound00:26:4412
3920351994341,2cyclictest68538-21kworker/u32:3+events_unbound00:26:4312
391980224340,2sleep60-21swapper/619:07:5912
392037399424,25cyclictest1161449-21thunderbird20:13:456
3920371994240,1cyclictest4076892-21kworker/u32:4+events_unbound22:45:195
3920362994241,1cyclictest4030949-21kworker/u32:5+events_unbound21:15:392
3920349994240,2cyclictest3918429-21kworker/u32:2+events_unbound22:22:5111
391989924240,1sleep00-21swapper/019:09:130
3920376994138,2cyclictest3918429-21kworker/u32:2+events_unbound21:35:227
3920360994140,1cyclictest4134064-21kworker/u32:2+events_unbound22:40:2615
3920341994138,1cyclictest0-21swapper/322:17:449
3920362994039,1cyclictest3918429-21kworker/u32:2+events_unbound22:14:172
3920349994039,1cyclictest3986768-21kworker/u32:1+events_unbound20:30:1311
391961324037,2sleep150-21swapper/1519:05:437
3920362993927,10cyclictest3992361-21kworker/10:2+events21:10:162
3920351993938,1cyclictest3918429-21kworker/u32:2+events_unbound21:36:2612
3920339993938,1cyclictest4171512-21kworker/u32:4+events_unbound00:10:238
391995523937,1sleep110-21swapper/1119:09:563
391977923937,1sleep50-21swapper/519:07:4211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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