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2026-03-28 - 11:10

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Sat Mar 28, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35453102404392,10sleep00-21swapper/019:05:010
35488232373336,13sleep110-21swapper/1119:08:093
35487312361342,13sleep30-21swapper/319:06:579
35486702357348,6sleep80-21swapper/819:06:1414
35454822356316,14sleep40-21swapper/419:05:0510
35489142355335,13sleep150-21swapper/1519:09:187
35487892355318,29sleep130-21swapper/1319:07:385
35487642354334,13sleep140-21swapper/1419:07:246
35486942354345,6sleep90-21swapper/919:06:3115
35486952353333,13sleep100-21swapper/1019:06:322
35488812352333,12sleep60-21swapper/619:08:5212
35486232352331,14sleep10-21swapper/119:05:341
35454852352331,14sleep70-21swapper/719:05:0813
35488322350330,13sleep20-21swapper/219:08:168
35487032348328,13sleep120-21swapper/1219:06:344
35488352346325,14sleep50-21swapper/519:08:1911
354948099424,25cyclictest0-21swapper/1421:18:496
354948099423,25cyclictest0-21swapper/1423:30:376
354948099413,25cyclictest0-21swapper/1422:46:416
354948099413,25cyclictest0-21swapper/1421:40:476
354948099413,25cyclictest0-21swapper/1420:56:516
354948099413,25cyclictest0-21swapper/1419:17:596
354948099413,25cyclictest0-21swapper/1400:36:316
3549471994137,4cyclictest0-21swapper/1123:29:053
354948099402,25cyclictest0-21swapper/1420:12:556
354948099390,14cyclictest0-21swapper/1421:29:486
354948099380,25cyclictest0-21swapper/1419:50:576
3549471993734,2cyclictest3739294-21kworker/u32:2+flush-259:023:30:173
354948099340,9cyclictest0-21swapper/1420:01:566
354948099332,18cyclictest0-21swapper/1420:45:516
3549477993332,1cyclictest3557749-21kworker/u32:2+flush-259:020:05:165
3549480993229,3cyclictest1774-21snmpd21:52:096
3549480993229,3cyclictest1774-21snmpd21:52:096
354948099317,13cyclictest0-21swapper/1423:08:396
3549480993121,1cyclictest0-21swapper/1422:03:006
354948099310,30cyclictest0-21swapper/1422:09:036
3549477993130,1cyclictest3739294-21kworker/u32:2+flush-259:023:10:155
354947499310,30cyclictest0-21swapper/1221:33:444
354947499310,30cyclictest0-21swapper/1200:09:304
354947199310,30cyclictest0-21swapper/1122:30:153
3549469993130,1cyclictest3841640-21kworker/10:2+events23:45:472
3549469993130,1cyclictest3721816-21kworker/10:1+events23:36:332
3549469993130,1cyclictest3721816-21kworker/10:1+events22:40:472
3549469993129,1cyclictest3721816-21kworker/10:1+events23:13:232
3549469993129,1cyclictest3721816-21kworker/10:1+events22:46:212
3549469993129,1cyclictest3679594-21kworker/10:1+events21:46:512
3549469993129,1cyclictest3679594-21kworker/10:1+events21:37:452
3549469993129,1cyclictest3612843-21kworker/10:2+events20:48:412
3549469993129,1cyclictest3569599-21kworker/10:2+events19:40:212
3549469993129,1cyclictest3551798-21kworker/10:0+events20:20:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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