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2026-01-22 - 08:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Thu Jan 22, 2026 00:46:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9969992386363,15sleep140-21swapper/1419:05:046
10004232363348,10sleep20-21swapper/219:09:098
10001732360314,15sleep150-21swapper/1519:05:537
10001372349306,14sleep110-21swapper/1119:05:323
10003512344322,14sleep60-21swapper/619:08:0912
10002912342324,11sleep70-21swapper/719:07:2113
10002752342320,14sleep80-21swapper/819:07:0614
10004772341320,14sleep120-21swapper/1219:09:514
10004082340322,12sleep40-21swapper/419:08:5410
10003672340318,15sleep50-21swapper/519:08:2411
10004552338298,32sleep130-21swapper/1319:09:365
10002332338315,15sleep90-21swapper/919:06:3515
10002122336313,15sleep100-21swapper/1019:06:192
10002672333311,15sleep00-21swapper/019:06:580
10004872331309,14sleep30-21swapper/319:09:599
10002852331309,15sleep10-21swapper/119:07:151
1000944995957,2cyclictest1208914-21kworker/u32:2+events_unbound23:05:1913
1000944995754,3cyclictest0-21swapper/700:08:4013
1000944995652,4cyclictest0-21swapper/723:18:5713
1000944995538,15cyclictest4450-21chrome23:29:2913
1000944995350,3cyclictest0-21swapper/719:57:2913
1000944995248,0cyclictest0-21swapper/722:58:0713
1000944995245,3cyclictest0-21swapper/721:14:4713
1000944995147,0cyclictest0-21swapper/722:29:3513
1000944995143,5cyclictest1769-21arpwatch23:53:0313
1000944995138,4cyclictest211rcu_preempt21:32:4113
100094499510,41cyclictest0-21swapper/721:26:0713
1000944994946,3cyclictest0-21swapper/721:47:0313
1000944994945,4cyclictest0-21swapper/722:33:2513
1000944994945,0cyclictest0-21swapper/721:41:2613
1000944994916,28cyclictest0-21swapper/723:39:4113
1000944994846,2cyclictest1240787-21kworker/u32:3+events_unbound23:43:4313
1000944994844,4cyclictest0-21swapper/700:19:5313
1000944994834,9cyclictest0-21swapper/720:23:1813
12126622470,0sleep110-21swapper/1122:35:133
1000944994744,3cyclictest0-21swapper/722:09:4113
1000944994744,3cyclictest0-21swapper/721:52:3813
1000944994743,4cyclictest0-21swapper/722:20:0513
1000944994743,4cyclictest0-21swapper/700:04:3713
1000944994743,4cyclictest0-21swapper/700:04:3713
1000944994743,0cyclictest0-21swapper/722:16:1713
1000944994743,0cyclictest0-21swapper/721:08:4713
1000944994739,4cyclictest1222454-21ssh22:43:1213
1000944994642,4cyclictest0-21swapper/723:56:3313
1000944994642,4cyclictest0-21swapper/723:56:3313
1000944994642,4cyclictest0-21swapper/721:21:2713
1000944994638,8cyclictest861rcuc/722:01:4513
1000944994638,5cyclictest1769-21arpwatch00:13:4113
1000944994638,4cyclictest1146151-21kworker/7:0-mm_percpu_wq21:58:0913
1000944994638,4cyclictest0-21swapper/722:10:2913
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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