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2026-04-26 - 05:02

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Sun Apr 26, 2026 00:46:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15283032362324,31sleep70-21swapper/719:06:1413
15286012360340,13sleep140-21swapper/1419:09:516
15282312360320,14sleep20-21swapper/219:05:378
15282212360340,13sleep130-21swapper/1319:05:315
15284712358349,6sleep90-21swapper/919:08:0915
15283222353334,12sleep50-21swapper/519:06:2811
15282842352331,14sleep100-21swapper/1019:06:012
15285572351332,12sleep150-21swapper/1519:09:207
15285182351330,14sleep00-21swapper/019:08:480
15284632351331,13sleep10-21swapper/119:08:011
15285452350311,14sleep40-21swapper/419:09:0810
15285442350330,13sleep30-21swapper/319:09:079
15284682350330,13sleep60-21swapper/619:08:0512
15282512350330,13sleep120-21swapper/1219:05:474
15282182349338,7sleep110-21swapper/1119:05:303
15284872347326,14sleep80-21swapper/819:08:2414
1529071994443,1cyclictest1571662-21kworker/u32:3+flush-259:020:10:1815
152908799339,11cyclictest0-21swapper/1422:17:296
1529064993333,0cyclictest0-21swapper/622:04:1312
1529064993330,3cyclictest0-21swapper/623:52:1512
1529050993330,3cyclictest1774-21snmpd19:58:088
152905099330,30cyclictest0-21swapper/223:40:248
152908799328,11cyclictest0-21swapper/1419:21:456
152908799327,25cyclictest0-21swapper/1423:23:236
1529071993231,1cyclictest1746304-21kworker/u32:3+events_unbound22:40:1915
152909099310,30cyclictest0-21swapper/1522:49:467
152909099310,30cyclictest0-21swapper/1522:20:167
152909099310,28cyclictest0-21swapper/1519:15:157
152908799310,30cyclictest0-21swapper/1420:25:166
1529085993129,1cyclictest1774-21snmpd20:57:285
152908599310,30cyclictest0-21swapper/1323:03:025
152908599310,30cyclictest0-21swapper/1320:00:175
1529080993130,1cyclictest1774-21snmpd23:45:124
1529080993130,1cyclictest133-21ksoftirqd/1221:49:194
1529080993130,1cyclictest133-21ksoftirqd/1221:49:194
1529077993128,3cyclictest1774-21snmpd22:31:013
152907599310,30cyclictest0-21swapper/1019:33:462
1529071993131,0cyclictest0-21swapper/921:49:5115
1529071993131,0cyclictest0-21swapper/921:49:5115
1529066993130,1cyclictest1774-21snmpd22:27:4613
152906499313,28cyclictest0-21swapper/623:57:5712
152905999310,30cyclictest0-21swapper/522:20:2111
152905699310,30cyclictest0-21swapper/422:42:3410
152905099310,30cyclictest0-21swapper/222:40:018
152905099310,30cyclictest0-21swapper/221:54:278
152904899310,30cyclictest0-21swapper/122:55:591
152904899310,30cyclictest0-21swapper/121:46:021
152904899310,30cyclictest0-21swapper/121:46:021
1529045993130,1cyclictest1774-21snmpd00:33:050
152904599310,30cyclictest0-21swapper/019:53:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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