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2026-01-19 - 09:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Mon Jan 19, 2026 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5236832359351,5sleep30-21swapper/319:08:549
5236732346327,12sleep100-21swapper/1019:08:452
5237052343322,14sleep60-21swapper/619:09:1312
5235562343318,15sleep150-21swapper/1519:07:137
5234782343333,6sleep110-21swapper/1119:06:213
5237312342318,17sleep80-21swapper/819:09:3114
5236302341318,15sleep70-21swapper/719:08:1113
5237362339316,15sleep130-21swapper/1319:09:365
5235772339316,16sleep90-21swapper/919:07:2315
5236412338314,15sleep10-21swapper/119:08:201
5234412338315,14sleep00-21swapper/019:05:550
5235522336314,15sleep120-21swapper/1219:07:104
5237282335313,14sleep50-21swapper/519:09:2811
5236252334310,15sleep40-21swapper/419:08:0710
5237252330309,14sleep20-21swapper/219:09:258
5202722325304,14sleep140-21swapper/1419:05:046
524243995048,2cyclictest624658-21kworker/u32:2+flush-259:022:14:0415
52425999469,13cyclictest0-21swapper/1400:29:036
52425999457,25cyclictest0-21swapper/1419:43:286
524228993937,2cyclictest562354-21kworker/u32:3+events_unbound20:57:0711
524261993526,5cyclictest0-21swapper/1520:25:157
52425999348,25cyclictest0-21swapper/1421:44:176
524228993434,0cyclictest0-21swapper/523:23:1011
52424999330,30cyclictest0-21swapper/1122:25:133
52425999327,14cyclictest0-21swapper/1422:28:136
524261993127,4cyclictest1774-21snmpd22:46:187
52425999317,13cyclictest0-21swapper/1420:49:226
52425999310,30cyclictest0-21swapper/1423:30:086
52425999310,30cyclictest0-21swapper/1421:28:156
52425599310,30cyclictest0-21swapper/1323:52:425
52425399310,30cyclictest0-21swapper/1223:04:194
524249993124,2cyclictest0-21swapper/1119:20:133
52424999310,1cyclictest0-21swapper/1100:30:153
524246993130,1cyclictest809066-21kworker/10:2+events23:38:342
524246993129,1cyclictest400590-21kworker/10:2+events21:19:252
52424699310,30cyclictest0-21swapper/1022:59:252
52424699310,30cyclictest0-21swapper/1022:32:092
524243993130,1cyclictest1774-21snmpd19:34:4215
52424399310,30cyclictest0-21swapper/922:36:4215
52423999310,30cyclictest0-21swapper/800:08:3914
52423999310,28cyclictest0-21swapper/820:20:1514
524228993131,0cyclictest0-21swapper/500:35:2811
524228993130,1cyclictest795970-21kworker/u32:4+events_unbound23:30:1811
524228993130,1cyclictest1774-21snmpd00:16:1011
524228993127,4cyclictest0-21swapper/521:33:2911
52422899310,30cyclictest0-21swapper/521:55:1511
52422899310,30cyclictest0-21swapper/521:55:1511
52422899310,30cyclictest0-21swapper/520:30:2211
52422499310,30cyclictest0-21swapper/423:45:2910
52422499310,1cyclictest0-21swapper/423:58:3310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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