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2026-02-18 - 11:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Wed Feb 18, 2026 00:46:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3664022378357,13sleep90-21swapper/919:06:5115
3665292376356,13sleep150-21swapper/1519:08:357
3663362365344,14sleep70-21swapper/719:06:0213
3664152358341,10sleep40-21swapper/419:07:0310
3663292355336,12sleep20-21swapper/219:05:568
3666502354347,5sleep120-21swapper/1219:09:524
3665732352332,13sleep140-21swapper/1419:09:066
3664512352343,6sleep10-21swapper/119:07:311
3664242351332,12sleep110-21swapper/1119:07:103
3663432350330,13sleep130-21swapper/1319:06:085
3665432348328,13sleep60-21swapper/619:08:4212
3663582348329,13sleep80-21swapper/819:06:1914
3664662347326,14sleep100-21swapper/1019:07:412
3663542346326,13sleep50-21swapper/519:06:1611
3663072340322,12sleep30-21swapper/319:05:429
3664502326306,13sleep00-21swapper/019:07:310
3773752650,0sleep80-21swapper/819:20:1214
36712399360,23cyclictest0-21swapper/1423:09:396
36712399350,22cyclictest0-21swapper/1420:13:546
367093993411,23cyclictest0-21swapper/420:06:2710
367125993325,4cyclictest0-21swapper/1520:30:417
367123993310,10cyclictest0-21swapper/1400:15:326
367093993329,4cyclictest707634-21ethtool00:15:1510
36709199330,32cyclictest0-21swapper/321:55:139
36711299320,31cyclictest0-21swapper/1022:22:152
36709199320,29cyclictest0-21swapper/322:35:159
367125993131,0cyclictest0-21swapper/1523:34:157
367125993130,1cyclictest720727-21nodev-device-ev00:25:187
36712599310,30cyclictest0-21swapper/1519:30:127
367123993130,1cyclictest1774-21snmpd23:49:126
367123993118,0cyclictest0-21swapper/1421:41:466
36711999310,30cyclictest0-21swapper/1319:42:015
36711799310,30cyclictest0-21swapper/1222:35:124
367112993130,1cyclictest492449-21kworker/10:1+events22:35:452
367112993130,1cyclictest492449-21kworker/10:1+events22:02:212
367112993129,1cyclictest1774-21snmpd20:20:052
36711299310,30cyclictest0-21swapper/1021:18:492
36710799310,30cyclictest0-21swapper/920:47:2715
367102993129,2cyclictest1774-21snmpd20:50:0313
36708699310,30cyclictest0-21swapper/219:49:288
36708699310,30cyclictest0-21swapper/219:49:288
36708199310,30cyclictest0-21swapper/023:54:060
36708199310,30cyclictest0-21swapper/023:30:140
36708199310,30cyclictest0-21swapper/022:30:030
36708199310,30cyclictest0-21swapper/022:27:240
36708199310,30cyclictest0-21swapper/021:10:460
36708199310,30cyclictest0-21swapper/020:31:500
367125993029,1cyclictest1774-21snmpd20:56:517
36712599300,30cyclictest0-21swapper/1519:47:137
36712599300,30cyclictest0-21swapper/1519:47:127
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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