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2026-08-30 - 01:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Aug 29, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
267754899731730,1cyclictest0-21swapper/1122:38:393
26775269957318,554cyclictest0-21swapper/520:38:5411
26775269957318,554cyclictest0-21swapper/520:38:5411
2677566995294,521cyclictest0-21swapper/1523:40:537
267751899525525,0cyclictest0-21swapper/323:00:539
267753299520518,2cyclictest2751035-21kworker/7:1+i915-unordered20:46:5413
2677508995180,517cyclictest0-21swapper/021:57:530
26775149951374,438cyclictest2831437-21kworker/2:2+i915-unordered22:15:538
267754899500441,29cyclictest0-21swapper/1121:35:533
267756299492490,2cyclictest2690317-21kworker/14:0+i915-unordered19:25:546
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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