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2026-06-14 - 20:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sun Jun 14, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
343896199692691,1cyclictest0-21swapper/419:41:3910
343894899492490,2cyclictest3683511-21kworker/1:2+i915-unordered00:09:171
343898099490489,1cyclictest0-21swapper/900:09:1715
343898099479478,1cyclictest3547379-21kworker/9:0+i915-unordered21:30:1715
3438982994781,476cyclictest0-21swapper/1020:13:172
343895799476476,0cyclictest0-21swapper/322:00:179
343898099475473,2cyclictest3640478-21kworker/9:1+i915-unordered22:59:1715
34389649947423,30cyclictest0-21swapper/520:43:0211
34389489947324,29cyclictest0-21swapper/123:15:391
343898299472470,2cyclictest3576762-21kworker/10:1+i915-unordered22:11:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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