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2025-08-21 - 21:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Thu Aug 21, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318740899551550,1cyclictest3266375-21kworker/7:1+i915-unordered21:15:4413
318743199546100,445cyclictest3266409-21kworker/12:1+i915-unordered20:48:444
31874319954599,445cyclictest3378037-21kworker/12:0+i915-unordered23:10:444
31874319952134,487cyclictest0-21swapper/1200:13:444
3187431995136,45cyclictest0-21swapper/1221:15:444
31874319949922,476cyclictest0-21swapper/1222:18:444
318738999495494,1cyclictest3213699-21kworker/2:1+i915-unordered19:54:448
31874319948727,460cyclictest0-21swapper/1221:38:444
318744299483482,1cyclictest3293789-21kworker/15:0+i915-unordered21:20:447
3187431994780,0cyclictest0-21swapper/1221:20:444
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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