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2025-11-22 - 18:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Nov 22, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
204907699737315,421cyclictest0-21swapper/900:02:3315
204910199728727,1cyclictest0-21swapper/1423:06:316
204905199690293,395cyclictest0-21swapper/219:31:328
204905199690293,395cyclictest0-21swapper/219:31:328
20490629956511,553cyclictest0-21swapper/520:55:4711
20490589956140,520cyclictest0-21swapper/422:03:4710
20490629954226,515cyclictest0-21swapper/522:17:4711
20490629954226,515cyclictest0-21swapper/522:17:4711
204905899539538,1cyclictest2185350-21kworker/4:1+i915-unordered21:52:4710
20490469953414,519cyclictest0-21swapper/121:13:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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