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2025-06-29 - 00:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Jun 28, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24072359954523,521cyclictest0-21swapper/400:02:2810
2407243995276,520cyclictest0-21swapper/622:06:2812
240723599512511,1cyclictest2621244-21kworker/4:1+i915-unordered23:28:2810
240723199508507,1cyclictest2535246-21kworker/3:0+i915-unordered21:52:289
240726499498497,1cyclictest2481709-21kworker/11:2+i915-unordered21:02:283
240726499493492,1cyclictest0-21swapper/1121:52:283
240726999489488,1cyclictest2539206-21kworker/12:2+i915-unordered21:48:284
240727799484483,1cyclictest0-21swapper/1421:57:286
240723199482482,0cyclictest0-21swapper/321:02:289
24072749948026,60cyclictest0-21swapper/1319:12:125
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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