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2025-11-15 - 18:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Nov 15, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16899209954724,522cyclictest0-21swapper/221:18:008
168997499530528,2cyclictest1698936-21kworker/15:0+i915-unordered19:33:007
1689920995264,521cyclictest0-21swapper/220:36:008
1689920995264,521cyclictest0-21swapper/220:36:008
1689920995263,521cyclictest0-21swapper/221:12:008
1689916995253,521cyclictest0-21swapper/119:51:001
168992399524523,1cyclictest1913166-21kworker/3:1+i915-unordered23:42:009
1689920995220,520cyclictest0-21swapper/200:23:008
16899639952031,488cyclictest0-21swapper/1200:18:004
168992099508506,2cyclictest1789128-21kworker/2:1+i915-unordered21:04:008
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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