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2026-05-21 - 12:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Thu May 21, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4030518995603,44cyclictest0-21swapper/719:27:0213
40305129952915,512cyclictest0-21swapper/519:42:0211
40305129952915,512cyclictest0-21swapper/519:42:0211
40305079947325,28cyclictest0-21swapper/422:48:2510
403054199468465,2cyclictest4039274-21kworker/12:2+i915-unordered19:20:024
403055499464464,0cyclictest4079509-21kworker/15:0+i915-unordered20:24:027
4030518994615,59cyclictest0-21swapper/722:23:2313
403054599458457,1cyclictest4041943-21kworker/13:1+i915-unordered19:42:025
403054599458457,1cyclictest4041943-21kworker/13:1+i915-unordered19:42:025
4030518994585,58cyclictest0-21swapper/719:30:0213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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