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2026-06-02 - 17:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Jun 02, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
418816999702302,399cyclictest0-21swapper/1000:33:222
4188135995267,519cyclictest0-21swapper/120:40:401
418814599515514,1cyclictest256811-21kworker/4:0+i915-unordered00:34:3910
418814599509507,1cyclictest216539-21kworker/4:2+i915-unordered23:53:4010
418814599499497,2cyclictest148055-21kworker/4:2+i915-unordered22:15:4010
41881819948811,59cyclictest0-21swapper/1222:43:244
418813999485483,2cyclictest35424-21kworker/2:1+i915-unordered20:00:408
418814599484483,1cyclictest160398-21kworker/4:2+i915-unordered22:36:4010
41881459948118,462cyclictest0-21swapper/421:00:4010
4188145994800,479cyclictest0-21swapper/423:21:4010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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