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2026-07-21 - 03:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Jul 21, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2847200995229,512cyclictest0-21swapper/100:10:071
2847205995170,516cyclictest0-21swapper/222:45:078
28471969951629,29cyclictest0-21swapper/019:40:070
2847219995060,505cyclictest0-21swapper/600:19:0712
284724599499497,2cyclictest0-21swapper/1221:27:074
284721599496496,0cyclictest3016713-21kworker/5:0+i915-unordered23:29:0711
284720599495493,1cyclictest3040869-21kworker/2:2+i915-unordered23:08:078
2847234994944,489cyclictest0-21swapper/1020:13:072
2847234994944,489cyclictest0-21swapper/1020:13:072
284724999492492,0cyclictest0-21swapper/1323:29:075
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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