You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-27 - 21:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Fri Feb 27, 2026 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9680249952598,422cyclictest1222362-21kworker/11:1+i915-unordered00:27:223
9680249951587,422cyclictest1174101-21kworker/11:2+i915-unordered23:26:223
9680249951490,423cyclictest1162087-21kworker/11:1+i915-unordered23:36:223
9680249951263,448cyclictest1132486-21kworker/11:0+i915-unordered22:56:223
9680249950581,420cyclictest1069519-21kworker/11:1+i915-unordered21:21:223
96802499494492,2cyclictest976560-21kworker/11:0+i915-unordered19:20:223
96802499493492,1cyclictest1198979-21kworker/11:0+i915-unordered00:38:223
96802499491490,1cyclictest1132486-21kworker/11:0+i915-unordered22:51:223
96802499491490,1cyclictest1000968-21kworker/11:1+i915-unordered19:52:223
96802499491490,1cyclictest1000968-21kworker/11:1+i915-unordered19:52:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional