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2026-05-08 - 09:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Fri May 08, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1503009950910,498cyclictest0-21swapper/723:10:2613
1503009950910,498cyclictest0-21swapper/723:10:2613
150277995023,498cyclictest0-21swapper/123:40:261
1503319949712,29cyclictest0-21swapper/1420:00:266
15030899490489,1cyclictest371142-21kworker/9:1+i915-unordered23:40:2615
15030499482482,0cyclictest195302-21kworker/8:0+i915-unordered20:12:2614
15028999475474,1cyclictest0-21swapper/420:00:2610
1503369947325,29cyclictest0-21swapper/1522:36:477
1503319946726,0cyclictest0-21swapper/1420:49:266
150331994540,57cyclictest0-21swapper/1400:19:116
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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