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2026-06-17 - 21:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Wed Jun 17, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34087949955128,522cyclictest0-21swapper/1219:24:124
34088079953817,519cyclictest0-21swapper/1522:14:117
34087489953520,514cyclictest0-21swapper/121:34:121
34087909952722,28cyclictest0-21swapper/1119:24:123
34087909952348,474cyclictest0-21swapper/1120:21:123
340879099515513,1cyclictest3489376-21kworker/11:0+i915-unordered20:46:123
34087529951013,496cyclictest0-21swapper/222:23:118
340879499500500,0cyclictest0-21swapper/1220:36:124
34087909949517,477cyclictest0-21swapper/1120:13:123
340879499489488,1cyclictest3553247-21kworker/12:0+i915-unordered22:13:124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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