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2026-04-28 - 10:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Apr 28, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46787399525524,1cyclictest0-21swapper/521:16:4511
46787399502501,1cyclictest496653-21kworker/5:2+i915-unordered20:35:4511
4679119949820,478cyclictest0-21swapper/1421:42:446
4679119949820,478cyclictest0-21swapper/1421:42:446
467865994954,490cyclictest0-21swapper/322:01:449
4679119949410,29cyclictest0-21swapper/1420:54:456
46787399489488,1cyclictest159145-21kworker/5:0+i915-unordered19:16:4511
467911994824,477cyclictest0-21swapper/1421:32:446
4679119948018,461cyclictest0-21swapper/1420:35:456
4679119947513,461cyclictest0-21swapper/1422:02:446
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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