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2026-05-11 - 09:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Mon May 11, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4020612995329,522cyclictest0-21swapper/620:59:2112
4020612995329,522cyclictest0-21swapper/620:59:2112
402060099517515,2cyclictest16311-21kworker/3:0+i915-unordered23:12:209
402061699503501,2cyclictest0-21swapper/719:12:2113
40206229949115,60cyclictest106-21ksoftirqd/921:52:2015
40206009949155,435cyclictest0-21swapper/320:37:219
4020600994896,44cyclictest0-21swapper/322:07:209
40206009947817,460cyclictest0-21swapper/321:15:219
4020612994750,60cyclictest79-21ksoftirqd/619:52:2112
402060099473472,1cyclictest56696-21kworker/3:2+i915-unordered00:05:209
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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