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2026-07-12 - 01:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Jul 11, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2529768995180,517cyclictest0-21swapper/420:37:2610
252980999516515,1cyclictest2564223-21kworker/14:1+i915-unordered19:48:266
252977299503501,2cyclictest2680818-21kworker/5:0+i915-unordered22:02:2611
252977299503501,2cyclictest2680818-21kworker/5:0+i915-unordered22:02:2611
2529765995000,499cyclictest0-21swapper/323:02:269
252978199498496,2cyclictest2702525-21kworker/7:1+i915-unordered22:48:2613
252980599492491,1cyclictest0-21swapper/1322:02:265
252980599492491,1cyclictest0-21swapper/1322:02:265
252981499488458,30cyclictest0-21swapper/1522:48:267
252978199481450,31cyclictest0-21swapper/719:58:2613
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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