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2026-02-25 - 17:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Wed Feb 25, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1003591995505,44cyclictest0-21swapper/1021:51:262
10035919952237,484cyclictest115-21ksoftirqd/1022:55:262
1003566995205,514cyclictest0-21swapper/320:03:269
10035689951113,498cyclictest0-21swapper/400:18:2510
10035539950046,453cyclictest171ktimers/000:30:250
1003557994992,496cyclictest0-21swapper/123:03:251
1003557994992,496cyclictest0-21swapper/123:03:251
1003568994959,485cyclictest0-21swapper/419:48:2610
100355799492491,1cyclictest987120-21kworker/1:0+i915-unordered19:18:261
100356699490490,0cyclictest0-21swapper/319:45:269
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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