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2026-05-05 - 09:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue May 05, 2026 00:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
386492499410410,0cyclictest0-21swapper/1320:13:565
386491999402401,1cyclictest0-21swapper/1221:57:184
386489499401398,2cyclictest3835007-21kworker/u64:2+events_unbound20:13:5612
38637992400392,5sleep50-21swapper/519:04:1711
38637992400392,5sleep50-21swapper/519:04:1711
386491999398395,2cyclictest4094347-21latency_hist23:18:324
386491999396395,1cyclictest0-21swapper/1223:34:314
386491999396395,1cyclictest0-21swapper/1223:12:404
386491999396395,1cyclictest0-21swapper/1222:53:074
386491999396395,1cyclictest0-21swapper/1222:37:554
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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