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2026-03-07 - 17:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Mar 07, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4919449956116,44cyclictest0-21swapper/419:57:0710
491936995350,533cyclictest0-21swapper/221:43:078
49198699521519,2cyclictest668636-21kworker/14:1+i915-unordered22:50:076
4919499952136,485cyclictest0-21swapper/500:10:0711
4919639951514,500cyclictest0-21swapper/921:12:0715
49197899512511,1cyclictest564261-21kworker/12:5+i915-unordered22:20:074
49197899511511,0cyclictest655827-21kworker/12:4+i915-unordered23:03:074
4919839950517,487cyclictest0-21swapper/1321:32:075
491986995033,499cyclictest0-21swapper/1400:16:076
4919869950116,484cyclictest0-21swapper/1421:17:076
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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