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2026-08-02 - 09:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sun Aug 02, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
347665699727311,415cyclictest0-21swapper/519:16:4511
34766519956312,548cyclictest0-21swapper/419:32:4510
347668599517515,2cyclictest3666232-21kworker/12:0+i915-unordered23:01:444
3476693995139,0cyclictest1491rcuc/1423:14:446
3476693995139,0cyclictest1491rcuc/1423:14:446
34766629950169,431cyclictest0-21swapper/720:26:4513
34766629950169,431cyclictest0-21swapper/720:26:4513
347668099492491,1cyclictest0-21swapper/1122:29:443
347665899492492,0cyclictest0-21swapper/621:21:4512
347665899490490,0cyclictest3650406-21kworker/6:0+i915-unordered23:14:4412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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