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2026-05-01 - 07:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Fri May 01, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27379199542541,1cyclictest447614-21kworker/2:2+i915-unordered22:42:398
2738449949512,482cyclictest0-21swapper/1519:11:397
2737829948912,476cyclictest0-21swapper/022:42:390
27380699482481,1cyclictest294639-21kworker/6:0+i915-unordered19:34:3912
27380699482481,1cyclictest294639-21kworker/6:0+i915-unordered19:34:3912
2738219947619,59cyclictest0-21swapper/1019:16:012
2738389947427,446cyclictest142-21ksoftirqd/1321:45:395
2738289947123,447cyclictest124-21ksoftirqd/1123:51:393
2737829946316,29cyclictest0-21swapper/019:55:220
2738449946210,60cyclictest160-21ksoftirqd/1519:37:397
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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