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2025-10-20 - 16:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Mon Oct 20, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
301316499725307,417cyclictest0-21swapper/019:49:490
301317399721720,1cyclictest0-21swapper/223:55:328
3013226995364,44cyclictest0-21swapper/1522:43:497
30132269953415,29cyclictest0-21swapper/1500:34:497
301318499527525,2cyclictest3065955-21kworker/5:1+i915-unordered20:13:4911
30132199951710,506cyclictest0-21swapper/1320:41:495
30131689950415,489cyclictest0-21swapper/121:38:491
301319899503502,1cyclictest0-21swapper/923:03:4915
301318499499498,1cyclictest3074670-21kworker/5:2+i915-unordered20:16:4911
301318499499498,1cyclictest0-21swapper/520:01:4911
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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