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2026-07-27 - 06:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Mon Jul 27, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2816067995540,553cyclictest0-21swapper/321:02:569
2816070995255,518cyclictest0-21swapper/423:02:5610
2816070994780,477cyclictest0-21swapper/419:43:5610
28160839947226,445cyclictest0-21swapper/720:33:5613
28160899946722,29cyclictest0-21swapper/919:16:2015
28160709946721,30cyclictest0-21swapper/421:48:5610
28160709946721,30cyclictest0-21swapper/421:48:5610
28160839946625,29cyclictest0-21swapper/720:59:5613
28160839946622,29cyclictest0-21swapper/722:29:5613
28161179946522,29cyclictest0-21swapper/1522:32:567
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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