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2026-04-25 - 04:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Apr 25, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1755969955532,522cyclictest0-21swapper/1400:24:506
1755459951526,488cyclictest0-21swapper/222:51:508
17557399509508,1cyclictest236632-21kworker/9:2+i915-unordered20:26:5015
1755459950538,466cyclictest0-21swapper/219:19:508
1755459950538,466cyclictest0-21swapper/219:19:508
17557399492491,1cyclictest0-21swapper/921:06:5015
1755389948913,475cyclictest0-21swapper/022:01:500
1755389948913,475cyclictest0-21swapper/022:01:500
175583994847,58cyclictest0-21swapper/1120:10:133
17555999482482,0cyclictest0-21swapper/519:52:5011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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