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2026-01-30 - 11:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Fri Jan 30, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10658289956543,521cyclictest0-21swapper/319:45:319
10658439955432,521cyclictest0-21swapper/700:17:3013
10658309951930,488cyclictest61-21ksoftirqd/422:02:3010
106583099511509,1cyclictest1235981-21kworker/4:1+i915-unordered22:39:3010
10658309949836,461cyclictest0-21swapper/400:17:3010
10658309949715,29cyclictest0-21swapper/420:05:3110
106583099492491,1cyclictest1214986-21kworker/4:0+i915-unordered22:24:3010
106583099492490,2cyclictest1227446-21kworker/4:2+i915-unordered22:19:3010
106583099491490,1cyclictest1172592-21kworker/4:0+i915-unordered21:22:3110
106583099491489,2cyclictest972989-21kworker/4:3+i915-unordered19:27:3110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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