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2026-02-18 - 17:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Wed Feb 18, 2026 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1174921995669,43cyclictest0-21swapper/520:07:3911
1174949995638,43cyclictest0-21swapper/1200:31:384
11749219952914,513cyclictest0-21swapper/523:21:3811
11749259952815,512cyclictest0-21swapper/600:23:3812
1174921995217,0cyclictest0-21swapper/520:13:3911
1174962995142,0cyclictest0-21swapper/1519:35:397
1174962995142,0cyclictest0-21swapper/1519:35:397
11749299951313,499cyclictest0-21swapper/719:28:3913
11749299951313,499cyclictest0-21swapper/719:28:3913
117492199512510,2cyclictest1356433-21kworker/5:0+i915-unordered23:03:3811
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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