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2026-09-05 - 05:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Sep 05, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3487396995897,579cyclictest0-21swapper/1521:05:407
3487396995897,579cyclictest0-21swapper/1521:05:407
34873689958317,45cyclictest0-21swapper/921:56:4015
34873379953816,521cyclictest0-21swapper/119:26:401
348734999524523,1cyclictest0-21swapper/422:25:4010
348738399523522,1cyclictest3648806-21kworker/12:0+i915-unordered22:25:404
348733799508507,1cyclictest3624810-21kworker/1:1+i915-unordered21:56:401
348737899499468,31cyclictest0-21swapper/1121:42:403
348737299497495,2cyclictest3503993-21kworker/10:0+i915-unordered19:35:402
34873879949518,59cyclictest0-21swapper/1320:15:255
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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