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2026-09-02 - 03:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Wed Sep 02, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
310799899712293,418cyclictest0-21swapper/219:12:468
3108015996037,28cyclictest0-21swapper/700:25:4613
31080429960222,578cyclictest0-21swapper/1321:07:465
31080139953532,503cyclictest0-21swapper/620:46:4612
310804599509508,1cyclictest3290932-21kworker/14:2+i915-unordered23:28:466
310802699508507,1cyclictest3221599-21kworker/10:2+i915-unordered21:27:462
310802699508507,1cyclictest3221599-21kworker/10:2+i915-unordered21:27:462
310799499506504,2cyclictest0-21swapper/122:22:461
310802699499469,30cyclictest0-21swapper/1020:38:462
31080239948414,59cyclictest0-21swapper/923:46:4615
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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