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2026-07-05 - 23:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sun Jul 05, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14055439955533,521cyclictest0-21swapper/1220:38:374
1405529995220,521cyclictest0-21swapper/900:22:3715
140552199519517,2cyclictest1656223-21kworker/7:0+i915-unordered23:47:3713
140550599504502,2cyclictest0-21swapper/323:32:379
140554399502472,30cyclictest0-21swapper/1221:37:374
140551099500499,1cyclictest1487805-21kworker/4:2+i915-unordered20:38:3710
1405514994965,490cyclictest0-21swapper/500:35:3711
140552999491489,2cyclictest0-21swapper/922:20:3715
140552999491489,2cyclictest0-21swapper/922:20:3715
140550599491489,2cyclictest1553036-21kworker/3:2+i915-unordered21:58:379
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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