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2026-01-05 - 04:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Mon Jan 05, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41927749944422,30cyclictest0-21swapper/620:08:5812
41927599943916,30cyclictest0-21swapper/222:58:168
41927599943914,30cyclictest0-21swapper/219:25:178
419279899427426,1cyclictest4098986-21kworker/12:0+events19:19:424
4192770994200,29cyclictest0-21swapper/521:16:5711
41928119941921,397cyclictest0-21swapper/1522:58:027
41928079941821,396cyclictest0-21swapper/1423:34:056
41928079941618,397cyclictest0-21swapper/1421:33:406
41928079941618,397cyclictest0-21swapper/1421:33:406
41928039941616,399cyclictest0-21swapper/1319:34:415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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