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2026-08-23 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sun Aug 23, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
292039799545544,1cyclictest3041600-21kworker/4:0+i915-unordered21:33:0510
29203899953814,523cyclictest0-21swapper/221:26:058
29204309952736,490cyclictest0-21swapper/1222:31:054
29203839952720,29cyclictest0-21swapper/022:24:050
292038599514513,1cyclictest3069846-21kworker/1:1+i915-unordered22:24:051
29203939951221,491cyclictest0-21swapper/322:01:059
292039399504474,30cyclictest0-21swapper/320:14:059
29204269950212,489cyclictest0-21swapper/1119:34:053
292041899498496,1cyclictest3026477-21kworker/10:0+i915-unordered21:26:052
2920389994967,488cyclictest0-21swapper/221:34:058
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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