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2025-09-17 - 17:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Wed Sep 17, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36340649953412,521cyclictest0-21swapper/1021:25:522
3634068995265,520cyclictest0-21swapper/1123:18:523
36340689950820,488cyclictest0-21swapper/1123:04:523
36340349949851,29cyclictest0-21swapper/319:56:359
363403099496495,1cyclictest0-21swapper/220:20:358
363407399486485,1cyclictest0-21swapper/1221:13:524
363407399485484,1cyclictest3716834-21kworker/12:0+i915-unordered20:49:524
363402599465464,1cyclictest3873943-21kworker/1:2+i915-unordered00:17:521
36340499946419,30cyclictest0-21swapper/721:31:4713
3634045994643,461cyclictest0-21swapper/621:25:5212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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