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2026-08-14 - 12:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Fri Aug 14, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28618559955837,520cyclictest0-21swapper/322:19:229
286184799540538,2cyclictest2954878-21kworker/1:1+i915-unordered21:07:221
28618979952131,489cyclictest0-21swapper/1320:24:225
28618479950218,483cyclictest0-21swapper/121:19:221
28618559949926,58cyclictest0-21swapper/321:23:229
2861847994954,490cyclictest0-21swapper/122:01:221
28618429949414,479cyclictest0-21swapper/021:07:220
286187699488486,2cyclictest0-21swapper/923:34:2215
2861842994830,23cyclictest0-21swapper/022:01:220
28618629948012,467cyclictest0-21swapper/522:36:2211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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