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2026-02-02 - 11:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Mon Feb 02, 2026 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
830340995736,45cyclictest0-21swapper/000:22:250
8303979954243,498cyclictest0-21swapper/1423:55:256
830397995173,0cyclictest0-21swapper/1420:31:256
830340995068,497cyclictest16-21ksoftirqd/000:00:250
830397994889,478cyclictest0-21swapper/1400:22:256
83037099487486,1cyclictest1087363-21kworker/8:0+i915-unordered00:22:2514
8303599948326,59cyclictest0-21swapper/520:27:4711
8303599948326,59cyclictest0-21swapper/520:27:4711
83040299475445,30cyclictest0-21swapper/1521:52:257
8303919947026,29cyclictest0-21swapper/1200:34:254
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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