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2026-05-27 - 15:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Wed May 27, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3896066995311,527cyclictest0-21swapper/023:04:510
3896123995131,44cyclictest0-21swapper/1421:10:516
3896066995058,496cyclictest0-21swapper/023:24:510
389610799504473,31cyclictest0-21swapper/1019:58:512
389610799503502,0cyclictest3953229-21kworker/10:2+i915-unordered20:28:512
389608999489487,2cyclictest3961283-21kworker/6:2+i915-unordered20:43:5112
38960699947413,460cyclictest0-21swapper/121:10:511
3896078994620,3cyclictest0-21swapper/320:49:339
3896082994617,58cyclictest0-21swapper/419:54:1410
3896082994592,59cyclictest0-21swapper/421:32:1310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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