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2026-03-10 - 21:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Mar 10, 2026 00:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
535177995409,530cyclictest0-21swapper/122:06:021
5352259953940,498cyclictest0-21swapper/1200:33:014
5352299953030,499cyclictest0-21swapper/1320:35:025
535213995270,28cyclictest0-21swapper/1023:10:352
53520799523522,1cyclictest685505-21kworker/9:4+i915-unordered22:06:0215
535200995182,515cyclictest0-21swapper/720:25:0213
5352259951011,498cyclictest0-21swapper/1200:05:014
535200995045,498cyclictest0-21swapper/721:51:0213
5352209950120,42cyclictest0-21swapper/1121:31:023
53518099498493,4cyclictest742589-21kworker/2:0+i915-unordered23:10:358
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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