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2026-02-14 - 15:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Feb 14, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12756839953739,497cyclictest0-21swapper/1221:11:464
1275645995055,498cyclictest0-21swapper/323:41:469
127569099485485,0cyclictest0-21swapper/1419:11:466
127568399478478,0cyclictest0-21swapper/1221:56:464
127567899476475,1cyclictest1481307-21kworker/11:0+i915-unordered23:41:463
12756339947334,0cyclictest0-21swapper/020:11:460
127567899469468,1cyclictest0-21swapper/1121:22:463
12756569946617,29cyclictest0-21swapper/623:48:2912
12756379946624,30cyclictest0-21swapper/121:53:461
127569099463462,1cyclictest1288287-21kworker/14:0+i915-unordered19:22:466
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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