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2026-06-11 - 20:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Thu Jun 11, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36824319957410,27cyclictest0-21swapper/1420:54:236
368239899509508,1cyclictest3767544-21kworker/6:1+i915-unordered20:54:2312
368242299505504,1cyclictest3896236-21kworker/12:2+i915-unordered23:56:234
36823779949523,58cyclictest0-21swapper/121:03:231
368237799485484,1cyclictest3703267-21kworker/1:3+i915-unordered19:40:231
368238999484454,30cyclictest0-21swapper/423:56:2310
368239899481481,0cyclictest3831821-21kworker/6:0+i915-unordered22:11:2312
36824089947426,28cyclictest0-21swapper/922:14:4515
36824009946913,58cyclictest0-21swapper/723:39:0713
3682418994650,56cyclictest0-21swapper/1121:26:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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