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2026-06-20 - 21:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Jun 20, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41768769954523,521cyclictest0-21swapper/1422:59:066
4176834995043,500cyclictest0-21swapper/400:21:0610
417683799499498,1cyclictest164743-21kworker/5:0+i915-unordered23:03:0611
417681899495463,31cyclictest0-21swapper/000:00:060
417683199494493,1cyclictest0-21swapper/319:08:069
417686399492491,1cyclictest4127028-21kworker/11:3+i915-unordered19:08:063
417687399488486,1cyclictest59985-21kworker/13:0+i915-unordered20:54:065
417683799488457,31cyclictest0-21swapper/520:54:0611
417683799484483,1cyclictest112447-21kworker/5:2+i915-unordered21:49:0611
417685099483481,2cyclictest221000-21kworker/8:1+i915-unordered00:00:0614
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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