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2026-08-11 - 11:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Aug 11, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2929594995563,552cyclictest0-21swapper/022:56:280
292962599549548,1cyclictest3091088-21kworker/8:0+i915-unordered22:56:2814
29296109954119,521cyclictest0-21swapper/422:38:2810
29296379953921,517cyclictest124-21ksoftirqd/1120:08:283
29296109953816,521cyclictest0-21swapper/423:26:2710
29296379952712,514cyclictest0-21swapper/1120:58:283
2929631995255,519cyclictest115-21ksoftirqd/1020:57:282
2929637995190,0cyclictest0-21swapper/1123:29:273
29296109951610,505cyclictest0-21swapper/400:26:2710
29296319951313,499cyclictest0-21swapper/1000:08:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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