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2026-01-26 - 05:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Mon Jan 26, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7133679949212,28cyclictest79-21ksoftirqd/622:42:3812
7133679944815,30cyclictest0-21swapper/622:16:5912
7133679944721,29cyclictest0-21swapper/622:10:3812
7133489944621,30cyclictest0-21swapper/120:43:331
7133959944520,422cyclictest0-21swapper/1200:25:384
7133679944418,30cyclictest0-21swapper/619:29:0212
7133909944126,414cyclictest0-21swapper/1122:19:383
7133979944013,30cyclictest0-21swapper/1320:27:385
7133959944010,30cyclictest0-21swapper/1221:34:014
7133789944018,419cyclictest0-21swapper/921:59:0115
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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