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2026-02-15 - 16:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sun Feb 15, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1262245995333,528cyclictest0-21swapper/322:45:449
12622609953233,498cyclictest0-21swapper/719:12:4413
12622549951314,498cyclictest0-21swapper/500:17:4411
1262235994980,497cyclictest0-21swapper/019:23:440
1262235994980,497cyclictest0-21swapper/019:23:440
1262235994879,477cyclictest0-21swapper/021:30:440
12622919947117,60cyclictest0-21swapper/1419:55:086
126229199456455,1cyclictest0-21swapper/1419:10:446
126224199455455,0cyclictest0-21swapper/221:25:448
12622649945128,29cyclictest0-21swapper/819:38:2914
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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