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2026-02-28 - 17:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Feb 28, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9107139955916,29cyclictest0-21swapper/222:57:208
9107139954322,520cyclictest0-21swapper/220:35:208
910732995330,28cyclictest0-21swapper/721:55:2013
91073299518517,1cyclictest979842-21kworker/7:2+i915-unordered20:32:2013
9107219951717,499cyclictest0-21swapper/422:42:2010
9107689951617,498cyclictest0-21swapper/1521:03:207
91074599496495,1cyclictest1068464-21kworker/10:1+i915-unordered22:57:202
910750994917,483cyclictest0-21swapper/1122:32:203
910750994917,483cyclictest0-21swapper/1122:32:203
9107139948923,466cyclictest0-21swapper/219:58:208
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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