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2026-09-08 - 05:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Sep 08, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36618579956512,551cyclictest0-21swapper/622:41:3412
3661869995647,27cyclictest0-21swapper/919:07:3515
36618469953965,473cyclictest0-21swapper/323:55:349
36618509953516,518cyclictest0-21swapper/423:58:3410
3661857995286,521cyclictest0-21swapper/619:30:3512
366183899524523,1cyclictest3618799-21kworker/1:6+i915-unordered19:07:351
366189299522521,1cyclictest3710880-21kworker/14:0+i915-unordered20:16:346
3661857995210,520cyclictest0-21swapper/620:53:3412
366187199517515,1cyclictest3779986-21kworker/10:1+i915-unordered21:32:342
366184199516515,1cyclictest0-21swapper/221:32:348
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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