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2026-04-08 - 00:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Apr 07, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41214899953738,498cyclictest0-21swapper/922:27:2315
412148199513512,1cyclictest4154263-21kworker/7:2+i915-unordered19:55:2313
412151599507506,1cyclictest0-21swapper/1519:55:237
4121489995020,501cyclictest0-21swapper/919:31:2315
412151599491491,0cyclictest149470-21kworker/15:1+i915-unordered23:53:237
41214949948517,29cyclictest0-21swapper/1019:57:232
41214789948325,60cyclictest0-21swapper/619:14:0712
4121494994740,473cyclictest0-21swapper/1023:45:232
41214949947317,453cyclictest0-21swapper/1022:27:232
412146699472470,2cyclictest0-21swapper/319:11:239
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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