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2026-07-09 - 00:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Wed Jul 08, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19775869958821,44cyclictest0-21swapper/1422:58:316
19775769953893,444cyclictest2074948-21kworker/11:2+i915-unordered21:19:323
19775769952317,44cyclictest0-21swapper/1100:30:313
197753499517516,1cyclictest1959839-21kworker/1:1+i915-unordered19:22:321
197757999506504,1cyclictest2234419-21kworker/12:2+i915-unordered00:30:314
197756899501500,1cyclictest2164691-21kworker/10:0+i915-unordered22:57:312
19775459949316,59cyclictest0-21swapper/423:55:1710
19775769948320,462cyclictest0-21swapper/1121:24:323
197756399479479,0cyclictest0-21swapper/923:17:3115
197758699477476,1cyclictest0-21swapper/1423:07:316
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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