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2026-08-08 - 10:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Aug 08, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
329100599695299,395cyclictest0-21swapper/122:43:331
32910289957035,0cyclictest0-21swapper/722:33:3313
329105799548547,1cyclictest3464725-21kworker/14:2+i915-unordered22:44:336
329102399508506,2cyclictest0-21swapper/619:36:3312
329102399506504,2cyclictest0-21swapper/622:44:3312
329106199486485,0cyclictest3452448-21kworker/15:0+i915-unordered22:39:337
32910189947427,28cyclictest0-21swapper/423:07:5410
32910189947427,28cyclictest0-21swapper/423:07:5410
3291051994693,465cyclictest0-21swapper/1221:22:334
32910059946923,29cyclictest0-21swapper/123:01:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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