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2026-05-02 - 07:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat May 02, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20105499551550,1cyclictest282147-21kworker/6:2+i915-unordered20:50:3712
2010349954622,520cyclictest0-21swapper/121:30:371
20105499540510,30cyclictest0-21swapper/623:06:3712
201085995320,528cyclictest0-21swapper/1319:15:375
20106599517515,2cyclictest0-21swapper/922:06:3715
20104299498497,1cyclictest278263-21kworker/3:2+i915-unordered21:16:379
201038994939,483cyclictest0-21swapper/221:47:378
2010349949215,60cyclictest0-21swapper/120:06:221
201076994910,490cyclictest0-21swapper/1123:32:373
20103299489430,30cyclictest0-21swapper/023:54:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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