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2026-06-05 - 19:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Fri Jun 05, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4114759995371,535cyclictest0-21swapper/221:04:348
411479299535534,1cyclictest14177-21kworker/10:0+i915-unordered21:04:342
41147519951676,29cyclictest171ktimers/023:23:550
411480599498498,0cyclictest70560-21kworker/13:0+i915-unordered22:23:345
411480599498498,0cyclictest70560-21kworker/13:0+i915-unordered22:23:345
411477899486484,2cyclictest78322-21kworker/7:0+i915-unordered22:21:3413
4114813994814,58cyclictest0-21swapper/1522:10:197
4114797994791,477cyclictest0-21swapper/1121:46:343
41148059947022,30cyclictest0-21swapper/1323:16:555
41147519946316,29cyclictest0-21swapper/021:42:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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