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2026-09-17 - 10:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Thu Sep 17, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39325969955013,536cyclictest0-21swapper/020:18:170
393264899532530,2cyclictest3949286-21kworker/13:2+i915-unordered19:33:185
393265399521491,30cyclictest0-21swapper/1500:18:177
393261099503502,1cyclictest4122441-21kworker/4:0+i915-unordered23:00:1710
393261099503502,1cyclictest4122441-21kworker/4:0+i915-unordered23:00:1710
3932602995030,502cyclictest0-21swapper/223:18:178
393263199501501,0cyclictest4138428-21kworker/10:1+i915-unordered23:18:172
393264399496495,1cyclictest3993663-21kworker/12:0+i915-unordered20:37:174
393261799491434,28cyclictest0-21swapper/622:40:1712
393264899488487,1cyclictest0-21swapper/1323:56:175
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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