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2026-05-14 - 12:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Thu May 14, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38551479952725,501cyclictest0-21swapper/723:37:1513
38551479952525,499cyclictest0-21swapper/723:55:1513
3855171995066,498cyclictest0-21swapper/1222:26:154
385514099471471,0cyclictest3880028-21kworker/5:0+i915-unordered19:41:1511
385512899465464,1cyclictest0-21swapper/222:09:158
385512899465464,1cyclictest0-21swapper/222:09:158
3855161994637,59cyclictest0-21swapper/1020:09:382
385513799462461,1cyclictest3956530-21kworker/4:2+i915-unordered22:26:1510
38551289946111,58cyclictest0-21swapper/221:55:158
385518399458457,1cyclictest4085242-21kworker/15:0+i915-unordered23:55:157
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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