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2026-06-08 - 19:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Mon Jun 08, 2026 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41325399956411,552cyclictest0-21swapper/1420:16:286
41324889954017,521cyclictest0-21swapper/220:40:288
41325399953111,519cyclictest151-21ksoftirqd/1420:49:286
413250399524523,1cyclictest4173357-21kworker/6:2+i915-unordered20:16:2812
4132531995220,521cyclictest0-21swapper/1221:00:284
413249999514513,1cyclictest100184-21kworker/5:1+i915-unordered22:54:2811
413249999514513,1cyclictest100184-21kworker/5:1+i915-unordered22:54:2811
413249999510480,30cyclictest0-21swapper/522:59:2811
413250799506503,3cyclictest177479-21kworker/7:0+i915-unordered00:08:2813
41324999950412,490cyclictest0-21swapper/520:38:2811
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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