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2026-03-24 - 22:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Mar 24, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39435219953522,512cyclictest0-21swapper/1200:18:484
39435349952827,500cyclictest0-21swapper/1521:52:487
394352699503502,1cyclictest0-21swapper/1321:51:485
394352199495495,0cyclictest3968350-21kworker/12:2+i915-unordered19:43:484
394352699492460,32cyclictest0-21swapper/1323:12:485
39434789948434,449cyclictest0-21swapper/122:36:481
394350199472471,1cyclictest3942884-21kworker/7:1+i915-unordered21:52:4813
3943493994627,58cyclictest0-21swapper/519:15:1011
3943521994566,59cyclictest0-21swapper/1219:13:484
39434939945528,29cyclictest0-21swapper/523:06:1111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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