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2026-03-17 - 22:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Mar 17, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
91455399707310,396cyclictest0-21swapper/720:02:4913
9145619956116,543cyclictest0-21swapper/923:12:4915
914564995290,526cyclictest0-21swapper/1021:34:492
914564995250,26cyclictest0-21swapper/1021:45:492
9145539951311,501cyclictest0-21swapper/700:19:0913
9145469950724,482cyclictest0-21swapper/523:28:0511
91456999489487,2cyclictest1046008-21kworker/11:0+i915-unordered22:01:493
914569994861,44cyclictest0-21swapper/1120:27:063
91456999485483,2cyclictest1130748-21kworker/11:2+i915-unordered23:24:493
91455099481481,0cyclictest0-21swapper/620:25:4912
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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