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2026-01-19 - 05:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Mon Jan 19, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6371399519518,1cyclictest102846-21kworker/2:0+i915-unordered19:52:518
637049950723,45cyclictest0-21swapper/020:55:510
6371399506505,1cyclictest141842-21kworker/2:2+i915-unordered20:55:518
63704994961,59cyclictest0-21swapper/019:30:510
6371399494493,0cyclictest285071-21kworker/2:1+i915-unordered23:34:518
63704994907,28cyclictest0-21swapper/023:37:510
637049948619,27cyclictest0-21swapper/023:40:510
637369947526,58cyclictest0-21swapper/822:05:3514
637369947424,58cyclictest0-21swapper/823:20:3314
6376699469466,2cyclictest0-21swapper/1523:30:517
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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