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2026-08-28 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Fri Aug 28, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28619099956610,43cyclictest0-21swapper/020:55:550
28619099956610,43cyclictest0-21swapper/020:55:550
2861931995531,551cyclictest0-21swapper/623:53:5512
28619429955215,536cyclictest0-21swapper/921:20:5515
2861931995505,544cyclictest0-21swapper/623:47:5512
2861931995505,544cyclictest0-21swapper/623:47:5512
28619319952132,488cyclictest0-21swapper/600:13:5512
286191399520519,1cyclictest2914884-21kworker/1:2+i915-unordered20:10:561
2861942994999,489cyclictest0-21swapper/921:27:5515
28619679949418,58cyclictest0-21swapper/1500:15:397
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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