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2026-07-15 - 01:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Wed Jul 15, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26804629955736,520cyclictest0-21swapper/519:59:1911
26804859952924,44cyclictest0-21swapper/1119:59:193
268046699523522,1cyclictest3704729-21kworker/6:0+i915-unordered19:18:1912
2680503995065,499cyclictest0-21swapper/1500:32:187
2680503995065,499cyclictest0-21swapper/1500:32:187
26804609950033,466cyclictest0-21swapper/419:08:1910
26804609950033,466cyclictest0-21swapper/419:08:1910
26804859947710,28cyclictest0-21swapper/1122:54:183
268044399476446,30cyclictest0-21swapper/021:37:180
2680477994741,59cyclictest0-21swapper/920:08:1815
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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