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2026-01-23 - 19:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Fri Jan 23, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6738819947420,58cyclictest0-21swapper/1221:44:284
6738819946522,29cyclictest0-21swapper/1221:34:254
67383999462431,31cyclictest0-21swapper/221:39:438
6738779946114,30cyclictest0-21swapper/1122:45:053
6738699946113,30cyclictest0-21swapper/1021:39:052
6738699945325,29cyclictest0-21swapper/1022:25:072
67385199453451,2cyclictest0-21swapper/500:26:4311
67388699452450,2cyclictest937571-21kworker/13:1+i915-unordered00:26:435
6738699945026,29cyclictest0-21swapper/1019:46:442
6738819944922,30cyclictest0-21swapper/1220:19:054
6738819944922,30cyclictest0-21swapper/1220:19:054
6738819944922,29cyclictest0-21swapper/1221:16:074
6738699944925,29cyclictest0-21swapper/1021:34:432
6738329944922,423cyclictest0-21swapper/022:24:280
6738819944822,29cyclictest0-21swapper/1200:30:264
6738589944823,29cyclictest0-21swapper/722:15:4313
67383999448446,2cyclictest793171-21kworker/2:1+i915-unordered21:37:438
6738819944621,29cyclictest0-21swapper/1200:12:064
6738369944620,424cyclictest0-21swapper/123:01:431
6738369944620,424cyclictest0-21swapper/123:01:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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