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2026-01-02 - 02:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Fri Jan 02, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
354759699468410,28cyclictest0-21swapper/323:34:059
3547620994597,58cyclictest0-21swapper/1000:31:222
35476109944823,30cyclictest3597169-21cat20:04:4713
35476209944525,30cyclictest0-21swapper/1000:22:012
35476109944521,30cyclictest0-21swapper/719:46:2213
35476109944521,30cyclictest0-21swapper/719:46:2213
35476409942323,399cyclictest0-21swapper/1420:43:216
3547640994210,28cyclictest0-21swapper/1400:27:226
35476069941923,395cyclictest0-21swapper/621:50:2212
3547625994188,409cyclictest2879527-21iostat22:16:453
35476179941616,396cyclictest0-21swapper/923:39:4515
35476209941415,398cyclictest0-21swapper/1023:45:442
35476259941215,396cyclictest0-21swapper/1120:57:523
35476069941218,393cyclictest0-21swapper/621:01:0612
354760099411410,1cyclictest0-21swapper/423:53:2210
35476319941010,399cyclictest0-21swapper/1220:45:084
35476179940915,0cyclictest0-21swapper/900:10:5615
3547631994089,398cyclictest0-21swapper/1200:05:124
35476159940815,392cyclictest0-21swapper/820:18:1514
3547631994078,398cyclictest0-21swapper/1220:35:474
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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