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2026-02-13 - 21:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Fri Feb 13, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10148559955228,523cyclictest0-21swapper/622:36:4812
1014841995298,520cyclictest0-21swapper/221:26:488
101485599515513,2cyclictest1236771-21kworker/6:2+i915-unordered23:46:4712
10148379951011,498cyclictest0-21swapper/120:01:481
101483799507506,1cyclictest1091851-21kworker/1:0+i915-unordered20:45:481
101483799498497,1cyclictest1071861-21kworker/1:0+i915-unordered20:18:481
101486699491491,0cyclictest1051660-21kworker/9:1+i915-unordered20:01:4815
101488399487485,2cyclictest1019665-21kworker/12:0+i915-unordered19:45:484
101485299487486,1cyclictest0-21swapper/500:23:4711
101488999484482,2cyclictest1180478-21kworker/14:2+i915-unordered22:36:486
1014849994846,58cyclictest0-21swapper/421:25:1010
1014860994762,29cyclictest0-21swapper/721:00:4813
10148499947526,28cyclictest0-21swapper/421:32:1010
101483799475473,2cyclictest0-21swapper/122:07:481
101483799475473,2cyclictest0-21swapper/122:07:481
10148899947125,28cyclictest0-21swapper/1423:35:326
1014841994690,468cyclictest0-21swapper/222:05:488
1014841994690,468cyclictest0-21swapper/222:05:488
10148609946720,29cyclictest0-21swapper/721:57:1013
10148609946718,30cyclictest0-21swapper/721:39:3313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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