You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-19 - 00:53
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Tue Nov 18, 2025 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
209745099737318,419cyclictest0-21swapper/219:57:548
2097450995791,42cyclictest0-21swapper/221:42:548
20974509953841,496cyclictest0-21swapper/219:36:548
2097462995116,504cyclictest0-21swapper/521:32:5411
209746299510508,2cyclictest0-21swapper/520:28:5411
2097454994783,474cyclictest0-21swapper/300:18:549
20974509947526,29cyclictest0-21swapper/222:11:378
20974929947425,29cyclictest0-21swapper/1220:20:184
2097454994740,473cyclictest0-21swapper/323:25:549
20974509947226,29cyclictest0-21swapper/221:21:168
209748999470470,0cyclictest77250irq/159-i91500:18:543
20974929946923,28cyclictest0-21swapper/1220:25:154
20974769946919,29cyclictest0-21swapper/923:48:3915
20974929946718,30cyclictest0-21swapper/1221:07:364
20974929946618,30cyclictest0-21swapper/1223:30:414
20974929946618,30cyclictest0-21swapper/1222:58:164
20974929946617,30cyclictest0-21swapper/1222:52:374
209748999466466,0cyclictest77250irq/159-i91523:25:543
20974929946518,29cyclictest0-21swapper/1200:18:154
20974929946517,30cyclictest0-21swapper/1200:08:154
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional