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2026-03-16 - 06:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Mon Mar 16, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100492699698298,398cyclictest0-21swapper/023:43:130
1004934995475,540cyclictest0-21swapper/221:30:518
10049419947519,453cyclictest0-21swapper/421:11:5110
10049389946916,58cyclictest0-21swapper/321:54:519
100496799465435,30cyclictest0-21swapper/1021:01:302
10049419945632,424cyclictest0-21swapper/423:44:5010
10049299945326,29cyclictest0-21swapper/123:19:121
10049299945326,29cyclictest0-21swapper/123:19:121
10049299945325,29cyclictest0-21swapper/123:47:171
1004926994511,59cyclictest0-21swapper/021:01:510
10049299944821,30cyclictest0-21swapper/121:11:121
10049419944621,30cyclictest0-21swapper/420:15:4710
10049419944621,30cyclictest0-21swapper/420:15:4710
10049419944621,30cyclictest0-21swapper/400:19:1410
10049489944520,30cyclictest0-21swapper/620:04:5112
10049269944526,29cyclictest0-21swapper/000:30:500
10049419944421,30cyclictest0-21swapper/422:46:1310
10049419944421,29cyclictest0-21swapper/421:26:1510
10049419944419,30cyclictest0-21swapper/423:05:3610
10049489944321,29cyclictest0-21swapper/620:49:5112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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