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2025-12-30 - 01:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Tue Dec 30, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31147439947922,58cyclictest0-21swapper/421:46:5010
3114750994618,59cyclictest0-21swapper/620:49:4912
31147539945024,29cyclictest0-21swapper/721:06:1213
31147439944921,29cyclictest0-21swapper/400:37:1110
31147349944921,424cyclictest0-21swapper/223:51:278
31147819944821,29cyclictest0-21swapper/1323:19:485
31147439944821,30cyclictest0-21swapper/421:21:5010
31147439944820,30cyclictest0-21swapper/422:06:4910
31147399944822,30cyclictest0-21swapper/323:20:279
31147309944822,30cyclictest0-21swapper/120:15:281
31147309944820,29cyclictest0-21swapper/121:44:491
31147819944719,30cyclictest0-21swapper/1323:09:505
31147309944719,30cyclictest0-21swapper/120:10:281
31147309944719,30cyclictest0-21swapper/120:10:281
31147309944621,29cyclictest0-21swapper/122:58:271
31147309944621,29cyclictest0-21swapper/122:58:271
31147819944519,29cyclictest0-21swapper/1322:29:515
31147439944519,29cyclictest0-21swapper/420:17:1210
31147819944416,427cyclictest0-21swapper/1321:08:495
31147439944419,29cyclictest0-21swapper/400:21:1210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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