You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-02 - 13:57
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Sun Nov 02, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6315699957335,537cyclictest0-21swapper/020:48:240
6316169955836,521cyclictest0-21swapper/1223:23:244
6316169953411,523cyclictest0-21swapper/1219:56:244
631616995210,519cyclictest0-21swapper/1220:59:244
63162699512511,1cyclictest0-21swapper/1522:53:247
6315939950918,490cyclictest0-21swapper/722:57:2413
6316169950616,489cyclictest0-21swapper/1223:33:244
631623994846,477cyclictest0-21swapper/1422:32:246
6316239948222,460cyclictest0-21swapper/1420:27:246
63157299480479,1cyclictest0-21swapper/123:27:241
631623994780,476cyclictest0-21swapper/1421:51:246
631623994780,476cyclictest0-21swapper/1421:51:246
631623994717,463cyclictest0-21swapper/1420:48:246
63159399469467,2cyclictest631243-21kworker/7:1+i915-unordered23:09:2413
6315729946626,29cyclictest0-21swapper/100:24:241
6315699946526,30cyclictest0-21swapper/022:29:240
6315939946315,30cyclictest0-21swapper/723:36:2413
6316269946213,29cyclictest0-21swapper/1500:03:087
6315699946114,445cyclictest0-21swapper/019:58:470
63159099460459,1cyclictest77250irq/159-i91520:59:2412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional