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2025-11-26 - 03:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Wed Nov 26, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
178798899698302,393cyclictest0-21swapper/623:54:0312
1787969995183,514cyclictest0-21swapper/122:54:031
178799999467466,1cyclictest1988626-21kworker/9:3+i915-unordered22:54:0315
17880029946417,28cyclictest0-21swapper/1022:35:242
1788007994558,28cyclictest1917790-21needreboot21:30:033
17880029944926,30cyclictest0-21swapper/1022:55:032
178797299447446,1cyclictest0-21swapper/220:25:038
17880029944526,418cyclictest0-21swapper/1023:32:022
17879699944522,420cyclictest0-21swapper/121:37:261
17879699944423,420cyclictest0-21swapper/122:44:251
17880029944324,418cyclictest0-21swapper/1021:21:262
17880029944323,419cyclictest0-21swapper/1021:31:272
17880029944224,418cyclictest0-21swapper/1020:26:272
17880029944223,419cyclictest0-21swapper/1022:47:252
17879699944222,419cyclictest0-21swapper/121:28:031
17880079944019,421cyclictest0-21swapper/1100:30:023
17880029944022,416cyclictest0-21swapper/1020:15:032
17879889943922,29cyclictest0-21swapper/623:25:2512
17879819943818,419cyclictest0-21swapper/420:49:0210
17879819943716,418cyclictest0-21swapper/420:50:0210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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