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2025-08-22 - 00:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5.osadl.org (updated Thu Aug 21, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318740899551550,1cyclictest3266375-21kworker/7:1+i915-unordered21:15:4413
318743199546100,445cyclictest3266409-21kworker/12:1+i915-unordered20:48:444
31874319954599,445cyclictest3378037-21kworker/12:0+i915-unordered23:10:444
31874319952134,487cyclictest0-21swapper/1200:13:444
3187431995136,45cyclictest0-21swapper/1221:15:444
31874319949922,476cyclictest0-21swapper/1222:18:444
318738999495494,1cyclictest3213699-21kworker/2:1+i915-unordered19:54:448
31874319948727,460cyclictest0-21swapper/1221:38:444
318744299483482,1cyclictest3293789-21kworker/15:0+i915-unordered21:20:447
3187431994780,0cyclictest0-21swapper/1221:20:444
318741899477476,1cyclictest0-21swapper/1019:54:442
31874319947324,29cyclictest0-21swapper/1220:31:074
31874319947025,29cyclictest0-21swapper/1220:09:284
31874319947025,29cyclictest0-21swapper/1220:09:284
3187413994671,6cyclictest0-21swapper/819:31:5614
31874249946522,30cyclictest0-21swapper/1123:28:443
3187431994640,461cyclictest0-21swapper/1219:54:444
318743699461459,2cyclictest0-21swapper/1320:11:445
318743699461459,2cyclictest0-21swapper/1320:11:445
318738699460458,2cyclictest3359461-21kworker/1:2+i915-unordered22:36:441
31874089945910,30cyclictest0-21swapper/720:11:0813
31874089945910,30cyclictest0-21swapper/720:11:0813
318743699458457,1cyclictest0-21swapper/1320:50:445
318743699457457,0cyclictest0-21swapper/1321:01:445
318739799456455,1cyclictest77250irq/159-i91523:46:4410
3187431994557,30cyclictest0-21swapper/1223:40:064
3187431994557,30cyclictest0-21swapper/1222:41:074
318743699452452,0cyclictest0-21swapper/1321:38:445
318738999451451,0cyclictest0-21swapper/223:05:298
318739799449448,1cyclictest77250irq/159-i91522:38:4410
318739799449448,1cyclictest77250irq/159-i91521:34:4410
318744299448445,3cyclictest0-21swapper/1521:15:447
3187431994480,29cyclictest0-21swapper/1223:33:294
318739799448447,1cyclictest77250irq/159-i91522:50:4410
3187424994470,26cyclictest0-21swapper/1120:19:053
3187424994470,26cyclictest0-21swapper/1120:19:053
31874089944726,421cyclictest0-21swapper/722:57:2913
31874089944726,421cyclictest0-21swapper/722:57:2913
3187408994470,27cyclictest0-21swapper/721:45:2713
3187424994460,29cyclictest0-21swapper/1119:46:443
31874319944525,418cyclictest0-21swapper/1219:45:074
318741899445443,2cyclictest3203254-21kworker/u64:7+events_unbound19:43:442
318739799445444,1cyclictest77250irq/159-i91522:58:4410
318739799445444,1cyclictest77250irq/159-i91522:58:4410
31874319944425,418cyclictest0-21swapper/1200:27:294
31873979944424,419cyclictest0-21swapper/420:48:4410
31874389944326,417cyclictest0-21swapper/1420:43:446
318741899442441,1cyclictest0-21swapper/1019:24:162
31873979944224,417cyclictest0-21swapper/420:21:4410
31873979944224,417cyclictest0-21swapper/420:21:4410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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