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2026-01-29 - 13:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5.osadl.org (updated Thu Jan 29, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
79935299545544,1cyclictest906076-21kworker/10:0+i915-unordered21:26:322
7993739953111,518cyclictest0-21swapper/1423:19:326
79933199528528,0cyclictest0-21swapper/420:32:3210
79933199528528,0cyclictest0-21swapper/420:32:3210
79936499517517,0cyclictest816982-21kworker/12:1+i915-unordered20:32:324
79936499517517,0cyclictest816982-21kworker/12:1+i915-unordered20:32:324
7993609951612,27cyclictest0-21swapper/1123:22:323
79932299514512,2cyclictest0-21swapper/221:26:328
799360995139,29cyclictest124-21ksoftirqd/1120:32:323
799360995139,29cyclictest124-21ksoftirqd/1120:32:323
799360995060,505cyclictest124-21ksoftirqd/1121:36:323
79935299498498,0cyclictest0-21swapper/1021:36:322
79932299497497,0cyclictest923133-21kworker/2:2+i915-unordered21:36:328
799360994937,485cyclictest124-21ksoftirqd/1121:27:323
79933899481479,2cyclictest990619-21kworker/6:1+i915-unordered23:19:3212
79936099478478,0cyclictest0-21swapper/1119:17:333
7993419947627,28cyclictest0-21swapper/723:20:5613
7993419947625,448cyclictest0-21swapper/700:09:1613
7993419947425,28cyclictest0-21swapper/719:57:5513
7993609947326,28cyclictest0-21swapper/1119:38:563
7993419947225,29cyclictest0-21swapper/700:03:5513
7993419947124,29cyclictest0-21swapper/721:55:3213
799378994691,468cyclictest0-21swapper/1523:59:327
79937899468467,1cyclictest0-21swapper/1523:22:327
7993469946311,28cyclictest1040607-21ntpq23:48:5314
7993149946317,30cyclictest0-21swapper/019:32:180
7993149946014,29cyclictest0-21swapper/021:33:150
7993609945811,28cyclictest0-21swapper/1119:48:193
7993789945712,30cyclictest0-21swapper/1522:47:327
799314994569,30cyclictest0-21swapper/020:01:190
79932799455454,1cyclictest69750irq/159-i91521:06:329
79932799453452,1cyclictest69750irq/159-i91519:27:339
799314994526,30cyclictest0-21swapper/021:00:160
799314994525,30cyclictest0-21swapper/021:41:160
7993419945123,30cyclictest0-21swapper/719:28:1613
799314994515,30cyclictest0-21swapper/022:51:560
799341994500,30cyclictest0-21swapper/722:30:5613
799341994500,29cyclictest0-21swapper/723:57:5513
7993419944828,418cyclictest0-21swapper/723:39:5313
7993149944824,30cyclictest0-21swapper/000:12:180
7993419944725,421cyclictest0-21swapper/722:19:5413
79936499446443,2cyclictest1019164-21kworker/u64:4+events_unbound23:52:544
7993649944622,29cyclictest0-21swapper/1222:06:324
7993509944625,420cyclictest0-21swapper/900:06:1615
7993419944524,419cyclictest0-21swapper/719:59:5413
7993419944524,419cyclictest0-21swapper/719:42:5513
7993419944524,418cyclictest0-21swapper/723:16:5413
7993419944524,418cyclictest0-21swapper/723:16:5413
7993419944523,421cyclictest0-21swapper/721:21:1613
7993419944521,30cyclictest0-21swapper/720:09:1613
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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