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2026-01-27 - 15:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot5s.osadl.org (updated Tue Jan 27, 2026 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7390462388366,14sleep40-21swapper/410
7388862363340,15sleep50-21swapper/511
7389562362339,14sleep30-21swapper/39
7390502349307,35sleep80-21swapper/814
7389452340317,14sleep100-21swapper/102
7388582337313,15sleep140-21swapper/146
7388082332308,15sleep10-21swapper/11
7387882323297,17sleep20-21swapper/28
7390342303280,15sleep90-21swapper/915
7388672303281,14sleep60-21swapper/612
7388552303280,15sleep110-21swapper/113
7388492303281,14sleep70-21swapper/713
7388372301279,14sleep120-21swapper/124
7389502300276,15sleep150-21swapper/157
7390612298276,14sleep00-21swapper/00
7388382288266,14sleep130-21swapper/135
739409995720,26cyclictest100655-21CPU13
10857372500,0sleep130-21swapper/135
73940999459,11cyclictest0-21swapper/713
73940999448,11cyclictest0-21swapper/713
73940999448,11cyclictest0-21swapper/713
73940999448,11cyclictest0-21swapper/713
73939199420,0cyclictest0-21swapper/28
739419994141,0cyclictest0-21swapper/102
739412994141,0cyclictest0-21swapper/814
739409994130,11cyclictest0-21swapper/713
73939999410,41cyclictest0-21swapper/410
73940699400,40cyclictest0-21swapper/612
739391994040,0cyclictest2247-21snmpd8
73938599400,39cyclictest0-21swapper/00
73938599400,39cyclictest0-21swapper/00
739416993837,1cyclictest0-21swapper/915
739412993838,0cyclictest0-21swapper/814
73943499370,37cyclictest0-21swapper/146
739429993636,0cyclictest0-21swapper/135
739436993529,5cyclictest2247-21snmpd7
73941999350,34cyclictest0-21swapper/102
73940999359,25cyclictest0-21swapper/713
739391993534,1cyclictest0-21swapper/28
739391993534,1cyclictest0-21swapper/28
739402993434,0cyclictest0-21swapper/511
739434993333,0cyclictest0-21swapper/146
739434993333,0cyclictest0-21swapper/146
739419993333,0cyclictest0-21swapper/102
739419993333,0cyclictest0-21swapper/102
739416993333,0cyclictest0-21swapper/915
73940999339,11cyclictest0-21swapper/713
73940999339,11cyclictest0-21swapper/713
73940999339,11cyclictest0-21swapper/713
73940999339,11cyclictest0-21swapper/713
73940999339,11cyclictest0-21swapper/713
739402993333,0cyclictest0-21swapper/511
739402993333,0cyclictest0-21swapper/511
739391993332,1cyclictest2247-21snmpd8
739385993330,2cyclictest100654-21CPU0
739426993232,0cyclictest0-21swapper/124
73941999320,0cyclictest0-21swapper/102
73940999328,11cyclictest0-21swapper/713
73940999328,11cyclictest0-21swapper/713
73940999328,11cyclictest0-21swapper/713
73940999328,11cyclictest0-21swapper/713
73940999328,11cyclictest0-21swapper/713
73940999328,11cyclictest0-21swapper/713
73940999328,11cyclictest0-21swapper/713
739409993232,0cyclictest0-21swapper/713
739409993232,0cyclictest0-21swapper/713
739385993231,1cyclictest2247-21snmpd0
73942999310,1cyclictest0-21swapper/135
739423993131,0cyclictest0-21swapper/113
739419993130,1cyclictest0-21swapper/102
739412993130,1cyclictest0-21swapper/814
73940999317,11cyclictest0-21swapper/713
73940999317,11cyclictest0-21swapper/713
73940999317,11cyclictest0-21swapper/713
73940999310,22cyclictest0-21swapper/713
73940999310,22cyclictest0-21swapper/713
739402993131,0cyclictest0-21swapper/511
739402993130,1cyclictest2247-21snmpd11
739399993131,0cyclictest0-21swapper/410
739395993110,1cyclictest0-21swapper/39
73938599310,30cyclictest0-21swapper/00
739436993027,3cyclictest2247-21snmpd7
739426993030,0cyclictest0-21swapper/124
73942699300,1cyclictest0-21swapper/124
739419993027,3cyclictest2247-21snmpd2
73940999307,11cyclictest0-21swapper/713
73940299300,1cyclictest0-21swapper/511
73940299300,1cyclictest0-21swapper/511
73939199300,29cyclictest0-21swapper/28
73943699290,29cyclictest0-21swapper/157
739423992929,0cyclictest0-21swapper/113
739423992929,0cyclictest0-21swapper/113
739419992929,0cyclictest0-21swapper/102
739416992927,1cyclictest2247-21snmpd15
73940999295,23cyclictest766028-21ntp_states13
739402992928,1cyclictest0-21swapper/511
739399992929,0cyclictest0-21swapper/410
739399992928,1cyclictest2247-21snmpd10
739395992928,1cyclictest2247-21snmpd9
739395992925,3cyclictest2247-21snmpd9
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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