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2025-11-01 - 00:20

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5s.osadl.org (updated Fri Oct 31, 2025 00:47:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23880872417358,18sleep100-21swapper/1019:05:292
23882392403375,18sleep40-21swapper/419:07:3210
23882872359302,45sleep150-21swapper/1519:08:157
23883072354302,41sleep00-21swapper/019:08:330
23881222347319,18sleep20-21swapper/219:05:528
23882302342314,18sleep120-21swapper/1219:07:244
23880912342312,19sleep140-21swapper/1419:05:336
23883922341313,18sleep80-21swapper/819:09:4514
23882972341311,19sleep70-21swapper/719:08:2313
23881082341312,19sleep60-21swapper/619:05:4112
23882992340312,18sleep90-21swapper/919:08:2615
23883562339312,17sleep110-21swapper/1119:09:163
23883232339311,18sleep130-21swapper/1319:08:465
23881602337309,18sleep10-21swapper/119:06:241
23882932335307,18sleep30-21swapper/319:08:199
23881842335307,18sleep50-21swapper/519:06:4511
2388758996010,25cyclictest0-21swapper/619:16:0112
2388737995641,13cyclictest1243418-21CPU8
238874099526,44cyclictest1243428-21CPU9
2388737995146,3cyclictest1243418-21CPU8
2388737995146,3cyclictest1243418-21CPU8
238875899479,25cyclictest0-21swapper/622:22:4312
2388740994741,4cyclictest1243426-21CPU9
2388740994741,4cyclictest1243426-21CPU9
2388737994730,15cyclictest1243426-21CPU8
2388737994627,17cyclictest1243417-21CPU8
2388737994627,17cyclictest1243417-21CPU8
238875899457,25cyclictest0-21swapper/623:06:4012
238875899446,13cyclictest0-21swapper/600:12:3412
2388740994438,4cyclictest1243417-21CPU9
238875899426,25cyclictest0-21swapper/620:43:5312
238875899426,25cyclictest0-21swapper/620:43:5212
238875899380,13cyclictest0-21swapper/619:59:5712
2388727993714,21cyclictest1243425-21CPU0
2388758993611,12cyclictest801ktimers/619:37:5912
238875899360,11cyclictest0-21swapper/620:21:5512
238875899360,11cyclictest0-21swapper/600:23:3312
2388727993623,11cyclictest1243416-21CPU0
2388758993511,24cyclictest0-21swapper/620:10:5612
2388758993510,14cyclictest0-21swapper/622:11:4412
2388727993533,1cyclictest1243422-21CPU0
2388727993532,2cyclictest1243422-21CPU0
2388727993518,15cyclictest1243417-21CPU0
238875899349,14cyclictest0-21swapper/619:48:5812
2388758993410,24cyclictest0-21swapper/623:39:3712
2388758993410,24cyclictest0-21swapper/623:17:3912
2388758993410,13cyclictest0-21swapper/621:05:5112
2388740993418,5cyclictest211rcu_preempt23:10:069
2388727993424,8cyclictest1243424-21CPU0
238877899336,25cyclictest1243419-21CPU4
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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