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2026-01-30 - 00:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5s.osadl.org (updated Thu Jan 29, 2026 00:45:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29412492360338,14sleep120-21swapper/124
29412482327304,14sleep110-21swapper/113
29410992319297,14sleep60-21swapper/612
29413592318294,15sleep130-21swapper/135
29413332312288,15sleep70-21swapper/713
29411372310287,15sleep90-21swapper/915
29413632309286,15sleep00-21swapper/00
29411562309287,14sleep80-21swapper/814
29410042309287,14sleep20-21swapper/28
29411512308286,14sleep40-21swapper/410
29412732307285,14sleep10-21swapper/11
29411212305283,14sleep100-21swapper/102
29413292304282,14sleep30-21swapper/39
29412782301279,14sleep50-21swapper/511
29411262301277,15sleep150-21swapper/157
29411972294266,18sleep140-21swapper/146
2941712995719,13cyclictest100651-21CPU13
294171299479,25cyclictest0-21swapper/713
294171299477,27cyclictest0-21swapper/713
294171299426,11cyclictest0-21swapper/713
2941742994140,1cyclictest2247-21snmpd7
2941739994040,0cyclictest0-21swapper/146
2941739994040,0cyclictest0-21swapper/146
2941739994039,1cyclictest2247-21snmpd6
2941739994039,1cyclictest2247-21snmpd6
2941703994039,1cyclictest2247-21snmpd10
2941695994023,17cyclictest2247-21snmpd8
2941732993937,1cyclictest2247-21snmpd5
2941732993937,1cyclictest2247-21snmpd5
2941739993821,1cyclictest0-21swapper/146
2941732993837,1cyclictest2247-21snmpd5
2941732993836,1cyclictest0-21swapper/135
2941727993838,0cyclictest0-21swapper/124
2941742993635,1cyclictest2247-21snmpd7
2941725993635,1cyclictest2247-21snmpd3
2941705993634,1cyclictest0-21swapper/511
2941703993634,1cyclictest2247-21snmpd10
2941722993517,17cyclictest0-21swapper/102
2941705993533,1cyclictest0-21swapper/511
2941700993534,1cyclictest0-21swapper/39
2941700993533,1cyclictest0-21swapper/39
2941692993534,1cyclictest0-21swapper/11
2941722993434,0cyclictest0-21swapper/102
294171299349,14cyclictest0-21swapper/713
2941710993433,1cyclictest0-21swapper/612
2941710993432,1cyclictest2247-21snmpd12
2941705993434,0cyclictest0-21swapper/511
2941705993434,0cyclictest0-21swapper/511
2941712993332,1cyclictest0-21swapper/713
2941692993332,1cyclictest0-21swapper/11
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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