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2026-05-28 - 04:58

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5s.osadl.org (updated Thu May 28, 2026 00:45:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
59052299861932861927,4cyclictest0-21swapper/612
59052699861821861816,4cyclictest0-21swapper/713
59051899849591849583,6cyclictest0-21swapper/511
59052699814828814817,9cyclictest3714971-21CPU13
59051899809009808998,9cyclictest3714971-21CPU11
59055399796981796975,4cyclictest181rcu_preempt6
59049699790527790521,5cyclictest0-21swapper/00
59054699761985761977,5cyclictest181rcu_preempt4
59054699752986752979,4cyclictest181rcu_preempt4
59050399702726702715,9cyclictest3714971-21CPU8
59050399702726702715,9cyclictest3714971-21CPU8
59052699698000697988,8cyclictest3714970-21CPU13
59051399677052677041,9cyclictest3714971-21CPU10
59051899668179668174,4cyclictest0-21swapper/511
59052299642919642910,6cyclictest181rcu_preempt12
59053699635503635492,9cyclictest3714972-21CPU2
59050099632973632959,9cyclictest3714967-21CPU1
59050099632973632959,9cyclictest3714967-21CPU1
59050099612978612972,5cyclictest0-21swapper/11
59054699610635610625,8cyclictest3714971-21CPU4
59052999558903558891,7cyclictest3714969-21CPU14
59050699542948542933,10cyclictest3714974-21CPU9
59053699541976541968,5cyclictest181rcu_preempt2
59054699524706524701,4cyclictest0-21swapper/124
59052299500912500905,4cyclictest181rcu_preempt12
59050699499946499934,8cyclictest3714973-21CPU9
59050699491947491942,3cyclictest181rcu_preempt9
59054099483975483968,4cyclictest181rcu_preempt3
59052699464580464575,4cyclictest0-21swapper/713
59054099458975458963,8cyclictest3714973-21CPU3
59050399456847456836,8cyclictest0-21swapper/28
59052999455662455656,5cyclictest0-21swapper/814
59053499453916453911,4cyclictest0-21swapper/915
59052299448355448347,7cyclictest3714973-21CPU12
59055799448016448006,8cyclictest3714974-21CPU7
59050699441979441971,6cyclictest3714968-21CPU9
59055799437004436998,5cyclictest0-21swapper/157
59055399436832436820,10cyclictest3714973-21CPU6
59055399434979434972,4cyclictest181rcu_preempt6
59054099434977434966,7cyclictest3714973-21CPU3
59050699433843433838,4cyclictest0-21swapper/39
59051899432124432113,9cyclictest3714973-21CPU11
59050099423232423222,8cyclictest3714975-21CPU1
59055799421725421718,6cyclictest0-21swapper/157
59052999419903419889,9cyclictest3714973-21CPU14
59054099414800414795,4cyclictest0-21swapper/113
59054699408981408969,8cyclictest3714975-21CPU4
59054699406993406987,5cyclictest0-21swapper/124
59051899406526406521,4cyclictest0-21swapper/511
59049699381034381029,4cyclictest0-21swapper/00
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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