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2026-06-11 - 13:18

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5s.osadl.org (updated Thu Jun 11, 2026 00:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22544599912190281219023,4cyclictest0-21swapper/146
225445999905945905940,4cyclictest0-21swapper/146
225445499900844900838,5cyclictest0-21swapper/135
225440899815883815875,7cyclictest3714973-21CPU8
225441599759305759300,4cyclictest0-21swapper/39
225443599748505748496,7cyclictest0-21swapper/814
225440199726919726910,8cyclictest3714968-21CPU0
225443599707319707314,4cyclictest0-21swapper/814
225445099704202704197,4cyclictest0-21swapper/124
225445999691122691117,4cyclictest0-21swapper/146
225445999678354678344,8cyclictest3714970-21CPU6
225443599666110666099,9cyclictest3714969-21CPU14
225443599663592663583,7cyclictest3714969-21CPU14
225445999661333661328,4cyclictest0-21swapper/146
225445499621883621877,4cyclictest181rcu_preempt5
225443599603873603864,8cyclictest3714970-21CPU14
225440199587006587000,4cyclictest181rcu_preempt0
225443899584097584088,7cyclictest0-21swapper/915
225443199577987577980,4cyclictest181rcu_preempt13
225441599569831569827,3cyclictest0-21swapper/39
225443599560113560107,5cyclictest0-21swapper/814
225440499550996550989,5cyclictest181rcu_preempt1
225443199529243529232,9cyclictest3714970-21CPU13
225445999524330524325,4cyclictest0-21swapper/146
225445099521350521340,8cyclictest3714972-21CPU4
225443899521125521120,4cyclictest0-21swapper/915
225445099496916496902,10cyclictest3714975-21CPU4
225443599495379495368,9cyclictest3714973-21CPU14
225443599495379495368,9cyclictest3714973-21CPU14
225445999493117493107,9cyclictest3714970-21CPU6
225441599488911488900,9cyclictest3714974-21CPU9
225440499483385483375,8cyclictest3714972-21CPU1
225444499461870461858,8cyclictest3714968-21CPU2
225444499461870461858,8cyclictest3714968-21CPU2
225440199460055460045,8cyclictest3714970-21CPU0
225443899459874459868,4cyclictest181rcu_preempt15
225440899456571456567,3cyclictest0-21swapper/28
225440199456059456047,9cyclictest3714971-21CPU0
225443899446109446104,4cyclictest0-21swapper/915
225445999425467425462,4cyclictest0-21swapper/146
225444699411910411902,5cyclictest181rcu_preempt3
225441599409402409393,7cyclictest3714969-21CPU9
225445999407922407917,4cyclictest0-21swapper/146
225445999407922407917,4cyclictest0-21swapper/146
225445999404940404930,8cyclictest3714969-21CPU6
225445999388907388894,9cyclictest3714973-21CPU6
225445999381280381272,6cyclictest0-21swapper/146
225443599379911379902,7cyclictest3714966-21CPU14
225445099374258374249,7cyclictest3714970-21CPU4
225444699371674371665,7cyclictest0-21swapper/113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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