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2026-06-04 - 10:21

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5s.osadl.org (updated Thu Jun 04, 2026 00:45:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
152090199888315888305,8cyclictest0-21swapper/814
152092299849500849495,4cyclictest0-21swapper/146
152089799799655799651,3cyclictest0-21swapper/713
152091699780932780925,4cyclictest181rcu_preempt4
152091699780932780925,4cyclictest181rcu_preempt4
152090699778898778891,4cyclictest181rcu_preempt15
152087999721862721857,4cyclictest0-21swapper/39
152087999688147688137,8cyclictest3714973-21CPU9
152090899687194687189,4cyclictest0-21swapper/102
152087299671994671982,8cyclictest3714970-21CPU1
152091299660901660895,4cyclictest181rcu_preempt3
152086799619956619943,9cyclictest3714971-21CPU0
152086799615954615948,4cyclictest181rcu_preempt0
152087699581416581406,8cyclictest3714975-21CPU8
152092299568912568906,4cyclictest181rcu_preempt6
152089799562877562871,4cyclictest181rcu_preempt13
152090199536971536961,8cyclictest3714971-21CPU14
152092099535437535424,11cyclictest3714972-21CPU5
152088699529284529275,7cyclictest0-21swapper/511
152090199529134529124,8cyclictest3714969-21CPU14
152091699511192511182,8cyclictest3714973-21CPU4
152092299505915505908,4cyclictest181rcu_preempt6
152088999486323486317,5cyclictest0-21swapper/612
152090699474397474390,6cyclictest3714969-21CPU15
152087699470003469991,8cyclictest3714975-21CPU8
152091299461354461349,4cyclictest0-21swapper/113
152087699460924460915,7cyclictest3714974-21CPU8
152092099456991456980,9cyclictest3714970-21CPU5
152087999450398450386,10cyclictest3714973-21CPU9
152087699439007438998,6cyclictest181rcu_preempt8
152086799430541430534,6cyclictest3714971-21CPU0
152090899428903428889,11cyclictest3714975-21CPU2
152090899425263425258,4cyclictest0-21swapper/102
152092299418916418903,8cyclictest3714967-21CPU6
152088699404639404635,3cyclictest0-21swapper/511
152091699401932401919,9cyclictest3714974-21CPU4
152092799393628393622,5cyclictest0-21swapper/157
152087299382272382267,4cyclictest0-21swapper/11
152089799366401366396,4cyclictest0-21swapper/713
152089799366113366108,4cyclictest0-21swapper/713
152086799363908363903,4cyclictest0-21swapper/00
152088699363605363599,5cyclictest0-21swapper/511
152086799361482361477,4cyclictest0-21swapper/00
152091699361378361374,3cyclictest0-21swapper/124
152090899361238361234,3cyclictest0-21swapper/102
152088699361000360990,8cyclictest3714969-21CPU11
152089799360489360484,4cyclictest0-21swapper/713
152090199359678359674,3cyclictest0-21swapper/814
152087999359280359276,3cyclictest0-21swapper/39
152088999358608358604,3cyclictest0-21swapper/612
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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