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2025-08-30 - 02:45

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5s.osadl.org (updated Sat Aug 30, 2025 00:47:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9977982371345,18sleep10-21swapper/119:09:051
9975902364311,18sleep20-21swapper/219:06:098
9976362363336,18sleep40-21swapper/419:06:4310
9977952354327,18sleep150-21swapper/1519:09:047
9977512350295,18sleep90-21swapper/919:08:2515
9976822347320,18sleep140-21swapper/1419:07:256
9977172346319,18sleep110-21swapper/1119:07:553
9978222344317,18sleep80-21swapper/819:09:2914
9977302343316,18sleep70-21swapper/719:08:0713
9976562342316,17sleep50-21swapper/519:07:0011
9976222342315,18sleep120-21swapper/1219:06:354
9978142339312,18sleep00-21swapper/019:09:200
9976132339312,18sleep30-21swapper/319:06:269
9977462338311,18sleep60-21swapper/619:08:2312
9976642338311,18sleep130-21swapper/1319:07:085
9977522336308,19sleep100-21swapper/1019:08:262
998206994216,25cyclictest3485315-21SPICE10:29:1612
99820699368,28cyclictest0-21swapper/600:24:5812
99820699367,14cyclictest0-21swapper/622:35:0712
99820699359,13cyclictest0-21swapper/620:45:1712
99820699358,14cyclictest0-21swapper/622:57:0612
99820699358,14cyclictest0-21swapper/622:02:1012
99820699358,14cyclictest0-21swapper/621:29:1312
99820699358,14cyclictest0-21swapper/621:07:1512
99820699357,14cyclictest0-21swapper/623:30:0212
99820699357,14cyclictest0-21swapper/620:01:2212
99820699357,14cyclictest0-21swapper/620:01:2112
99820699348,14cyclictest0-21swapper/619:17:2512
99820699347,27cyclictest0-21swapper/623:19:0412
99820699347,14cyclictest0-21swapper/620:12:2112
99820699347,14cyclictest0-21swapper/620:12:2012
998213993327,2cyclictest1526-21snmpd22:17:3414
99820699339,24cyclictest0-21swapper/622:13:0912
99820699337,14cyclictest0-21swapper/622:46:0712
99820699337,14cyclictest0-21swapper/622:24:0812
99820699337,14cyclictest0-21swapper/622:24:0812
99820699337,13cyclictest0-21swapper/623:52:0012
99820699337,13cyclictest0-21swapper/619:39:2412
99820699337,13cyclictest0-21swapper/600:35:5612
99820699337,13cyclictest0-21swapper/600:35:5612
99821399320,27cyclictest0-21swapper/821:41:1814
99820699328,24cyclictest0-21swapper/621:18:1412
99820699328,24cyclictest0-21swapper/600:13:5812
99820699326,13cyclictest0-21swapper/621:51:1112
99820699326,13cyclictest0-21swapper/620:34:1912
998213993126,1cyclictest1526-21snmpd00:07:1914
99820699317,24cyclictest0-21swapper/623:08:0412
99820699316,24cyclictest0-21swapper/620:23:1912
99823999300,30cyclictest0-21swapper/1422:00:546
99823999300,1cyclictest0-21swapper/1423:25:426
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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