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2026-03-04 - 04:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot6s.osadl.org (updated Wed Mar 04, 2026 00:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2105542244237,4sleep120-21swapper/1219:06:014
2108512242234,5sleep90-21swapper/919:09:3919
2108042241202,11sleep170-21swapper/1719:09:079
2108562240232,5sleep140-21swapper/1419:09:446
2105142238217,13sleep70-21swapper/719:05:3717
2105322237229,5sleep130-21swapper/1319:05:425
2106522236194,12sleep100-21swapper/1019:07:192
2107162233213,13sleep180-21swapper/1819:08:0810
2107142233212,13sleep160-21swapper/1619:08:078
2107022230211,12sleep60-21swapper/619:07:5716
2106692230209,13sleep30-21swapper/319:07:3313
2105442228209,12sleep20-21swapper/219:05:5112
2105022228207,13sleep190-21swapper/1919:05:2811
2105802227208,12sleep150-21swapper/1519:06:257
2105962226207,12sleep80-21swapper/819:06:3718
2105412225205,12sleep00-21swapper/019:05:490
2106112221203,11sleep10-21swapper/119:06:501
2108222220200,12sleep110-21swapper/1119:09:213
2106992218199,12sleep50-21swapper/519:07:5515
2105922197177,13sleep40-21swapper/419:06:3314
21126099828,33cyclictest0-21swapper/823:32:0218
4618332440,0sleep20-21swapper/200:00:1212
21124099250,25cyclictest0-21swapper/419:11:3314
21129099232,20cyclictest472312-21qemu-system-x8619:10:469
211285992323,0cyclictest0-21swapper/1619:11:328
211285992323,0cyclictest0-21swapper/1600:15:178
21126099230,22cyclictest270528-21strings20:15:1718
21126099230,18cyclictest0-21swapper/819:11:3418
21129699220,21cyclictest472371-21CPU11
211275992222,0cyclictest0-21swapper/1319:10:465
211262992220,1cyclictest472370-21CPU19
211260992220,1cyclictest472371-21CPU18
211251992221,0cyclictest0-21swapper/622:44:2416
21124099225,16cyclictest0-21swapper/400:20:1714
21124099224,17cyclictest468751-21sshd-session00:08:3114
21124099224,17cyclictest0-21swapper/400:37:4014
21124099223,18cyclictest0-21swapper/400:15:1814
21123999220,21cyclictest212060-21cpuspeed_turbos19:10:1213
21129699210,20cyclictest0-21swapper/1919:10:1511
21129499210,21cyclictest0-21swapper/1819:12:4210
21128599210,16cyclictest0-21swapper/1622:13:268
211275992110,11cyclictest0-21swapper/1322:53:595
21126599210,21cyclictest0-21swapper/1000:08:402
21126299210,21cyclictest464448-21ssh00:03:0619
21126299210,21cyclictest0-21swapper/919:10:4519
21125199210,20cyclictest0-21swapper/619:12:3516
21124099214,16cyclictest0-21swapper/419:35:1814
21124099213,16cyclictest0-21swapper/400:30:1314
211296992020,0cyclictest0-21swapper/1920:50:1411
21129699200,1cyclictest472370-21CPU11
21129699200,0cyclictest0-21swapper/1920:15:1811
211294992020,0cyclictest0-21swapper/1800:03:0010
21129499200,20cyclictest0-21swapper/1823:20:1610
21129499200,20cyclictest0-21swapper/1823:00:1710
211265992018,1cyclictest7504-21CPU2
211262992020,0cyclictest167633-21kworker/9:1+events20:55:1719
211262992020,0cyclictest0-21swapper/919:35:1519
211262992019,1cyclictest477275-21scp00:22:1219
21125599200,19cyclictest0-21swapper/719:10:0317
21125199200,19cyclictest0-21swapper/619:35:1516
21124099209,11cyclictest0-21swapper/422:50:5914
21124099205,0cyclictest0-21swapper/423:55:2614
21124099204,15cyclictest352017-21cat21:50:1514
21124099204,15cyclictest0-21swapper/423:45:2114
21123999200,19cyclictest0-21swapper/322:15:1613
211231992019,0cyclictest0-21swapper/119:12:351
211296991919,0cyclictest0-21swapper/1919:15:1711
211296991919,0cyclictest0-21swapper/1900:03:0611
211296991918,1cyclictest0-21swapper/1921:50:2411
211294991919,0cyclictest296254-21strings20:45:1610
211294991916,2cyclictest472370-21CPU10
21129499190,0cyclictest0-21swapper/1822:01:2310
211285991919,0cyclictest0-21swapper/1600:20:128
21128599190,0cyclictest0-21swapper/1622:20:168
21128299190,19cyclictest0-21swapper/1519:10:407
21128099190,1cyclictest472371-21CPU6
21128099190,19cyclictest0-21swapper/1419:10:586
21128099190,18cyclictest0-21swapper/1421:23:226
21128099190,18cyclictest0-21swapper/1419:36:196
21127599190,19cyclictest0-21swapper/1300:15:185
21127299190,19cyclictest0-21swapper/1222:20:164
21127299190,19cyclictest0-21swapper/1219:11:164
21127299190,0cyclictest0-21swapper/1223:45:164
211262991919,0cyclictest0-21swapper/923:20:1619
211262991919,0cyclictest0-21swapper/920:50:1419
21126299190,18cyclictest413256-21kworker/9:0+events23:45:1519
211260991918,1cyclictest0-21swapper/822:20:1618
21126099190,19cyclictest0-21swapper/800:22:1118
21125599190,18cyclictest0-21swapper/722:20:1717
21125599190,0cyclictest0-21swapper/723:05:1417
21125199190,19cyclictest0-21swapper/623:05:1416
21125199190,19cyclictest0-21swapper/620:50:1416
21125199190,0cyclictest343490-21strings21:40:1716
21125199190,0cyclictest343490-21strings21:40:1716
21124499190,19cyclictest0-21swapper/519:35:1515
21124499190,19cyclictest0-21swapper/519:10:4415
21124099194,3cyclictest0-21swapper/419:20:1214
21124099194,3cyclictest0-21swapper/400:00:1214
21124099193,3cyclictest0-21swapper/400:10:2114
21124099193,15cyclictest0-21swapper/400:25:1614
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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