OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8
Special All - All RT - Optimization - Ethernet - Thumbnails - Next

Click here to display the system's profile data or here to proceed to next system.

Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system

Characteristics of the 100 highest latencies:

System rack0slot6s.osadl.org (updated Tue May 19, 2026 00:46:04)
Delayed (victim)					Switcher (culprit)			Timestamp	CPU
PID	Prio	Total latency (µs)	T^(,W^*) latency (µs)	Cmd	PID	Prio	Cmd	Timestamp	CPU
1603131	2	242	220,14	sleep16	0	-21	swapper/16	19:08:37	8
1603124	2	241	233,5	sleep11	0	-21	swapper/11	19:08:32	3
1603154	2	237	230,4	sleep10	0	-21	swapper/10	19:08:52	2
1602958	2	236	229,4	sleep6	0	-21	swapper/6	19:06:46	16
1602849	2	235	218,9	sleep9	0	-21	swapper/9	19:05:30	19
1602986	2	233	215,11	sleep7	0	-21	swapper/7	19:07:08	17
1603036	2	231	218,8	sleep3	0	-21	swapper/3	19:07:44	13
1603188	2	230	211,12	sleep12	0	-21	swapper/12	19:09:13	4
1602848	2	230	210,12	sleep8	0	-21	swapper/8	19:05:29	18
1602897	2	229	210,12	sleep4	0	-21	swapper/4	19:06:04	14
1602923	2	227	207,12	sleep18	0	-21	swapper/18	19:06:19	10
1603177	2	226	212,9	sleep5	0	-21	swapper/5	19:09:06	15
1603208	2	223	184,31	sleep1	0	-21	swapper/1	19:09:23	1
1602949	2	222	201,13	sleep19	0	-21	swapper/19	19:06:40	11
1603164	2	220	202,11	sleep15	0	-21	swapper/15	19:08:56	7
1603132	2	212	203,5	sleep17	0	-21	swapper/17	19:08:39	9
1602967	2	208	198,6	sleep14	0	-21	swapper/14	19:06:54	6
1602966	2	205	188,11	sleep13	0	-21	swapper/13	19:06:53	5
1603027	2	188	169,12	sleep0	0	-21	swapper/0	19:07:42	0
1603109	2	76	68,5	sleep2	0	-21	swapper/2	19:08:24	12
1603649	99	66	5,23	cyclictest	0	-21	swapper/10	23:41:56	2
1603677	99	42	34,0	cyclictest	0	-21	swapper/19	19:44:59	11
1603644	99	41	0,1	cyclictest	1700471	-21	CPU		19
1603677	99	39	0,1	cyclictest	1700472	-21	CPU		11
1603644	99	39	0,36	cyclictest	0	-21	swapper/9	21:48:59	19
1603655	99	38	31,0	cyclictest	0	-21	swapper/12	20:09:59	4
1603644	99	37	33,4	cyclictest	0	-21	swapper/9	20:55:58	19
1603675	99	36	0,35	cyclictest	1646533	-21	crond	19:59:59	10
1603665	99	36	1,34	cyclictest	1700471	-21	CPU		7
1603658	99	36	1,34	cyclictest	1700471	-21	CPU		5
1603644	99	36	33,3	cyclictest	0	-21	swapper/9	20:11:58	19
1603644	99	36	28,7	cyclictest	1700472	-21	CPU		19
1603675	99	35	33,1	cyclictest	1700472	-21	CPU		10
1603675	99	35	33,1	cyclictest	1700471	-21	CPU		10
1603667	99	35	33,1	cyclictest	1700472	-21	CPU		8
1603665	99	35	33,1	cyclictest	1700471	-21	CPU		7
1603665	99	35	33,1	cyclictest	1700471	-21	CPU		7
1603660	99	35	0,33	cyclictest	0	-21	swapper/14	21:50:59	6
1603660	99	35	0,1	cyclictest	1700471	-21	CPU		6
1603658	99	35	0,34	cyclictest	1700472	-21	CPU		5
1603644	99	35	29,6	cyclictest	0	-21	swapper/9	22:04:58	19
1603644	99	35	27,0	cyclictest	0	-21	swapper/9	20:09:58	19
1603634	99	35	0,34	cyclictest	1700471	-21	CPU		17
1603626	99	35	0,34	cyclictest	0	-21	swapper/4	20:13:59	14
1603623	99	35	0,34	cyclictest	1700472	-21	CPU		13
1603677	99	34	33,0	cyclictest	0	-21	swapper/19	21:06:59	11
1603675	99	34	34,0	cyclictest	0	-21	swapper/18	21:49:58	10
1603675	99	34	32,1	cyclictest	1700472	-21	CPU		10
1603675	99	34	0,33	cyclictest	0	-21	swapper/18	19:20:58	10
1603667	99	34	32,1	cyclictest	1700471	-21	CPU		8
1603665	99	34	0,33	cyclictest	0	-21	swapper/15	20:13:58	7
1603660	99	34	32,1	cyclictest	1700471	-21	CPU		6
1603660	99	34	0,33	cyclictest	0	-21	swapper/14	21:33:59	6
1603660	99	34	0,33	cyclictest	0	-21	swapper/14	21:33:58	6
1603660	99	34	0,1	cyclictest	0	-21	swapper/14	23:14:59	6
1603658	99	34	0,33	cyclictest	0	-21	swapper/13	20:43:59	5
1603634	99	34	32,1	cyclictest	1700471	-21	CPU		17
1603633	99	34	0,33	cyclictest	0	-21	swapper/6	20:08:59	16
1603633	99	34	0,33	cyclictest	0	-21	swapper/6	19:24:59	16
1603630	99	34	0,33	cyclictest	0	-21	swapper/5	20:58:59	15
1603620	99	34	32,2	cyclictest	0	-21	swapper/2	20:48:58	12
1603677	99	33	0,33	cyclictest	0	-21	swapper/19	20:06:58	11
1603675	99	33	33,0	cyclictest	0	-21	swapper/18	22:10:58	10
1603675	99	33	33,0	cyclictest	0	-21	swapper/18	21:40:59	10
1603675	99	33	33,0	cyclictest	0	-21	swapper/18	21:40:59	10
1603675	99	33	33,0	cyclictest	0	-21	swapper/18	19:37:58	10
1603675	99	33	33,0	cyclictest	0	-21	swapper/18	19:32:58	10
1603667	99	33	33,0	cyclictest	0	-21	swapper/16	21:21:58	8
1603667	99	33	0,0	cyclictest	0	-21	swapper/16	20:40:58	8
1603667	99	33	0,0	cyclictest	0	-21	swapper/16	20:00:59	8
1603665	99	33	33,0	cyclictest	0	-21	swapper/15	21:02:58	7
1603665	99	33	0,33	cyclictest	0	-21	swapper/15	22:01:59	7
1603665	99	33	0,33	cyclictest	0	-21	swapper/15	20:51:59	7
1603660	99	33	0,33	cyclictest	0	-21	swapper/14	21:18:58	6
1603660	99	33	0,1	cyclictest	1874863	-21	updatedb	00:30:08	6
1603660	99	33	0,1	cyclictest	1700471	-21	CPU		6
1603660	99	33	0,0	cyclictest	0	-21	swapper/14	19:59:58	6
1603649	99	33	31,1	cyclictest	1700471	-21	CPU		2
1603649	99	33	0,32	cyclictest	1700472	-21	CPU		2
1603649	99	33	0,1	cyclictest	1700472	-21	CPU		2
1603634	99	33	33,0	cyclictest	0	-21	swapper/7	19:28:58	17
1603634	99	33	32,0	cyclictest	0	-21	swapper/7	21:55:59	17
1603634	99	33	32,0	cyclictest	0	-21	swapper/7	19:48:59	17
1603634	99	33	32,0	cyclictest	0	-21	swapper/7	19:15:59	17
1603634	99	33	0,33	cyclictest	0	-21	swapper/7	19:52:58	17
1603634	99	33	0,0	cyclictest	0	-21	swapper/7	21:13:58	17
1603634	99	33	0,0	cyclictest	0	-21	swapper/7	20:02:59	17
1603634	99	33	0,0	cyclictest	0	-21	swapper/7	00:09:59	17
1603634	99	33	0,0	cyclictest	0	-21	swapper/7	00:09:59	17
1603626	99	33	33,0	cyclictest	0	-21	swapper/4	20:29:58	14
1603626	99	33	0,0	cyclictest	0	-21	swapper/4	19:39:59	14
1603623	99	33	0,33	cyclictest	0	-21	swapper/3	22:32:59	13
1603623	99	33	0,33	cyclictest	0	-21	swapper/3	21:30:59	13
1603623	99	33	0,33	cyclictest	0	-21	swapper/3	21:30:59	13
1603620	99	33	13,20	cyclictest	42	1	rcuc/2	22:35:15	12
1603677	99	32	32,0	cyclictest	0	-21	swapper/19	21:49:58	11
1603675	99	32	32,0	cyclictest	0	-21	swapper/18	20:13:58	10
1603675	99	32	30,1	cyclictest	1700471	-21	CPU		10
1603675	99	32	0,32	cyclictest	0	-21	swapper/18	23:47:59	10
1603667	99	32	32,0	cyclictest	0	-21	swapper/16	21:31:58	8
^Timer ^*Wakeup (latency=timer+wakeup+contextswitch)


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This page was last modified on 2019-05-28 - 00:17