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2026-02-25 - 02:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot6s.osadl.org (updated Wed Feb 25, 2026 00:46:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9671052278271,4sleep100-21swapper/1019:09:142
9670962248241,4sleep40-21swapper/419:09:0714
9667562239232,4sleep60-21swapper/619:05:2816
9669342236217,12sleep30-21swapper/319:07:2513
9671222234226,5sleep50-21swapper/519:09:2815
9668402234214,12sleep00-21swapper/019:06:230
9668422233213,12sleep20-21swapper/219:06:2412
9667632232224,5sleep120-21swapper/1219:05:344
9671922230210,12sleep140-21swapper/1419:09:576
9668852230212,11sleep130-21swapper/1319:06:555
9667772230222,5sleep10-21swapper/119:05:441
9670532223204,12sleep160-21swapper/1619:08:398
9670202223206,10sleep150-21swapper/1519:08:187
9668052223202,13sleep180-21swapper/1819:06:0110
9668832222201,13sleep110-21swapper/1119:06:533
9671852219199,12sleep90-21swapper/919:09:5319
9670122213192,13sleep80-21swapper/819:08:1218
9668062211190,13sleep190-21swapper/1919:06:0111
9669702208187,13sleep70-21swapper/719:07:5017
9668042207187,12sleep170-21swapper/1719:06:009
9676299910410,47cyclictest0-21swapper/319:17:0213
96763399869,45cyclictest0-21swapper/422:32:0214
96763399869,45cyclictest0-21swapper/422:32:0114
96766399607,49cyclictest0-21swapper/1300:31:025
967669995941,12cyclictest472370-21CPU7
967653995823,14cyclictest472370-21CPU2
967659995724,33cyclictest1341rcuc/1200:03:204
967647995731,26cyclictest0-21swapper/823:57:2918
967647995723,32cyclictest0-21swapper/822:20:1718
967677995614,37cyclictest10558031kworker/u80:0+i91522:33:599
967677995614,37cyclictest10558031kworker/u80:0+i91522:33:599
967637995611,4cyclictest71-21ksoftirqd/522:09:2315
967663995523,31cyclictest0-21swapper/1323:00:195
967637995419,32cyclictest472371-21CPU15
967659995325,26cyclictest1341rcuc/1219:20:424
967659995325,26cyclictest1341rcuc/1219:20:424
96764799530,0cyclictest0-21swapper/820:00:4418
967619995318,35cyclictest231rcuc/000:03:200
967679995236,13cyclictest7504-21CPU10
967659995224,25cyclictest0-21swapper/1220:45:174
967657995222,26cyclictest0-21swapper/1120:45:173
967647995221,30cyclictest0-21swapper/800:05:1118
967647995220,31cyclictest0-21swapper/819:24:0118
967647995220,31cyclictest0-21swapper/819:24:0018
96764799512,6cyclictest472370-21CPU18
967647995019,30cyclictest981165-21surface-HDMI-A-00:22:0518
967647995016,33cyclictest0-21swapper/823:15:1918
967637995013,36cyclictest0-21swapper/500:03:2015
967663994919,26cyclictest0-21swapper/1319:10:135
967653994913,35cyclictest1141rcuc/1000:03:212
967679994817,1cyclictest190-21ksoftirqd/1800:27:4410
967659994817,30cyclictest0-21swapper/1223:00:204
967657994824,22cyclictest0-21swapper/1123:55:133
967657994822,25cyclictest1251rcuc/1119:20:423
967657994822,25cyclictest1251rcuc/1119:20:423
967649994837,9cyclictest472371-21CPU19
967683994714,30cyclictest1198392-21kworker/u80:0+i91523:46:0511
967679994724,1cyclictest981166-21surface-DP-122:42:2010
967679994724,1cyclictest981166-21surface-DP-122:42:1910
967677994721,4cyclictest472370-21CPU9
967663994722,23cyclictest0-21swapper/1320:00:005
967657994716,31cyclictest0-21swapper/1100:03:203
967653994725,22cyclictest981166-21surface-DP-121:47:212
967647994716,30cyclictest0-21swapper/820:16:0218
967639994722,2cyclictest908613-21cosmic-comp23:09:1716
967629994714,6cyclictest981166-21surface-DP-119:32:4813
967629994714,6cyclictest981166-21surface-DP-119:32:4813
967679994626,0cyclictest908613-21cosmic-comp21:17:2110
967649994644,1cyclictest0-21swapper/900:25:5919
96764799460,15cyclictest0-21swapper/819:54:5618
967637994615,6cyclictest71-21ksoftirqd/523:58:5715
967629994644,1cyclictest0-21swapper/323:00:5913
967627994644,1cyclictest908613-21cosmic-comp22:08:2112
967619994619,25cyclictest0-21swapper/019:20:430
967619994619,25cyclictest0-21swapper/019:20:420
967683994513,29cyclictest12200631kworker/u80:0+i91500:05:5211
967673994515,28cyclictest1220063-21kworker/u80:0+i91500:02:018
967647994515,30cyclictest941irq_work/822:34:2118
967647994515,30cyclictest941irq_work/822:34:2018
967637994544,0cyclictest0-21swapper/500:33:5715
967627994519,23cyclictest472371-21CPU12
967683994414,29cyclictest1951irq_work/1919:17:3011
967667994414,28cyclictest1055803-21kworker/u80:0+i91521:16:586
967663994411,27cyclictest0-21swapper/1321:20:375
967659994422,1cyclictest0-21swapper/1221:10:184
967659994412,26cyclictest136-21ksoftirqd/1222:08:254
967657994421,23cyclictest0-21swapper/1121:10:183
967649994414,29cyclictest1031irq_work/923:20:2019
967639994414,28cyclictest1055803-21kworker/u80:0+i91522:28:5516
967623994440,1cyclictest472370-21CPU1
96761999446,36cyclictest0-21swapper/022:08:120
967619994418,25cyclictest231rcuc/020:45:170
967679994315,28cyclictest1861irq_work/1820:21:5810
967677994310,27cyclictest0-21swapper/1721:11:129
967677994310,26cyclictest0-21swapper/1722:19:249
967669994310,33cyclictest0-21swapper/1500:12:207
967663994319,1cyclictest0-21swapper/1300:05:185
967663994311,26cyclictest0-21swapper/1321:19:005
96765999439,30cyclictest0-21swapper/1222:20:174
96765999434,37cyclictest0-21swapper/1223:16:214
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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