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2025-07-01 - 05:27

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot7s.osadl.org (updated Fri May 23, 2025 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
795444212865,52sleep20-21swapper/219:06:432
793942211862,24sleep00-21swapper/019:05:000
795500210775,24sleep10-21swapper/119:07:261
795638210664,34sleep30-21swapper/319:09:123
795840997015,42cyclictest0-21swapper/321:55:303
795832992817,10cyclictest0-21swapper/023:32:420
79583299260,25cyclictest0-21swapper/023:46:580
79583299260,25cyclictest0-21swapper/020:02:380
79584099250,25cyclictest0-21swapper/322:08:073
79583999240,24cyclictest0-21swapper/200:16:582
795834992414,4cyclictest803576-21sensors_fan19:25:231
79583999231,14cyclictest844229-21/usr/sbin/munin21:10:102
795832992211,10cyclictest0-21swapper/023:18:330
79584099201,1cyclictest191rcu_preempt00:08:253
79584099198,5cyclictest0-21swapper/323:54:163
79584099192,7cyclictest191rcu_preempt21:19:383
795840991912,7cyclictest0-21swapper/320:35:063
79583999199,4cyclictest0-21swapper/221:30:382
79583999196,1cyclictest0-21swapper/221:49:002
795832991915,4cyclictest0-21swapper/021:58:240
79584099188,10cyclictest0-21swapper/300:18:073
79584099182,0cyclictest0-21swapper/319:43:253
795839991816,1cyclictest0-21swapper/220:04:322
795839991815,2cyclictest1051-21snmpd21:37:172
795834991816,1cyclictest0-21swapper/120:31:181
795834991815,2cyclictest1051-21snmpd00:03:221
795834991812,5cyclictest0-21swapper/121:00:051
79583499180,0cyclictest0-21swapper/122:16:131
79583299187,10cyclictest0-21swapper/022:22:070
795839991714,2cyclictest1051-21snmpd22:39:172
79583999170,1cyclictest0-21swapper/220:35:162
79583999170,17cyclictest0-21swapper/223:29:122
79583999170,17cyclictest0-21swapper/220:15:512
79583499170,17cyclictest0-21swapper/122:54:291
79583499170,16cyclictest0-21swapper/123:50:121
79583499170,16cyclictest0-21swapper/123:44:041
79583499170,16cyclictest0-21swapper/122:46:281
79583499170,16cyclictest0-21swapper/122:37:471
79583499170,16cyclictest0-21swapper/119:46:071
79583299170,17cyclictest0-21swapper/022:28:520
79583299170,17cyclictest0-21swapper/021:47:360
79583299170,17cyclictest0-21swapper/020:46:280
79583299170,17cyclictest0-21swapper/020:13:500
79583299170,17cyclictest0-21swapper/019:59:150
79583299170,15cyclictest0-21swapper/021:10:160
79584099166,1cyclictest0-21swapper/300:03:243
79584099162,0cyclictest0-21swapper/300:22:173
795840991610,6cyclictest0-21swapper/322:50:233
79584099160,7cyclictest0-21swapper/321:45:093
79584099160,16cyclictest0-21swapper/323:05:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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