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2025-12-09 - 07:50

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot8s.osadl.org (updated Tue Dec 09, 2025 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
275991940,84ptp4l0-21swapper/119:06:411
304728678,6sleep70-21swapper/719:06:419
304027059,9sleep00-21swapper/019:06:340
301727059,9sleep50-21swapper/519:06:157
3231326654,10sleep110-21swapper/1119:05:083
3179126554,8sleep40-21swapper/419:05:016
309726552,10sleep60-21swapper/619:07:168
303726352,9sleep100-21swapper/1019:06:322
60702620,0sleep60-21swapper/622:40:148
60702620,0sleep60-21swapper/622:40:148
229492610,1sleep1201rcuc/120:55:221
265782550,0sleep70-21swapper/722:25:149
138632550,0sleep60-21swapper/620:45:148
378399222,7cyclictest0-21swapper/420:20:006
378399221,16cyclictest0-21swapper/423:50:006
378399212,15cyclictest0-21swapper/400:30:006
378399212,14cyclictest0-21swapper/420:45:006
378399191,17cyclictest0-21swapper/421:50:176
378699185,8cyclictest0-21swapper/522:30:007
378699180,3cyclictest0-21swapper/500:10:187
379299173,8cyclictest0-21swapper/623:20:008
378699173,8cyclictest0-21swapper/522:05:007
275991170,3ptp4l21-21ksoftirqd/100:30:231
172642170,0sleep50-21swapper/500:20:027
381099160,1cyclictest0-21swapper/1023:50:242
379299162,8cyclictest0-21swapper/621:05:008
378699162,8cyclictest0-21swapper/523:00:007
378699162,8cyclictest0-21swapper/523:00:007
376899160,1cyclictest0-21swapper/123:50:241
323102167,7sleep80-21swapper/819:05:0510
275991160,3ptp4l6040-21sshd21:57:161
275991160,0ptp4l0-21swapper/120:30:001
44972150,0sleep110-21swapper/1119:50:133
381499153,7cyclictest0-21swapper/1120:05:003
381099150,15cyclictest0-21swapper/1022:10:242
379299153,7cyclictest0-21swapper/621:17:098
379299153,7cyclictest0-21swapper/620:25:268
378699153,7cyclictest0-21swapper/519:15:007
378699153,7cyclictest0-21swapper/500:25:017
275991150,0ptp4l0-21swapper/123:30:001
275991150,0ptp4l0-21swapper/122:10:221
275991150,0ptp4l0-21swapper/120:40:151
275991150,0ptp4l0-21swapper/120:35:141
275991150,0ptp4l0-21swapper/119:25:141
275991150,0ptp4l0-21swapper/119:10:271
380599144,6cyclictest0-21swapper/919:25:0011
380599142,8cyclictest0-21swapper/923:10:0011
380599142,7cyclictest0-21swapper/923:35:0011
379299142,7cyclictest0-21swapper/622:20:018
378399142,7cyclictest0-21swapper/422:45:006
378399142,7cyclictest0-21swapper/422:45:006
375499142,7cyclictest0-21swapper/000:20:240
375499141,8cyclictest0-21swapper/021:50:000
375499141,8cyclictest0-21swapper/020:05:000
301952140,0sleep70-21swapper/721:05:179
275991140,1ptp4l21-21ksoftirqd/100:09:281
275991140,0ptp4l0-21swapper/123:10:001
275991140,0ptp4l0-21swapper/100:25:231
379299132,6cyclictest0-21swapper/623:45:018
379299132,6cyclictest0-21swapper/623:00:008
379299132,6cyclictest0-21swapper/623:00:008
379299131,8cyclictest20279-21kworker/u24:000:05:018
379299130,8cyclictest0-21swapper/621:00:008
378699133,7cyclictest0-21swapper/521:10:007
378699133,6cyclictest0-21swapper/523:05:017
3777991311,1cyclictest0-21swapper/322:30:005
375499132,6cyclictest0-21swapper/020:15:000
375499130,8cyclictest0-21swapper/000:35:010
275991130,1ptp4l27460-21getsmi21:00:271
275991130,1ptp4l21-21ksoftirqd/120:15:221
275991130,0ptp4l0-21swapper/123:35:181
275991130,0ptp4l0-21swapper/123:00:131
275991130,0ptp4l0-21swapper/123:00:131
275991130,0ptp4l0-21swapper/122:50:211
275991130,0ptp4l0-21swapper/122:50:211
275991130,0ptp4l0-21swapper/122:15:161
129332130,0chrt0-21swapper/522:05:227
381499122,6cyclictest0-21swapper/1123:00:003
381499122,6cyclictest0-21swapper/1123:00:003
381499121,6cyclictest0-21swapper/1120:15:003
380599123,6cyclictest0-21swapper/922:10:0011
380599120,8cyclictest0-21swapper/923:50:0111
379299122,6cyclictest0-21swapper/619:35:008
379299121,6cyclictest0-21swapper/621:50:008
378699122,6cyclictest0-21swapper/520:00:257
378399122,6cyclictest0-21swapper/422:25:006
378399120,7cyclictest0-21swapper/422:15:006
377799123,8cyclictest0-21swapper/300:15:015
377799123,8cyclictest0-21swapper/300:05:005
377799122,8cyclictest0-21swapper/321:45:005
375499122,6cyclictest0-21swapper/020:00:000
275991120,3ptp4l26903-21cpuspeed20:20:121
275991120,2ptp4l29427-21hddtemp_smartct19:40:171
275991120,1ptp4l21-21ksoftirqd/122:48:121
275991120,1ptp4l21-21ksoftirqd/122:48:121
275991120,0ptp4l0-21swapper/123:40:141
275991120,0ptp4l0-21swapper/121:40:131
275991120,0ptp4l0-21swapper/121:20:221
275991120,0ptp4l0-21swapper/120:50:581
275991120,0ptp4l0-21swapper/120:05:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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