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2025-08-30 - 00:46

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8s.osadl.org (updated Fri Aug 29, 2025 12:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
949801000,94rtkit-daemon0-21swapper/1007:09:442
275991860,77ptp4l0-21swapper/107:06:321
213722680,0sleep30-21swapper/312:00:135
2195626756,9sleep00-21swapper/007:08:390
2180126654,10sleep50-21swapper/507:06:187
2178126655,9sleep110-21swapper/1107:06:013
2176426654,10sleep70-21swapper/707:05:459
2003026553,9sleep60-21swapper/607:05:198
230662610,0sleep20-21swapper/212:00:244
147022610,0sleep90-21swapper/907:40:1311
2184125746,9sleep40-21swapper/407:06:546
133762570,0sleep50-21swapper/509:45:007
2247799243,16cyclictest0-21swapper/412:30:006
2251399210,4cyclictest0-21swapper/1107:39:553
2247799212,15cyclictest0-21swapper/409:00:016
2247799212,14cyclictest0-21swapper/410:20:006
2247299213,11cyclictest0-21swapper/307:10:005
2250499203,10cyclictest0-21swapper/907:15:0111
8312190,0sleep5833-21sed11:35:007
275991170,0ptp4l0-21swapper/111:15:131
2247299173,8cyclictest0-21swapper/310:50:265
2246899173,9cyclictest0-21swapper/210:25:014
2246899173,10cyclictest0-21swapper/211:50:004
2246899170,16cyclictest0-21swapper/212:10:194
275991160,0ptp4l0-21swapper/111:00:201
275991160,0ptp4l0-21swapper/108:45:241
267652160,0sleep9681rcuc/909:20:0111
2250499163,8cyclictest0-21swapper/912:05:2511
2250499162,9cyclictest0-21swapper/909:55:0011
2246899163,8cyclictest0-21swapper/211:40:004
2246899163,8cyclictest0-21swapper/210:55:004
2246899163,8cyclictest0-21swapper/209:10:014
169922160,0sleep30-21swapper/310:30:155
275991150,1ptp4l21-21ksoftirqd/112:10:271
275991150,1ptp4l21-21ksoftirqd/111:55:161
275991150,1ptp4l21-21ksoftirqd/108:55:201
275991150,0ptp4l0-21swapper/112:35:201
275991150,0ptp4l0-21swapper/111:20:201
275991150,0ptp4l0-21swapper/109:00:201
275991150,0ptp4l0-21swapper/108:35:271
2250099152,8cyclictest0-21swapper/811:55:0010
2247299154,7cyclictest0-21swapper/307:25:015
2247299152,8cyclictest0-21swapper/311:55:005
2247299152,8cyclictest0-21swapper/308:15:005
2247299152,7cyclictest0-21swapper/310:50:005
2247299152,7cyclictest0-21swapper/307:20:015
2246899153,8cyclictest0-21swapper/208:40:344
2246899153,7cyclictest0-21swapper/211:55:234
2246899153,7cyclictest0-21swapper/210:50:004
2246899153,7cyclictest0-21swapper/210:00:254
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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