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2026-01-22 - 06:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8s.osadl.org (updated Thu Jan 22, 2026 00:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2834911010,93ptp4l0-21swapper/119:06:541
94080960,90rtkit-daemon0-21swapper/1019:05:032
39627666,8sleep50-21swapper/519:08:447
42927160,9sleep110-21swapper/1119:09:143
48126755,10sleep60-21swapper/619:09:568
3108526755,9sleep40-21swapper/419:05:196
3275526654,10sleep70-21swapper/719:07:099
3266726654,10sleep00-21swapper/019:05:500
108392520,0sleep10-21swapper/120:00:201
67272490,0sleep00-21swapper/022:45:110
172022470,0sleep110-21swapper/1123:00:003
97599230,17cyclictest0-21swapper/1020:14:562
93399202,14cyclictest0-21swapper/422:50:016
93399202,14cyclictest0-21swapper/421:40:006
95199191,2cyclictest0-21swapper/723:00:169
91299193,10cyclictest0-21swapper/121:50:011
91299192,11cyclictest0-21swapper/123:35:001
975991810,1cyclictest741rcuc/1022:32:192
92999180,17cyclictest0-21swapper/320:20:165
98299170,16cyclictest0-21swapper/1100:10:153
97199173,9cyclictest0-21swapper/920:40:0111
95199173,8cyclictest0-21swapper/700:29:599
92999172,9cyclictest0-21swapper/322:10:005
91299173,8cyclictest0-21swapper/121:20:011
91299173,8cyclictest0-21swapper/121:20:001
283491170,0ptp4l0-21swapper/122:30:171
98299162,7cyclictest0-21swapper/1123:50:003
98299161,8cyclictest0-21swapper/1121:35:013
98299161,8cyclictest0-21swapper/1121:35:003
97199162,8cyclictest0-21swapper/920:25:0011
95199162,10cyclictest0-21swapper/723:25:019
95199161,9cyclictest0-21swapper/720:25:019
93899164,7cyclictest0-21swapper/520:40:007
92999163,8cyclictest0-21swapper/323:35:015
92999162,9cyclictest0-21swapper/322:35:005
91299161,14cyclictest0-21swapper/123:35:161
283491160,1ptp4l21-21ksoftirqd/121:35:121
283491160,0ptp4l0-21swapper/119:45:111
98299152,8cyclictest0-21swapper/1100:30:003
97199152,8cyclictest0-21swapper/923:50:0111
95199153,8cyclictest0-21swapper/721:25:009
95199153,8cyclictest0-21swapper/721:25:009
93899154,7cyclictest0-21swapper/500:40:007
93899153,8cyclictest0-21swapper/523:45:007
93899153,7cyclictest0-21swapper/522:10:007
92999152,8cyclictest0-21swapper/321:55:015
92999152,8cyclictest0-21swapper/300:20:015
92999152,7cyclictest0-21swapper/322:25:015
91299152,8cyclictest9955-21kworker/u24:200:24:591
3852157,6sleep80-21swapper/819:08:3410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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