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2026-02-26 - 08:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8s.osadl.org (updated Thu Feb 26, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2834911080,57ptp4l0-21swapper/119:06:391
94080990,94rtkit-daemon0-21swapper/419:08:416
1044527254,9sleep00-21swapper/019:07:240
1043927159,10sleep70-21swapper/719:07:209
1051026856,10sleep110-21swapper/1119:08:233
1032626757,8sleep50-21swapper/519:05:407
1042926656,8sleep100-21swapper/1019:07:102
1034026554,9sleep60-21swapper/619:05:538
97342520,0sleep80-21swapper/821:10:2010
106442410,0sleep10-21swapper/121:10:491
111762370,0sleep80-21swapper/819:50:1110
1104499192,11cyclictest0-21swapper/1121:10:023
179952180,0sleep60-21swapper/622:05:128
1102899183,9cyclictest0-21swapper/821:10:0110
1100199183,10cyclictest0-21swapper/219:40:004
1099199185,8cyclictest0-21swapper/022:10:000
1099199184,8cyclictest0-21swapper/019:15:010
1102899173,8cyclictest0-21swapper/820:25:2210
1102899172,9cyclictest0-21swapper/819:50:0110
1102499174,8cyclictest0-21swapper/720:00:019
1100199173,9cyclictest0-21swapper/222:55:004
1100199173,8cyclictest0-21swapper/200:15:004
1100199172,10cyclictest0-21swapper/220:30:014
1099199172,9cyclictest0-21swapper/020:15:010
283491160,1ptp4l21-21ksoftirqd/122:25:001
283491160,1ptp4l21-21ksoftirqd/119:55:181
283491160,1ptp4l21-21ksoftirqd/119:30:121
283491160,1ptp4l21-21ksoftirqd/100:35:161
1104499162,10cyclictest0-21swapper/1120:10:013
1102899162,9cyclictest0-21swapper/819:35:0210
1102499160,15cyclictest0-21swapper/719:10:179
1101999163,7cyclictest0-21swapper/621:25:018
1101999162,9cyclictest0-21swapper/620:15:018
1101999162,8cyclictest0-21swapper/623:10:008
1101499162,8cyclictest0-21swapper/500:20:007
1101499161,11cyclictest6144-21kworker/u24:023:35:007
1099599163,8cyclictest0-21swapper/123:20:001
1099199163,8cyclictest0-21swapper/023:01:410
1099199163,8cyclictest0-21swapper/000:00:010
1099199162,9cyclictest0-21swapper/021:05:010
104402167,7sleep80-21swapper/819:07:2110
283491150,1ptp4l21-21ksoftirqd/122:55:151
283491150,1ptp4l21-21ksoftirqd/122:05:241
283491150,1ptp4l21-21ksoftirqd/121:20:011
283491150,1ptp4l21-21ksoftirqd/121:05:131
1104499153,8cyclictest0-21swapper/1120:35:013
1102899153,7cyclictest0-21swapper/819:25:0110
1102899150,14cyclictest0-21swapper/800:00:1710
1102499153,8cyclictest0-21swapper/700:00:009
1102499153,7cyclictest0-21swapper/721:25:239
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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