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2025-10-22 - 20:33

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8s.osadl.org (updated Wed Oct 22, 2025 12:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1319321010,0sleep40-21swapper/408:40:176
94980940,89rtkit-daemon0-21swapper/007:09:090
275991930,83ptp4l0-21swapper/107:08:391
397927764,10sleep50-21swapper/507:05:217
551526858,8sleep110-21swapper/1107:07:403
545826751,6sleep100-21swapper/1007:06:512
551126453,9sleep70-21swapper/707:07:369
538526355,6sleep40-21swapper/407:05:446
550826152,6sleep60-21swapper/607:07:348
182912600,0sleep90-21swapper/912:15:2311
289452590,0sleep60-21swapper/611:05:248
177432560,0sleep50-21swapper/509:30:017
608599290,1cyclictest0-21swapper/1011:20:252
604999213,12cyclictest0-21swapper/212:05:004
604999203,10cyclictest0-21swapper/207:15:014
608099190,18cyclictest0-21swapper/911:20:1911
607199191,17cyclictest0-21swapper/709:40:189
605899191,8cyclictest0-21swapper/410:35:006
604999193,11cyclictest0-21swapper/210:10:004
604999193,10cyclictest0-21swapper/209:15:014
215662190,0sleep30-21swapper/308:10:145
6089991816,1cyclictest0-21swapper/1112:40:003
604999183,9cyclictest0-21swapper/208:45:004
604099182,7cyclictest0-21swapper/012:15:240
608099172,10cyclictest0-21swapper/911:10:0011
607699173,9cyclictest0-21swapper/812:09:5910
607199173,9cyclictest0-21swapper/710:00:009
607199173,9cyclictest0-21swapper/707:55:009
605899172,14cyclictest0-21swapper/407:45:016
604499173,9cyclictest0-21swapper/107:35:011
604099173,9cyclictest0-21swapper/008:30:010
110312170,0sleep100-21swapper/1011:25:192
608099162,9cyclictest0-21swapper/911:44:5911
607699162,9cyclictest0-21swapper/809:00:0110
607199162,8cyclictest0-21swapper/711:35:009
606799162,8cyclictest0-21swapper/607:50:018
605899163,9cyclictest0-21swapper/411:50:006
604999163,8cyclictest0-21swapper/210:54:594
604499162,8cyclictest0-21swapper/108:05:011
604499162,7cyclictest0-21swapper/109:30:011
604499161,14cyclictest0-21swapper/110:35:181
275991160,1ptp4l21-21ksoftirqd/111:44:591
275991160,1ptp4l21-21ksoftirqd/110:50:131
275991160,1ptp4l21-21ksoftirqd/107:50:121
608999152,8cyclictest0-21swapper/1109:15:013
608099153,8cyclictest0-21swapper/912:40:0111
608099153,8cyclictest0-21swapper/910:55:0011
608099152,8cyclictest0-21swapper/911:30:0011
608099152,8cyclictest0-21swapper/907:40:0111
607699152,8cyclictest0-21swapper/811:04:5910
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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