You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-05 - 07:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8s.osadl.org (updated Thu Feb 05, 2026 00:44:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2834911330,124ptp4l0-21swapper/119:08:211
1867627154,9sleep50-21swapper/519:09:367
1858727160,9sleep110-21swapper/1119:08:173
1853226756,9sleep100-21swapper/1019:07:282
1862126654,10sleep40-21swapper/419:08:476
1869126553,10sleep70-21swapper/719:09:509
1840026554,9sleep00-21swapper/019:05:310
1488926451,10sleep60-21swapper/619:05:018
296832500,0sleep111009-21runrttasks20:45:143
1914399191,17cyclictest0-21swapper/1122:30:173
1910999194,9cyclictest0-21swapper/521:25:017
1909699193,10cyclictest0-21swapper/200:00:014
1909699183,9cyclictest0-21swapper/223:20:014
1909699183,9cyclictest0-21swapper/223:20:004
283491170,0ptp4l0-21swapper/120:15:131
1908699173,9cyclictest0-21swapper/022:25:010
1908699173,8cyclictest0-21swapper/023:30:010
1908699173,8cyclictest0-21swapper/023:30:010
283491160,0ptp4l0-21swapper/122:55:181
283491160,0ptp4l0-21swapper/120:35:141
283491160,0ptp4l0-21swapper/119:45:131
1909699163,9cyclictest0-21swapper/220:45:004
1909699163,8cyclictest0-21swapper/221:15:014
283491150,1ptp4l21-21ksoftirqd/120:55:241
283491150,1ptp4l21-21ksoftirqd/119:20:181
1911499153,7cyclictest0-21swapper/620:25:008
1909699153,7cyclictest0-21swapper/221:10:294
1909699152,8cyclictest0-21swapper/223:00:004
1909699151,9cyclictest0-21swapper/200:30:014
1908699154,7cyclictest30881-21kworker/u24:023:05:010
1908699152,7cyclictest0-21swapper/020:50:250
283491140,6ptp4l21-21ksoftirqd/122:05:131
283491140,1ptp4l21-21ksoftirqd/122:20:011
283491140,0ptp4l0-21swapper/120:50:131
1912399142,8cyclictest0-21swapper/819:35:0010
1912399142,7cyclictest0-21swapper/823:30:0110
1912399142,7cyclictest0-21swapper/823:30:0110
1911499142,7cyclictest0-21swapper/600:30:008
1910999142,7cyclictest0-21swapper/520:35:007
1910999141,7cyclictest0-21swapper/500:25:007
1909699142,8cyclictest0-21swapper/220:15:014
1909699142,5cyclictest0-21swapper/200:35:124
314822130,0sleep70-21swapper/723:35:179
283491130,1ptp4l21-21ksoftirqd/123:23:351
283491130,1ptp4l21-21ksoftirqd/123:23:341
283491130,1ptp4l21-21ksoftirqd/120:07:011
283491130,1ptp4l21-21ksoftirqd/119:26:341
283491130,0ptp4l0-21swapper/123:40:191
283491130,0ptp4l0-21swapper/121:15:181
1912399133,6cyclictest0-21swapper/800:15:0110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional