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2026-03-13 - 18:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot1.osadl.org (updated Fri Mar 13, 2026 12:45:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
145262200156,21sleep30-21swapper/307:09:563
144782200160,26sleep20-21swapper/207:09:192
144712200162,24sleep00-21swapper/007:09:130
144102196160,23sleep10-21swapper/107:08:251
75162690,0sleep00-21swapper/011:12:340
246932250,1sleep228-21ksoftirqd/207:27:202
219162190,0sleep20-21swapper/210:08:002
14644991412,1cyclictest28-21ksoftirqd/208:55:002
14644991311,1cyclictest28-21ksoftirqd/210:50:002
14644991311,1cyclictest28-21ksoftirqd/208:30:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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