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2024-06-09 - 03:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot1.osadl.org (updated Sun Jun 09, 2024 00:45:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
266812234158,25sleep20-21swapper/219:09:432
266372214173,27sleep00-21swapper/019:09:100
264642199162,24sleep10-21swapper/119:06:541
265012198160,24sleep30-21swapper/319:07:243
56812140,1sleep35682-21pmu-power00:35:263
2680799140,13cyclictest15316-21/usr/sbin/munin23:20:132
2680799130,12cyclictest0-21swapper/220:10:092
2680299130,12cyclictest0-21swapper/120:10:201
26807991211,1cyclictest28-21ksoftirqd/221:00:012
2681499118,1cyclictest35-21ksoftirqd/321:20:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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