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2025-05-09 - 05:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot1.osadl.org (updated Fri May 09, 2025 00:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
172082210142,54sleep30-21swapper/319:06:513
174332203164,26sleep20-21swapper/219:09:482
171902198160,25sleep00-21swapper/019:06:350
172832197160,24sleep10-21swapper/119:07:491
48042690,0sleep20-21swapper/200:26:182
264792620,0sleep20-21swapper/222:50:182
327152600,1sleep121-21ksoftirqd/100:20:211
17541991514,1cyclictest28-21ksoftirqd/223:21:292
293082130,1sleep00-21swapper/000:16:080
17547991312,1cyclictest35-21ksoftirqd/319:45:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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