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2026-01-27 - 11:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot1.osadl.org (updated Tue Jan 27, 2026 00:45:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
147552220159,47sleep30-21swapper/319:06:383
148012201160,27sleep20-21swapper/219:07:132
148362199160,25sleep00-21swapper/019:07:400
147582197158,26sleep10-21swapper/119:06:401
137382660,0sleep30-21swapper/323:57:383
289932580,0sleep20-21swapper/223:35:192
191132420,0sleep20-21swapper/219:15:152
1511699177,9cyclictest28-21ksoftirqd/223:30:102
221002130,0sleep10-21swapper/119:20:181
15123991311,1cyclictest35-21ksoftirqd/321:00:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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