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2026-07-27 - 13:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot1.osadl.org (updated Mon Jul 27, 2026 00:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201952207158,24sleep00-21swapper/019:07:080
203472202162,26sleep30-21swapper/319:09:083
202342202161,26sleep20-21swapper/219:07:382
202112201165,23sleep10-21swapper/119:07:221
115642660,0sleep20-21swapper/221:05:142
20512991311,1cyclictest28-21ksoftirqd/219:15:012
2051299130,1cyclictest0-21swapper/200:28:002
265092120,0sleep20-21swapper/223:44:062
2051299125,3cyclictest61650irq/122-eno123:05:362
2049899120,0cyclictest0-21swapper/019:50:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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