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2026-02-16 - 07:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack1slot1.osadl.org (updated Mon Feb 16, 2026 00:45:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
186852217150,23sleep20-21swapper/219:08:592
187552208170,24sleep00-21swapper/019:09:530
187562203149,42sleep10-21swapper/119:09:541
186812199160,26sleep30-21swapper/319:08:563
196092660,0sleep10-21swapper/121:19:531
126752610,1sleep3341rcuc/323:54:503
59362160,0sleep30-21swapper/323:05:123
18862991413,1cyclictest28-21ksoftirqd/223:40:172
18862991412,1cyclictest28-21ksoftirqd/219:50:202
18857991413,1cyclictest9-21ksoftirqd/020:55:000
18862991313,0cyclictest28-21ksoftirqd/221:45:212
18862991311,1cyclictest28-21ksoftirqd/223:35:002
18862991311,1cyclictest28-21ksoftirqd/223:00:002
18862991311,1cyclictest28-21ksoftirqd/221:05:192
18857991311,1cyclictest9-21ksoftirqd/000:00:000
18862991211,1cyclictest28-21ksoftirqd/220:45:002
18862991211,1cyclictest28-21ksoftirqd/220:10:212
18862991211,1cyclictest28-21ksoftirqd/220:10:202
18862991211,1cyclictest28-21ksoftirqd/219:30:162
18862991210,1cyclictest28-21ksoftirqd/223:20:172
18862991210,1cyclictest28-21ksoftirqd/222:05:182
18862991210,1cyclictest28-21ksoftirqd/221:00:002
18862991210,1cyclictest28-21ksoftirqd/220:25:142
18862991210,1cyclictest28-21ksoftirqd/219:25:152
18857991210,2cyclictest9-21ksoftirqd/023:20:140
18857991210,1cyclictest26440-21sshd19:23:120
1886299119,1cyclictest28-21ksoftirqd/223:05:132
18862991110,1cyclictest28-21ksoftirqd/219:55:132
1885799119,1cyclictest9-21ksoftirqd/000:15:170
18857991110,1cyclictest9-21ksoftirqd/023:10:000
18857991110,1cyclictest9-21ksoftirqd/020:45:000
18857991110,1cyclictest9-21ksoftirqd/000:39:590
12772110,8sleep335-21ksoftirqd/320:45:193
1887099109,1cyclictest35-21ksoftirqd/323:35:213
1886299109,1cyclictest28-21ksoftirqd/223:25:132
1886299109,1cyclictest28-21ksoftirqd/223:15:142
1886299109,1cyclictest28-21ksoftirqd/223:10:022
1886299109,1cyclictest28-21ksoftirqd/223:05:002
1886299109,1cyclictest28-21ksoftirqd/222:15:102
1886299109,1cyclictest28-21ksoftirqd/221:19:202
1886299109,1cyclictest28-21ksoftirqd/220:45:112
1886299109,1cyclictest28-21ksoftirqd/220:20:192
1886299109,1cyclictest28-21ksoftirqd/220:05:132
1886299109,1cyclictest28-21ksoftirqd/219:40:002
1886299109,1cyclictest28-21ksoftirqd/200:35:192
1886299108,1cyclictest28-21ksoftirqd/223:50:002
1886299108,1cyclictest28-21ksoftirqd/222:45:212
1886299108,1cyclictest28-21ksoftirqd/221:21:162
1886299107,2cyclictest28-21ksoftirqd/222:25:002
18862991010,0cyclictest28-21ksoftirqd/223:55:182
18862991010,0cyclictest28-21ksoftirqd/221:30:112
1885899100,0cyclictest0-21swapper/100:33:431
1885799109,1cyclictest9-21ksoftirqd/022:40:140
1885799108,1cyclictest11685-21diskmemload21:44:080
27793290,0sleep10-21swapper/100:12:521
188709990,7cyclictest0-21swapper/322:38:013
188629998,1cyclictest28-21ksoftirqd/222:50:112
188629998,1cyclictest28-21ksoftirqd/222:40:212
188629998,1cyclictest28-21ksoftirqd/222:25:162
188629998,1cyclictest28-21ksoftirqd/221:28:502
188629998,1cyclictest28-21ksoftirqd/221:10:122
188629998,1cyclictest28-21ksoftirqd/220:50:102
188629998,1cyclictest28-21ksoftirqd/220:05:002
188629998,1cyclictest28-21ksoftirqd/219:15:142
188629998,1cyclictest28-21ksoftirqd/200:30:222
188629998,1cyclictest28-21ksoftirqd/200:00:122
188629997,1cyclictest28-21ksoftirqd/222:35:112
188629997,1cyclictest28-21ksoftirqd/221:40:182
188629997,1cyclictest28-21ksoftirqd/200:25:002
188629997,1cyclictest28-21ksoftirqd/200:10:002
188579998,1cyclictest9-21ksoftirqd/023:55:000
188579998,1cyclictest9-21ksoftirqd/021:50:210
188579998,1cyclictest9-21ksoftirqd/021:25:130
188579998,1cyclictest9-21ksoftirqd/021:15:110
188579998,0cyclictest9-21ksoftirqd/000:30:180
188579997,1cyclictest9-21ksoftirqd/019:50:000
188579997,1cyclictest9-21ksoftirqd/019:35:120
188579995,1cyclictest18490-21diskstats20:15:120
188579990,0cyclictest11685-21diskmemload21:38:410
188709986,1cyclictest707-21snmpd23:11:193
188709986,1cyclictest707-21snmpd22:49:093
188709986,1cyclictest707-21snmpd21:45:113
188629987,1cyclictest28-21ksoftirqd/223:40:002
188629987,1cyclictest28-21ksoftirqd/222:00:142
188629987,1cyclictest28-21ksoftirqd/221:55:002
188629987,1cyclictest28-21ksoftirqd/220:35:162
188629987,1cyclictest28-21ksoftirqd/220:15:122
188629987,1cyclictest28-21ksoftirqd/219:45:122
188629987,1cyclictest28-21ksoftirqd/200:15:152
188629987,1cyclictest28-21ksoftirqd/200:10:012
188629986,1cyclictest707-21snmpd20:31:232
188629986,1cyclictest28-21ksoftirqd/223:55:002
188629986,1cyclictest28-21ksoftirqd/222:30:152
188629986,1cyclictest28-21ksoftirqd/222:15:002
188629986,1cyclictest28-21ksoftirqd/221:55:122
188629986,1cyclictest28-21ksoftirqd/221:35:112
188629986,1cyclictest28-21ksoftirqd/221:00:122
188589980,4cyclictest0-21swapper/123:10:111
188579987,1cyclictest9-21ksoftirqd/023:25:130
188579987,1cyclictest9-21ksoftirqd/023:00:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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