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2026-08-12 - 06:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack1slot1.osadl.org (updated Wed Aug 12, 2026 00:45:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
273032215154,50sleep30-21swapper/319:09:163
271862206149,43sleep00-21swapper/019:07:440
271632200159,26sleep20-21swapper/219:07:252
273312199160,25sleep10-21swapper/119:09:381
44522590,0sleep10-21swapper/123:50:111
221222370,0sleep30-21swapper/300:15:013
169822220,0sleep10-21swapper/121:50:051
169822220,0sleep10-21swapper/121:50:041
79372180,0sleep10-21swapper/123:08:341
27459991612,4cyclictest21-21ksoftirqd/123:43:511
27459991612,4cyclictest21-21ksoftirqd/100:17:261
27459991511,0cyclictest111rcu_preempt21:40:421
274192150,0sleep30-21swapper/322:05:013
2747099130,10cyclictest548-21systemd-logind23:24:082
2745999130,13cyclictest56-21kworker/1:122:59:041
2745999130,13cyclictest0-21swapper/120:55:551
2745999120,12cyclictest0-21swapper/120:44:421
2745999120,12cyclictest0-21swapper/119:37:311
2745999120,0cyclictest0-21swapper/120:33:301
2745599123,4cyclictest8346-21cut20:45:000
27455991211,1cyclictest9-21ksoftirqd/022:40:140
27455991211,1cyclictest9-21ksoftirqd/021:20:200
27455991210,1cyclictest9-21ksoftirqd/022:25:100
2747099119,1cyclictest28-21ksoftirqd/221:05:002
27470991110,1cyclictest28-21ksoftirqd/222:00:192
27459991111,0cyclictest21-21ksoftirqd/121:25:081
2745999110,11cyclictest0-21swapper/122:36:391
2745999110,0cyclictest0-21swapper/123:32:391
2745999110,0cyclictest0-21swapper/122:47:521
2745999110,0cyclictest0-21swapper/121:07:061
2745599119,1cyclictest9-21ksoftirqd/020:20:010
27455991110,1cyclictest9-21ksoftirqd/021:45:200
27455991110,1cyclictest9-21ksoftirqd/021:40:000
27455991110,1cyclictest9-21ksoftirqd/000:00:160
46962100,0sleep10-21swapper/122:17:021
2747399100,4cyclictest0-21swapper/321:55:123
2747099109,1cyclictest28-21ksoftirqd/220:00:002
2747099108,1cyclictest28-21ksoftirqd/223:31:502
2747099108,1cyclictest28-21ksoftirqd/222:15:152
2747099100,9cyclictest0-21swapper/223:46:522
2747099100,6cyclictest21775-21/usr/sbin/munin21:10:212
2747099100,10cyclictest0-21swapper/200:01:432
2745999108,1cyclictest21-21ksoftirqd/122:10:121
2745999108,1cyclictest21-21ksoftirqd/121:05:001
2745999102,7cyclictest111rcu_preempt21:39:101
2745999101,8cyclictest111rcu_preempt00:37:161
2745999101,7cyclictest21-21ksoftirqd/120:50:191
2745999100,8cyclictest21-21ksoftirqd/100:00:221
2745999100,0cyclictest0-21swapper/123:55:011
2745999100,0cyclictest0-21swapper/123:21:261
2745999100,0cyclictest0-21swapper/122:25:311
2745999100,0cyclictest0-21swapper/122:03:071
2745999100,0cyclictest0-21swapper/119:59:561
2745599109,1cyclictest9-21ksoftirqd/021:10:210
2745599108,1cyclictest9-21ksoftirqd/021:00:010
2745599108,1cyclictest32444-21ls00:29:590
2745599103,4cyclictest5728-21sed22:19:590
2745599102,4cyclictest7667-21perf23:55:000
274739996,2cyclictest11301-21snmpd21:04:363
274739990,6cyclictest0-21swapper/323:48:323
274709998,1cyclictest28-21ksoftirqd/221:24:592
274709998,1cyclictest28-21ksoftirqd/220:00:172
274709998,0cyclictest28-21ksoftirqd/200:30:222
274599999,0cyclictest21-21ksoftirqd/121:59:581
274599998,1cyclictest21-21ksoftirqd/123:39:091
274599998,1cyclictest21-21ksoftirqd/123:15:481
274599998,1cyclictest21-21ksoftirqd/122:35:011
274599998,1cyclictest21-21ksoftirqd/121:45:451
274599998,1cyclictest21-21ksoftirqd/121:23:401
274599998,1cyclictest21-21ksoftirqd/100:26:261
274599998,1cyclictest21-21ksoftirqd/100:11:041
274599995,3cyclictest21-21ksoftirqd/119:10:111
274599995,3cyclictest21-21ksoftirqd/119:10:101
274599994,4cyclictest111rcu_preempt23:10:191
274599991,1cyclictest21-21ksoftirqd/100:30:171
274599991,1cyclictest111rcu_preempt19:45:111
274599991,1cyclictest111rcu_preempt00:24:011
274599990,8cyclictest21-21ksoftirqd/121:15:331
274599990,8cyclictest111rcu_preempt22:51:151
274599990,8cyclictest111rcu_preempt20:10:181
274599990,0cyclictest0-21swapper/120:22:191
274559999,0cyclictest9-21ksoftirqd/023:15:000
274559998,1cyclictest9-21ksoftirqd/022:55:200
274559998,1cyclictest9-21ksoftirqd/022:01:570
274559998,1cyclictest9-21ksoftirqd/020:00:160
274559997,1cyclictest9-21ksoftirqd/022:20:130
274559997,1cyclictest9-21ksoftirqd/021:00:000
274559997,1cyclictest9-21ksoftirqd/000:35:140
274559996,1cyclictest9-21ksoftirqd/019:20:000
274559993,5cyclictest648-21perf23:44:590
274559993,5cyclictest25493-21date00:20:010
274559991,4cyclictest8432-21perf23:10:000
274739986,1cyclictest14067-21hwlatdetect20:55:153
274739986,1cyclictest11301-21snmpd00:30:003
274739986,1cyclictest11301-21snmpd00:07:303
274739983,2cyclictest20099-21diskmemload23:17:103
274739982,3cyclictest30872-21cat23:40:193
274739980,7cyclictest29057-21kworker/u8:122:58:363
274739980,7cyclictest0-21swapper/322:26:263
274709988,0cyclictest28-21ksoftirqd/220:20:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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