You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-08 - 10:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack1slot1.osadl.org (updated Sun Mar 08, 2026 00:45:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
250822220147,57sleep00-21swapper/019:06:040
253482212173,25sleep20-21swapper/219:09:312
250732201162,25sleep30-21swapper/319:05:583
252262198161,24sleep10-21swapper/119:07:571
185202680,0sleep10-21swapper/123:11:031
102882670,0sleep10-21swapper/122:20:131
242312570,0sleep30-21swapper/322:37:203
246662160,0sleep00-21swapper/021:15:440
240272150,0sleep10-21swapper/123:20:001
25469991414,0cyclictest28-21ksoftirqd/223:43:162
2546599140,13cyclictest0-21swapper/123:45:171
2546599140,13cyclictest0-21swapper/122:40:201
2546599140,13cyclictest0-21swapper/122:35:141
2546599140,13cyclictest0-21swapper/119:40:011
2546599140,0cyclictest0-21swapper/122:50:111
25459991411,2cyclictest9-21ksoftirqd/000:15:100
25469991313,0cyclictest28-21ksoftirqd/200:19:322
25469991312,1cyclictest28-21ksoftirqd/222:47:032
25469991312,1cyclictest28-21ksoftirqd/219:15:002
2546599130,13cyclictest0-21swapper/123:35:151
2546599130,13cyclictest0-21swapper/120:30:151
2546599130,13cyclictest0-21swapper/100:20:341
2546599130,12cyclictest0-21swapper/121:05:191
2546599130,12cyclictest0-21swapper/120:05:181
2546599130,0cyclictest0-21swapper/122:20:001
2546599130,0cyclictest0-21swapper/121:45:121
2546599130,0cyclictest0-21swapper/121:45:111
2546599130,0cyclictest0-21swapper/100:26:581
25459991311,1cyclictest9-21ksoftirqd/023:15:000
25459991311,1cyclictest9-21ksoftirqd/020:10:000
2546999128,3cyclictest28-21ksoftirqd/222:24:212
2546999123,6cyclictest548-21systemd-logind00:00:212
25469991211,1cyclictest28-21ksoftirqd/219:15:142
25469991210,1cyclictest28-21ksoftirqd/222:55:212
2546599120,12cyclictest0-21swapper/123:50:171
2546599120,12cyclictest0-21swapper/122:10:341
2546599120,12cyclictest0-21swapper/121:35:001
2546599120,11cyclictest0-21swapper/123:25:201
2546599120,11cyclictest0-21swapper/121:41:051
2546599120,11cyclictest0-21swapper/119:25:161
2546599120,0cyclictest0-21swapper/123:43:261
2546599120,0cyclictest0-21swapper/123:07:331
2546599120,0cyclictest0-21swapper/121:27:041
2546599120,0cyclictest0-21swapper/100:37:521
2546599120,0cyclictest0-21swapper/100:37:521
2546599120,0cyclictest0-21swapper/100:02:231
25459991210,1cyclictest9-21ksoftirqd/023:30:000
2545999120,12cyclictest0-21swapper/021:00:120
2546999119,1cyclictest3550-21hddtemp_smartct21:30:142
25469991111,0cyclictest28-21ksoftirqd/221:42:462
25469991111,0cyclictest28-21ksoftirqd/200:06:122
25469991110,1cyclictest28-21ksoftirqd/223:15:132
25469991110,1cyclictest28-21ksoftirqd/223:15:002
25469991110,1cyclictest28-21ksoftirqd/222:15:162
25469991110,1cyclictest28-21ksoftirqd/200:35:172
25469991110,1cyclictest28-21ksoftirqd/200:35:162
2546999110,7cyclictest27347-21ls20:19:592
2546599110,11cyclictest0-21swapper/121:00:001
2546599110,11cyclictest0-21swapper/120:20:161
2546599110,11cyclictest0-21swapper/119:15:181
2546599110,10cyclictest0-21swapper/119:55:191
2546599110,0cyclictest0-21swapper/123:03:441
2546599110,0cyclictest0-21swapper/122:09:221
2546599110,0cyclictest0-21swapper/122:04:281
2546599110,0cyclictest0-21swapper/121:15:171
2546599110,0cyclictest0-21swapper/121:14:281
2546599110,0cyclictest0-21swapper/120:46:491
2546599110,0cyclictest0-21swapper/100:15:191
2546599110,0cyclictest0-21swapper/100:05:141
25459991110,1cyclictest9-21ksoftirqd/023:50:140
2545999111,5cyclictest14878-21perf23:50:010
2546999109,1cyclictest28-21ksoftirqd/223:55:152
2546999109,1cyclictest28-21ksoftirqd/222:10:202
2546999109,1cyclictest28-21ksoftirqd/219:50:142
2546999108,1cyclictest28-21ksoftirqd/222:25:182
2546599101,9cyclictest0-21swapper/123:55:141
2546599100,9cyclictest0-21swapper/123:23:221
2546599100,9cyclictest0-21swapper/122:26:551
2546599100,6cyclictest0-21swapper/120:37:041
2546599100,10cyclictest0-21swapper/122:46:361
2546599100,10cyclictest0-21swapper/121:54:431
2546599100,10cyclictest0-21swapper/121:37:301
2546599100,10cyclictest0-21swapper/121:20:181
2546599100,1cyclictest0-21swapper/122:58:341
2546599100,0cyclictest0-21swapper/100:30:571
2545999109,1cyclictest9-21ksoftirqd/023:15:170
2545999109,1cyclictest9-21ksoftirqd/022:25:120
2545999109,1cyclictest9-21ksoftirqd/000:35:140
2545999109,1cyclictest9-21ksoftirqd/000:35:140
2545999109,1cyclictest9-21ksoftirqd/000:35:000
2545999109,1cyclictest9-21ksoftirqd/000:20:100
2545999108,1cyclictest9-21ksoftirqd/021:45:010
254779997,1cyclictest35-21ksoftirqd/319:19:593
254779990,6cyclictest21715-21sendmail_mailst23:15:193
254699999,0cyclictest28-21ksoftirqd/223:48:102
254699999,0cyclictest28-21ksoftirqd/223:20:142
254699999,0cyclictest28-21ksoftirqd/222:02:112
254699999,0cyclictest28-21ksoftirqd/221:56:392
254699999,0cyclictest28-21ksoftirqd/220:30:172
254699998,1cyclictest28-21ksoftirqd/223:30:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional