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2025-12-17 - 08:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Wed Dec 17, 2025 00:45:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
106642203163,27sleep10-21swapper/119:08:341
104652201161,26sleep30-21swapper/319:05:593
104572201162,26sleep00-21swapper/019:05:520
104762199161,25sleep20-21swapper/219:06:062
240742200,1sleep024077-21uniq19:35:160
119252130,0sleep10-21swapper/123:40:181
10874991311,1cyclictest28-21ksoftirqd/219:15:012
10862991210,1cyclictest9-21ksoftirqd/023:45:000
1088399109,1cyclictest35-21ksoftirqd/320:20:013
1088399100,2cyclictest0-21swapper/323:05:123
1087499100,9cyclictest0-21swapper/200:30:202
1086299109,1cyclictest9-21ksoftirqd/020:40:180
1086299109,1cyclictest9-21ksoftirqd/020:40:000
1086299103,6cyclictest7428-21perf20:10:010
108839990,1cyclictest0-21swapper/320:10:133
108749998,1cyclictest28-21ksoftirqd/219:45:002
108749996,1cyclictest0-21swapper/223:29:242
108629998,1cyclictest9-21ksoftirqd/021:25:000
108629998,1cyclictest9-21ksoftirqd/000:00:000
108629998,0cyclictest9-21ksoftirqd/019:35:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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