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2026-02-21 - 03:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Sat Feb 21, 2026 00:45:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21162217152,21sleep00-21swapper/019:08:250
20752202159,28sleep10-21swapper/119:07:541
19212202164,24sleep20-21swapper/219:05:522
19472199159,26sleep30-21swapper/319:06:153
172752670,0sleep00-21swapper/019:40:000
24062580,0sleep00-21swapper/022:39:540
204052230,0sleep00-21swapper/023:42:450
325852150,0sleep00-21swapper/021:55:130
253812150,1sleep228-21ksoftirqd/219:55:152
232199144,5cyclictest4713-21cat19:15:010
232199144,5cyclictest4713-21cat19:15:000
2335991311,1cyclictest28-21ksoftirqd/200:15:002
2335991210,1cyclictest17666-21apt-get23:40:102
2321991210,1cyclictest9-21ksoftirqd/023:50:000
2321991210,1cyclictest9-21ksoftirqd/023:05:010
232199119,1cyclictest9-21ksoftirqd/000:29:590
232199113,4cyclictest8441-21perf00:10:010
232199113,4cyclictest7893-21perf21:25:010
232199113,4cyclictest26616-21latency_hist20:00:000
233999100,5cyclictest0-21swapper/300:30:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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