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2026-07-09 - 13:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Jul 09, 2026 00:45:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10852214149,51sleep00-21swapper/019:08:260
8582209158,25sleep30-21swapper/319:05:313
11532201163,25sleep10-21swapper/119:09:191
11072200159,27sleep20-21swapper/219:08:442
320922640,0sleep20-21swapper/223:29:122
284142170,0sleep20-21swapper/200:07:292
92322160,0sleep10-21swapper/122:13:281
131599144,1cyclictest5077-21ssh21:24:273
130799130,13cyclictest0-21swapper/221:37:082
131599120,2cyclictest0-21swapper/300:34:383
1286991211,1cyclictest9-21ksoftirqd/023:25:150
1286991210,1cyclictest9-21ksoftirqd/023:35:010
76122110,0sleep00-21swapper/021:26:020
130799116,1cyclictest61650irq/122-eno122:21:072
130799116,1cyclictest61650irq/122-eno122:21:072
130799116,0cyclictest61650irq/122-eno122:40:172
130799115,1cyclictest61650irq/122-eno123:10:182
130799111,9cyclictest26576-21diskmemload22:00:212
128699119,1cyclictest9-21ksoftirqd/019:30:000
128699113,4cyclictest2881-21perf22:49:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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