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2026-04-18 - 00:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Fri Apr 17, 2026 12:45:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
252552213149,21sleep00-21swapper/007:06:530
252552213149,21sleep00-21swapper/007:06:520
253822204155,23sleep30-21swapper/307:08:333
253822204155,23sleep30-21swapper/307:08:333
253092200161,25sleep20-21swapper/207:07:342
253092200161,25sleep20-21swapper/207:07:342
253482198160,25sleep10-21swapper/107:08:071
253482198160,25sleep10-21swapper/107:08:061
166362680,0sleep10-21swapper/109:46:061
229202610,0sleep20-21swapper/212:02:122
229862550,0sleep30-21swapper/310:38:093
305892190,0sleep10-21swapper/111:30:151
327352170,0sleep30-21swapper/312:15:143
25579991413,1cyclictest9-21ksoftirqd/010:25:110
25587991312,1cyclictest0-21swapper/109:15:151
2557999132,5cyclictest31832-21perf08:30:000
25579991312,1cyclictest9-21ksoftirqd/012:25:000
25605991210,1cyclictest35-21ksoftirqd/308:20:003
25605991210,1cyclictest35-21ksoftirqd/307:40:003
25600991211,1cyclictest0-21swapper/211:55:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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