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2026-03-19 - 20:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Mar 19, 2026 12:45:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
141112212148,51sleep00-21swapper/007:07:520
141122210178,21sleep10-21swapper/107:07:531
140812200162,25sleep20-21swapper/207:07:302
140152199160,26sleep30-21swapper/307:06:393
310892610,0sleep121-21ksoftirqd/111:44:521
187102180,0sleep20-21swapper/210:05:122
297592160,0sleep10-21swapper/110:19:131
1439099134,3cyclictest35-21ksoftirqd/310:10:133
14382991210,1cyclictest28-21ksoftirqd/207:20:002
1438299120,11cyclictest0-21swapper/208:40:212
1438299119,1cyclictest28-21ksoftirqd/210:25:002
1438299119,1cyclictest28-21ksoftirqd/209:15:012
14382991110,1cyclictest31163-21ssh11:01:342
1439099100,4cyclictest19723-21aten_r1power_po11:30:103
1436299101,4cyclictest6386-21/usr/sbin/munin08:00:010
1436299101,4cyclictest6386-21/usr/sbin/munin08:00:010
143909998,1cyclictest35-21ksoftirqd/311:50:003
143909998,1cyclictest15072-21sh09:19:593
143909993,5cyclictest18424-21kworker/u8:112:36:513
143829998,1cyclictest28-21ksoftirqd/210:35:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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