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2026-01-27 - 00:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Mon Jan 26, 2026 12:45:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6142237162,60sleep20-21swapper/207:08:552
4352211156,43sleep10-21swapper/107:06:531
4922201162,25sleep30-21swapper/307:07:393
4242196157,25sleep00-21swapper/007:06:440
161652540,0sleep20-21swapper/211:38:152
241622140,1sleep079099cyclictest11:07:450
796991312,1cyclictest28-21ksoftirqd/209:40:002
79399139,4cyclictest56-21kworker/1:108:46:391
79399139,0cyclictest56-21kworker/1:108:35:301
793991310,3cyclictest21-21ksoftirqd/110:05:021
808991210,1cyclictest35-21ksoftirqd/307:55:003
79699120,12cyclictest0-21swapper/207:25:192
79399128,4cyclictest56-21kworker/1:109:53:501
79399128,4cyclictest21-21ksoftirqd/112:08:111
793991212,0cyclictest21-21ksoftirqd/109:25:131
80899119,1cyclictest35-21ksoftirqd/309:20:143
79399110,10cyclictest0-21swapper/108:30:111
79099119,1cyclictest9-21ksoftirqd/008:15:000
79099114,3cyclictest6211-21perf07:20:000
80899108,1cyclictest35-21ksoftirqd/311:55:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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