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2026-05-14 - 05:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu May 14, 2026 00:45:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
105992213178,23sleep00-21swapper/019:05:560
105592213150,49sleep20-21swapper/219:05:252
106892202163,25sleep10-21swapper/119:07:051
87992201161,26sleep30-21swapper/319:05:063
182192750,0sleep10-21swapper/122:53:131
215882730,1sleep121-21ksoftirqd/122:15:121
12552720,0sleep10-21swapper/122:30:151
287582670,0sleep00-21swapper/019:45:130
249812660,0sleep10-21swapper/123:45:151
294682170,0sleep00-21swapper/022:25:130
1100199130,13cyclictest56-21kworker/1:123:08:261
1100199130,0cyclictest56-21kworker/1:120:09:181
1100199130,0cyclictest56-21kworker/1:120:09:181
1102499121,10cyclictest30299-21taskset21:42:503
11001991210,1cyclictest111rcu_preempt21:14:441
1100199120,12cyclictest0-21swapper/120:31:411
1100199120,0cyclictest0-21swapper/119:24:311
1099399123,4cyclictest706-21latency_hist19:54:590
10993991210,1cyclictest9-21ksoftirqd/020:05:010
1101799119,1cyclictest28-21ksoftirqd/223:04:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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