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2026-04-24 - 03:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Fri Apr 24, 2026 00:45:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
207742232158,26sleep30-21swapper/319:06:023
208932221157,24sleep10-21swapper/119:07:331
208522215149,23sleep20-21swapper/219:07:022
208752213149,50sleep00-21swapper/019:07:200
206612620,1sleep32117299cyclictest23:24:393
21162580,0sleep30-21swapper/319:35:143
179302540,0sleep20-21swapper/221:55:182
136402180,0sleep20-21swapper/222:32:072
2116499144,7cyclictest10442-21kworker/2:022:17:362
2116499130,12cyclictest0-21swapper/223:44:442
21164991212,0cyclictest28-21ksoftirqd/223:12:302
21164991212,0cyclictest28-21ksoftirqd/221:17:252
21164991211,1cyclictest28-21ksoftirqd/222:09:592
21164991210,1cyclictest28-21ksoftirqd/200:05:142
21155991211,1cyclictest9-21ksoftirqd/023:54:590
21155991210,1cyclictest9-21ksoftirqd/021:45:000
21155991210,1cyclictest9-21ksoftirqd/000:15:000
21172991110,1cyclictest35-21ksoftirqd/322:55:003
21172991110,1cyclictest35-21ksoftirqd/321:40:013
21164991111,0cyclictest28-21ksoftirqd/200:29:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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