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2026-02-20 - 02:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Fri Feb 20, 2026 00:45:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157142208157,25sleep30-21swapper/319:09:093
154402199161,24sleep20-21swapper/219:05:322
155852198159,25sleep10-21swapper/119:07:261
154782198160,24sleep00-21swapper/019:06:040
179762610,0sleep20-21swapper/223:24:502
214122570,0sleep20-21swapper/223:28:382
126022570,0sleep10-21swapper/121:15:001
84642230,6sleep09-21ksoftirqd/020:00:140
1589799140,1cyclictest18419-21ls19:15:003
141012140,0sleep10-21swapper/123:19:561
1589799130,4cyclictest7118-21df23:10:133
1589799130,1cyclictest0-21swapper/323:23:203
15889991313,0cyclictest0-21swapper/222:25:122
15889991310,1cyclictest28-21ksoftirqd/221:15:012
1588399139,4cyclictest21-21ksoftirqd/123:43:341
1589799122,1cyclictest26788-21awk20:39:593
1589799120,11cyclictest13555-21ssh23:18:333
1589799120,1cyclictest8712-21diskmemload00:06:063
1589799120,1cyclictest3197-21df23:05:143
1589799120,1cyclictest240-21systemd-journal21:24:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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