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2026-02-10 - 03:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Tue Feb 10, 2026 00:45:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325702231157,26sleep20-21swapper/219:07:142
327642210156,42sleep00-21swapper/019:09:450
324702203150,40sleep10-21swapper/119:05:561
324522200161,25sleep30-21swapper/319:05:423
56312750,0sleep00-21swapper/021:25:000
81322590,0sleep00-21swapper/023:30:120
224442190,0sleep10-21swapper/122:25:171
184952180,0sleep10-21swapper/100:25:081
416991514,1cyclictest28-21ksoftirqd/223:20:152
416991413,1cyclictest28-21ksoftirqd/221:45:002
416991413,1cyclictest28-21ksoftirqd/200:20:182
416991312,1cyclictest28-21ksoftirqd/222:50:202
416991312,1cyclictest28-21ksoftirqd/219:20:152
416991312,1cyclictest28-21ksoftirqd/200:35:142
423991211,1cyclictest35-21ksoftirqd/320:01:153
41699128,4cyclictest28-21ksoftirqd/222:25:192
416991211,1cyclictest28-21ksoftirqd/223:00:012
416991211,1cyclictest28-21ksoftirqd/222:00:122
416991211,1cyclictest28-21ksoftirqd/221:55:192
416991211,1cyclictest28-21ksoftirqd/221:45:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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