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2026-04-02 - 16:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Apr 02, 2026 12:45:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
200262212148,50sleep00-21swapper/007:05:390
201232209157,26sleep30-21swapper/307:06:553
200742205149,22sleep10-21swapper/107:06:161
200132199159,26sleep20-21swapper/207:05:282
11192140,0sleep30-21swapper/312:35:153
247612130,0sleep00-21swapper/009:35:180
20464991311,1cyclictest28-21ksoftirqd/208:50:002
20464991311,1cyclictest28-21ksoftirqd/208:25:002
2045099138,4cyclictest9-21ksoftirqd/011:05:220
20450991311,1cyclictest9-21ksoftirqd/010:40:000
2045899129,0cyclictest0-21swapper/111:28:021
20450991210,1cyclictest9-21ksoftirqd/012:20:100
20450991210,1cyclictest9-21ksoftirqd/010:45:000
20450991210,1cyclictest9-21ksoftirqd/010:15:010
20450991210,1cyclictest9-21ksoftirqd/010:15:000
20464991110,1cyclictest28-21ksoftirqd/212:30:012
2045099119,1cyclictest9-21ksoftirqd/012:05:010
20450991111,0cyclictest9-21ksoftirqd/009:22:280
20450991110,1cyclictest9-21ksoftirqd/011:50:100
2047299108,1cyclictest693-21runrttasks09:43:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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