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2025-11-11 - 02:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Tue Nov 11, 2025 00:45:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
301902212149,22sleep00-21swapper/019:05:560
303082199157,29sleep10-21swapper/119:07:311
301772199158,27sleep20-21swapper/219:05:472
302082198159,25sleep30-21swapper/319:06:113
56112640,1sleep09-21ksoftirqd/020:30:150
109122600,0sleep224120-21diskmemload23:05:172
3060799130,12cyclictest0-21swapper/219:50:162
3060099130,12cyclictest0-21swapper/119:50:161
44922120,9sleep335-21ksoftirqd/322:10:203
3061599119,1cyclictest35-21ksoftirqd/320:45:003
3060799112,8cyclictest27283-21sh22:43:542
3060799112,8cyclictest27283-21sh22:43:542
30607991110,1cyclictest28-21ksoftirqd/223:25:002
30607991110,1cyclictest28-21ksoftirqd/200:10:002
30607991110,0cyclictest0-21swapper/200:10:132
3059199110,9cyclictest24120-21diskmemload22:00:320
3059199110,5cyclictest2259-21/usr/sbin/munin20:25:010
112402110,0sleep00-21swapper/000:35:560
60842100,0sleep20-21swapper/221:28:582
3061599108,1cyclictest35-21ksoftirqd/323:40:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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