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2026-05-28 - 06:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu May 28, 2026 00:45:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218662213150,22sleep30-21swapper/319:08:033
217982208151,44sleep20-21swapper/219:07:102
219352205141,21sleep00-21swapper/019:08:570
219212197158,26sleep10-21swapper/119:08:471
117142700,0sleep10-21swapper/123:55:171
34032680,0sleep10-21swapper/100:28:061
170472600,0sleep20-21swapper/220:05:132
22105991210,1cyclictest28-21ksoftirqd/221:35:142
2209999120,0cyclictest0-21swapper/119:30:131
22088991210,1cyclictest9-21ksoftirqd/022:20:000
22088991210,1cyclictest9-21ksoftirqd/021:55:010
2210599119,1cyclictest28-21ksoftirqd/223:35:162
2210599119,1cyclictest28-21ksoftirqd/222:40:002
2210599119,1cyclictest28-21ksoftirqd/221:10:132
22105991110,1cyclictest28-21ksoftirqd/221:40:122
2210599110,11cyclictest0-21swapper/221:30:002
2208899119,1cyclictest9-21ksoftirqd/022:50:000
2208899119,1cyclictest9-21ksoftirqd/021:45:000
22088991110,1cyclictest9-21ksoftirqd/022:45:000
22088991110,1cyclictest9-21ksoftirqd/022:29:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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