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2026-07-23 - 17:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Jul 23, 2026 12:45:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
118622219148,47sleep00-21swapper/007:07:250
120402212173,26sleep20-21swapper/207:09:442
118582201163,24sleep10-21swapper/107:07:221
120412199158,27sleep30-21swapper/307:09:453
1670521110,0sleep20-21swapper/210:10:172
269642670,0sleep326965-21dump-pmu-power07:40:003
112352560,0sleep20-21swapper/210:49:222
247772140,0sleep20-21swapper/211:53:592
236942140,0sleep20-21swapper/210:20:152
1215899133,5cyclictest15833-21perf08:25:010
12189991210,1cyclictest35-21ksoftirqd/308:55:003
12169991111,0cyclictest0-21swapper/111:23:181
1215899119,1cyclictest9-21ksoftirqd/008:40:000
1215899112,5cyclictest7786-21latency_hist10:45:000
1215899111,6cyclictest0-21swapper/010:26:010
1217599109,1cyclictest28-21ksoftirqd/211:40:002
121899998,1cyclictest35-21ksoftirqd/312:25:003
121899990,5cyclictest0-21swapper/310:45:123
121589991,6cyclictest19147-21kworker/u8:210:31:230
121589991,4cyclictest25480-21sed08:45:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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