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2026-07-16 - 16:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Jul 16, 2026 12:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158642219156,49sleep20-21swapper/207:07:512
159522200160,26sleep30-21swapper/307:09:013
158622198142,42sleep00-21swapper/007:07:480
156892197160,24sleep10-21swapper/107:05:331
1613499130,13cyclictest0-21swapper/210:00:112
1612399130,13cyclictest0-21swapper/010:00:120
16134991211,1cyclictest28-21ksoftirqd/207:25:012
1612399123,4cyclictest23244-21latency_hist11:29:590
16123991210,1cyclictest9-21ksoftirqd/011:05:110
16123991210,1cyclictest9-21ksoftirqd/008:15:130
16123991210,1cyclictest9-21ksoftirqd/008:15:130
1614299119,1cyclictest35-21ksoftirqd/310:05:003
16142991110,1cyclictest35-21ksoftirqd/310:55:013
1613499115,5cyclictest28-21ksoftirqd/209:55:542
16134991110,1cyclictest0-21swapper/211:55:142
1613499110,11cyclictest0-21swapper/209:12:482
1612399119,1cyclictest9-21ksoftirqd/011:30:120
16123991111,0cyclictest9-21ksoftirqd/010:55:140
16123991110,1cyclictest9-21ksoftirqd/012:35:100
16123991110,1cyclictest9-21ksoftirqd/012:10:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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