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2026-03-30 - 12:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Mon Mar 30, 2026 00:45:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
129272229157,25sleep20-21swapper/219:07:502
130082205148,43sleep00-21swapper/019:08:530
128612201163,24sleep30-21swapper/319:06:593
128792197160,24sleep10-21swapper/119:07:131
206522730,0sleep20-21swapper/200:15:162
19442730,0sleep20-21swapper/221:45:122
65372680,0sleep30-21swapper/323:15:143
131392640,1sleep21318199cyclictest21:18:422
13181992019,1cyclictest28-21ksoftirqd/220:25:012
13181992018,1cyclictest28-21ksoftirqd/219:25:002
13181991918,1cyclictest28-21ksoftirqd/221:55:182
169682180,0sleep10-21swapper/121:23:131
13181991717,0cyclictest28-21ksoftirqd/220:15:152
13181991716,1cyclictest28-21ksoftirqd/221:40:142
169922160,0sleep20-21swapper/222:05:112
13181991616,0cyclictest28-21ksoftirqd/223:59:132
13181991616,0cyclictest28-21ksoftirqd/223:59:132
13181991616,0cyclictest28-21ksoftirqd/200:23:262
13181991515,0cyclictest28-21ksoftirqd/223:46:352
13181991515,0cyclictest28-21ksoftirqd/223:21:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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