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2026-02-25 - 04:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Wed Feb 25, 2026 00:45:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
261882208170,25sleep30-21swapper/319:07:473
263442206169,24sleep00-21swapper/019:09:490
263582200162,25sleep20-21swapper/219:09:582
261092199159,27sleep10-21swapper/119:06:441
62242750,2sleep121-21ksoftirqd/123:35:181
229862640,0sleep20-21swapper/200:39:352
273262570,0sleep027323-21sh00:03:000
129412170,0sleep10-21swapper/100:25:161
8032150,0sleep10-21swapper/121:25:171
26432991311,1cyclictest9-21ksoftirqd/022:20:000
26450991212,0cyclictest0-21swapper/322:37:053
26450991210,1cyclictest35-21ksoftirqd/300:35:003
26444991211,1cyclictest28-21ksoftirqd/222:55:002
26444991211,1cyclictest28-21ksoftirqd/222:30:002
26444991210,1cyclictest28-21ksoftirqd/221:40:002
2643299124,4cyclictest26386-21perf22:40:000
26432991210,1cyclictest9-21ksoftirqd/021:45:000
2645099110,8cyclictest28798-21munin-node21:59:083
2645099110,8cyclictest28798-21munin-node21:59:083
26444991110,1cyclictest28-21ksoftirqd/223:20:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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