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2026-01-01 - 13:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Jan 01, 2026 12:45:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1978623790,4sleep00-21swapper/007:05:220
204672213143,48sleep30-21swapper/307:09:083
204652200162,25sleep10-21swapper/107:09:061
202452200162,24sleep20-21swapper/207:06:132
20621991715,1cyclictest9-21ksoftirqd/009:15:000
97482130,0sleep10-21swapper/112:25:161
20642991311,1cyclictest35-21ksoftirqd/311:20:003
309142120,1sleep12062799cyclictest09:45:121
2062199121,5cyclictest28677-21perf10:50:000
2064299118,1cyclictest35-21ksoftirqd/309:00:003
20642991110,1cyclictest35-21ksoftirqd/308:25:003
2063499119,1cyclictest28-21ksoftirqd/212:34:592
2063499119,1cyclictest28-21ksoftirqd/207:40:012
2062199119,1cyclictest9-21ksoftirqd/012:30:000
2064299109,1cyclictest35-21ksoftirqd/310:10:003
2064299109,1cyclictest35-21ksoftirqd/308:15:013
2064299108,1cyclictest35-21ksoftirqd/310:15:003
20634991010,0cyclictest0-21swapper/211:15:512
2062199107,1cyclictest9-21ksoftirqd/008:44:560
206429997,1cyclictest24515-21latency_hist11:50:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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