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2026-07-30 - 18:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Jul 30, 2026 12:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
266582213178,22sleep30-21swapper/307:05:593
268532205146,44sleep20-21swapper/207:08:312
266702205155,23sleep00-21swapper/007:06:080
268002199160,26sleep10-21swapper/107:07:501
27061991412,1cyclictest9-21ksoftirqd/010:20:000
27079991312,1cyclictest28-21ksoftirqd/210:50:002
2706199122,5cyclictest12024-21latency_hist07:45:000
27061991210,1cyclictest9-21ksoftirqd/009:10:000
27079991110,1cyclictest28-21ksoftirqd/210:25:022
27079991110,1cyclictest28-21ksoftirqd/210:17:102
27079991110,1cyclictest28-21ksoftirqd/209:30:162
2706199119,1cyclictest9-21ksoftirqd/011:25:130
27061991110,1cyclictest9-21ksoftirqd/011:50:140
281982100,0sleep20-21swapper/211:37:332
2708899100,2cyclictest0-21swapper/312:10:123
2707999109,1cyclictest28-21ksoftirqd/210:40:152
2707999109,1cyclictest28-21ksoftirqd/209:45:002
2707999108,1cyclictest28-21ksoftirqd/211:15:132
2707999106,1cyclictest61650irq/122-eno109:14:012
2707999100,10cyclictest0-21swapper/210:07:302
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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