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2026-08-27 - 20:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Aug 27, 2026 12:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26502201162,25sleep10-21swapper/107:09:071
26142201163,24sleep00-21swapper/007:08:370
27032200159,27sleep20-21swapper/207:09:482
24112200168,20sleep30-21swapper/307:05:593
74882170,0sleep30-21swapper/310:56:153
132152160,0sleep00-21swapper/007:30:120
2825991312,1cyclictest28-21ksoftirqd/211:20:202
2825991311,1cyclictest28-21ksoftirqd/212:13:282
2825991311,1cyclictest28-21ksoftirqd/209:20:002
2825991210,1cyclictest28-21ksoftirqd/211:30:012
2825991210,1cyclictest28-21ksoftirqd/210:15:152
281799120,11cyclictest0-21swapper/111:40:121
280599121,5cyclictest20749-21latency_hist09:45:010
282599119,1cyclictest28-21ksoftirqd/209:10:152
2825991111,0cyclictest28-21ksoftirqd/212:17:142
2825991110,1cyclictest28-21ksoftirqd/211:45:212
2825991110,1cyclictest28-21ksoftirqd/209:50:182
282599110,7cyclictest240-21systemd-journal10:00:002
282599110,0cyclictest0-21swapper/212:32:112
280599119,1cyclictest9-21ksoftirqd/010:10:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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