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2026-02-17 - 02:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Tue Feb 17, 2026 00:45:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
322022221157,25sleep10-21swapper/119:05:441
323872213158,42sleep30-21swapper/319:08:073
323272206148,45sleep00-21swapper/019:07:200
323022199160,26sleep20-21swapper/219:07:022
78382180,1sleep10-21swapper/120:30:151
194362160,0sleep10-21swapper/122:21:091
238832140,0sleep30-21swapper/323:09:013
3263599126,1cyclictest16789-21sh23:00:122
32635991210,1cyclictest28-21ksoftirqd/221:40:002
32628991210,1cyclictest9-21ksoftirqd/022:20:140
32628991210,1cyclictest9-21ksoftirqd/020:05:000
3263599110,0cyclictest0-21swapper/221:54:152
3262899119,1cyclictest9-21ksoftirqd/022:30:000
3262899119,1cyclictest9-21ksoftirqd/020:50:000
32628991110,1cyclictest9-21ksoftirqd/020:00:000
32628991110,1cyclictest9-21ksoftirqd/019:35:110
3264699101,8cyclictest25871-21diskmemload00:36:173
3263599106,3cyclictest27648-21sh23:13:372
3263599101,8cyclictest61650irq/122-eno100:10:202
3263599100,10cyclictest0-21swapper/222:19:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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