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2026-01-12 - 14:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Mon Jan 12, 2026 12:45:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
298262211174,24sleep10-21swapper/107:08:091
297032202164,24sleep20-21swapper/207:06:332
298382201161,27sleep30-21swapper/307:08:193
299522198161,23sleep00-21swapper/007:09:500
290522160,0sleep20-21swapper/211:56:052
30061991513,1cyclictest28-21ksoftirqd/207:15:002
30061991412,1cyclictest28-21ksoftirqd/209:45:002
3006199129,2cyclictest28-21ksoftirqd/212:20:132
30061991210,1cyclictest28-21ksoftirqd/212:35:012
30061991210,1cyclictest28-21ksoftirqd/212:25:172
30061991210,1cyclictest28-21ksoftirqd/210:40:152
30061991210,1cyclictest28-21ksoftirqd/210:19:592
3005499120,11cyclictest0-21swapper/108:45:141
33932110,0sleep10-21swapper/110:05:101
3006199119,1cyclictest28-21ksoftirqd/207:20:202
30061991110,1cyclictest28-21ksoftirqd/209:53:042
30052991110,1cyclictest9-21ksoftirqd/009:24:590
3006199109,1cyclictest28-21ksoftirqd/211:30:112
3006199109,1cyclictest28-21ksoftirqd/210:25:152
3006199109,1cyclictest28-21ksoftirqd/209:40:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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