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2026-02-10 - 01:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Mon Feb 09, 2026 12:45:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165062201161,26sleep00-21swapper/007:07:360
165532199160,26sleep20-21swapper/207:08:142
163532199162,24sleep10-21swapper/107:05:361
145802198157,27sleep30-21swapper/307:05:043
1677599120,11cyclictest7263-21cat10:30:013
16770991210,1cyclictest28-21ksoftirqd/208:40:012
16775991110,1cyclictest35-21ksoftirqd/308:05:003
1677099119,1cyclictest28-21ksoftirqd/209:45:002
1677099119,1cyclictest28-21ksoftirqd/209:00:002
16770991110,1cyclictest28-21ksoftirqd/207:15:002
1676599110,5cyclictest19179-21users07:15:000
1677099109,1cyclictest28-21ksoftirqd/209:50:002
1677099109,1cyclictest28-21ksoftirqd/208:30:002
1677099108,1cyclictest28-21ksoftirqd/211:05:002
1677099108,1cyclictest28-21ksoftirqd/211:00:002
1677099108,1cyclictest28-21ksoftirqd/208:35:012
167709998,1cyclictest28-21ksoftirqd/211:40:002
167709998,1cyclictest28-21ksoftirqd/211:10:132
167709998,1cyclictest28-21ksoftirqd/210:15:002
167709998,1cyclictest28-21ksoftirqd/208:15:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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