You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-12-01 - 10:40
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Mon Dec 01, 2025 00:45:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180672230159,24sleep30-21swapper/319:05:523
182022211157,42sleep00-21swapper/019:07:340
180812201162,26sleep20-21swapper/219:06:032
162122200161,26sleep10-21swapper/119:05:001
291722120,0sleep20-21swapper/222:19:122
18499991110,0cyclictest28-21ksoftirqd/200:00:002
1849199110,11cyclictest0-21swapper/100:25:191
18483991110,1cyclictest9-21ksoftirqd/000:33:510
1849999101,8cyclictest1497-21sendmail-mta22:00:512
1848399109,1cyclictest9-21ksoftirqd/021:19:490
1848399108,1cyclictest9-21ksoftirqd/021:30:000
18483991010,0cyclictest9-21ksoftirqd/021:52:350
148782100,0sleep30-21swapper/321:14:413
185049998,1cyclictest35-21ksoftirqd/300:35:003
184999998,1cyclictest28-21ksoftirqd/221:19:262
184999997,1cyclictest28-21ksoftirqd/223:35:342
184999990,5cyclictest5843-21proc_pri22:30:202
184839998,1cyclictest9-21ksoftirqd/022:50:000
184839990,6cyclictest26919-21/usr/sbin/munin00:35:230
184839990,6cyclictest26919-21/usr/sbin/munin00:35:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional