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2026-06-18 - 10:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Jun 18, 2026 00:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
313552222157,25sleep10-21swapper/119:09:101
314062216152,51sleep00-21swapper/019:09:500
311312202164,25sleep30-21swapper/319:06:143
310952199161,24sleep20-21swapper/219:05:462
112582690,0sleep20-21swapper/221:35:122
29382660,0sleep10-21swapper/123:35:151
250712660,0sleep10-21swapper/120:00:191
161642610,0sleep20-21swapper/200:36:402
292782330,0sleep20-21swapper/222:43:252
3154199135,7cyclictest28997-21cat00:10:153
204032130,0sleep30-21swapper/319:50:213
31541991211,1cyclictest35-21ksoftirqd/322:40:003
3154199121,3cyclictest20476-21munin-run00:00:003
31512991210,1cyclictest9-21ksoftirqd/021:10:000
3154199115,5cyclictest24420-21ssh21:10:013
3154199115,5cyclictest20896-21ssh21:47:523
3154199113,1cyclictest240-21systemd-journal20:40:003
31541991110,1cyclictest35-21ksoftirqd/321:00:003
3154199111,1cyclictest28268-21chrt22:40:263
3154199110,3cyclictest0-21swapper/322:32:283
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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