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2026-11-07 - 06:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Sat Nov 07, 2026 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
129592205166,26sleep30-21swapper/319:07:343
130682203139,21sleep00-21swapper/019:09:010
129052201162,25sleep10-21swapper/119:06:521
128092198159,26sleep20-21swapper/219:05:372
11662220,0sleep00-21swapper/019:50:130
221332170,0sleep10-21swapper/119:25:161
90192150,0sleep10-21swapper/100:20:001
58432140,0sleep00-21swapper/021:55:120
1323099147,6cyclictest9-21ksoftirqd/000:35:110
13230991413,1cyclictest9-21ksoftirqd/021:05:000
13230991413,1cyclictest9-21ksoftirqd/000:30:120
13230991412,1cyclictest9-21ksoftirqd/020:09:590
496621311,0sleep335-21ksoftirqd/321:54:253
13230991312,1cyclictest9-21ksoftirqd/023:55:000
13230991312,1cyclictest9-21ksoftirqd/023:20:010
1324699120,11cyclictest61650irq/122-eno121:24:422
1323099122,5cyclictest4458-21latency_hist22:40:000
13230991211,1cyclictest9-21ksoftirqd/000:20:170
13230991210,1cyclictest9-21ksoftirqd/023:55:190
13230991210,1cyclictest9-21ksoftirqd/022:45:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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