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2026-05-21 - 05:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu May 21, 2026 00:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
118482223157,26sleep10-21swapper/119:07:381
118372209172,24sleep00-21swapper/019:07:290
117352207149,46sleep20-21swapper/219:06:112
117162197158,26sleep30-21swapper/319:05:543
202032560,0sleep30-21swapper/321:28:293
1212199140,13cyclictest0-21swapper/119:25:141
12121991311,1cyclictest20049-21chrt22:55:101
12115991310,2cyclictest9-21ksoftirqd/022:35:000
12128991211,1cyclictest0-21swapper/221:49:282
12128991210,1cyclictest28-21ksoftirqd/223:45:002
12128991210,1cyclictest271rcuc/221:15:002
1212199121,3cyclictest0-21swapper/123:00:121
1212199120,1cyclictest0-21swapper/123:45:291
1212199120,0cyclictest0-21swapper/119:30:101
12115991210,1cyclictest9-21ksoftirqd/000:00:010
136552110,0sleep20-21swapper/222:01:572
1212899119,1cyclictest28-21ksoftirqd/219:49:592
12128991110,1cyclictest28-21ksoftirqd/220:45:002
1212199110,3cyclictest0-21swapper/100:05:211
1212199110,10cyclictest0-21swapper/100:15:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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