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2026-02-28 - 04:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Sat Feb 28, 2026 00:45:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158512207150,43sleep30-21swapper/319:09:523
157002201148,40sleep10-21swapper/119:07:531
155522201161,26sleep20-21swapper/219:05:582
155252197160,24sleep00-21swapper/019:05:340
163721220,0sleep01593799cyclictest19:45:120
185992680,0sleep00-21swapper/019:15:000
4482590,0sleep20-21swapper/221:40:012
190272160,1sleep019032-21unixbench_multi21:20:200
178732160,0sleep20-21swapper/223:25:012
142182140,0sleep10-21swapper/123:20:121
15953991312,1cyclictest28-21ksoftirqd/221:00:002
1595399120,12cyclictest0-21swapper/200:25:032
1593799125,6cyclictest11298-1kworker/u9:000:00:110
1593799121,5cyclictest0-21swapper/019:55:000
1595399119,1cyclictest28-21ksoftirqd/223:35:002
15953991110,1cyclictest28-21ksoftirqd/222:10:012
15953991110,1cyclictest28-21ksoftirqd/219:25:002
1595799102,7cyclictest30645-21taskset22:17:103
1595399109,1cyclictest28-21ksoftirqd/223:20:012
1595399109,1cyclictest28-21ksoftirqd/220:55:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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