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2026-04-14 - 22:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Tue Apr 14, 2026 12:45:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14632226157,55sleep30-21swapper/307:07:353
16082220153,23sleep20-21swapper/207:09:272
15972203164,25sleep10-21swapper/107:09:181
13412202150,22sleep00-21swapper/007:05:590
1071721060,0sleep00-21swapper/010:10:180
80682500,0sleep20-21swapper/211:31:302
174199140,0cyclictest0-21swapper/109:20:431
1750991313,0cyclictest28-21ksoftirqd/212:33:042
1750991313,0cyclictest28-21ksoftirqd/210:22:042
1750991313,0cyclictest28-21ksoftirqd/210:01:502
1750991312,1cyclictest28-21ksoftirqd/211:10:002
1750991312,1cyclictest28-21ksoftirqd/210:06:482
174199130,12cyclictest0-21swapper/108:40:181
1733991312,1cyclictest9-21ksoftirqd/011:05:150
1733991311,1cyclictest9-21ksoftirqd/007:59:590
1750991211,1cyclictest28-21ksoftirqd/209:40:142
1750991210,1cyclictest28-21ksoftirqd/211:10:162
175099121,4cyclictest0-21swapper/208:15:132
1733991211,1cyclictest9-21ksoftirqd/008:30:000
94482110,0sleep30-21swapper/310:10:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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