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2026-01-20 - 00:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Mon Jan 19, 2026 12:45:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27302245156,23sleep20-21swapper/207:07:422
25692212148,21sleep00-21swapper/007:05:350
25902211159,41sleep10-21swapper/107:05:521
26122197158,26sleep30-21swapper/307:06:103
177732170,0sleep10-21swapper/110:55:371
302172150,1sleep1298999cyclictest09:10:441
2997991312,1cyclictest28-21ksoftirqd/208:35:002
106212130,0sleep10-21swapper/109:26:341
2997991211,1cyclictest28-21ksoftirqd/210:45:002
298799123,4cyclictest12178-21perf09:30:010
299799119,1cyclictest28-21ksoftirqd/209:10:002
299799119,1cyclictest28-21ksoftirqd/207:20:002
2997991110,1cyclictest28-21ksoftirqd/208:40:002
2987991110,1cyclictest9-21ksoftirqd/012:40:000
300599108,1cyclictest35-21ksoftirqd/308:00:003
300599101,7cyclictest3667-21latency_hist10:00:013
299799109,1cyclictest28-21ksoftirqd/209:45:002
299799103,6cyclictest61650irq/122-eno111:35:152
298799109,1cyclictest9-21ksoftirqd/011:45:000
298799109,1cyclictest9-21ksoftirqd/011:45:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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