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2025-08-29 - 14:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Fri Aug 29, 2025 12:45:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3136725470,6sleep09-21ksoftirqd/007:05:150
9122208154,21sleep10-21swapper/107:08:591
8762202164,25sleep20-21swapper/207:08:322
6992202158,28sleep30-21swapper/307:06:193
1202421080,0sleep10-21swapper/109:31:241
52472740,0sleep20-21swapper/207:15:162
1107991413,1cyclictest28-21ksoftirqd/212:24:332
110799130,12cyclictest0-21swapper/208:50:142
1107991211,1cyclictest28-21ksoftirqd/212:10:002
1107991211,1cyclictest28-21ksoftirqd/211:20:142
1107991211,1cyclictest28-21ksoftirqd/210:48:032
1107991211,1cyclictest28-21ksoftirqd/207:35:012
1107991210,1cyclictest28-21ksoftirqd/210:45:002
1120991110,1cyclictest35-21ksoftirqd/311:05:153
110799119,1cyclictest28-21ksoftirqd/209:10:012
110799119,1cyclictest28-21ksoftirqd/209:10:002
1107991110,1cyclictest28-21ksoftirqd/212:01:532
1107991110,1cyclictest28-21ksoftirqd/211:35:182
1107991110,1cyclictest28-21ksoftirqd/211:30:192
1107991110,1cyclictest28-21ksoftirqd/210:32:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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