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2026-08-13 - 18:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Thu Aug 13, 2026 12:45:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2936324000,7sleep30-21swapper/307:05:243
299842207152,21sleep10-21swapper/107:09:251
299702200160,26sleep20-21swapper/207:09:142
297522198160,24sleep00-21swapper/007:06:220
317342800,0sleep10-21swapper/108:20:011
292432600,1sleep3341rcuc/310:03:283
90272200,1sleep29021-21gltestperf07:30:162
30132991414,0cyclictest0-21swapper/210:00:172
30132991311,1cyclictest28-21ksoftirqd/207:25:012
30124991313,0cyclictest0-21swapper/109:28:141
3011799130,12cyclictest0-21swapper/008:05:140
30132991111,0cyclictest20075-21ssh11:21:152
3011799119,1cyclictest9-21ksoftirqd/007:20:010
3011799113,4cyclictest26246-21perf09:15:010
3011799113,4cyclictest26246-21perf09:15:010
3011799113,4cyclictest11596-21perf10:24:590
284972110,0sleep30-21swapper/309:15:573
10912110,0sleep30-21swapper/310:10:123
3014099109,1cyclictest32010-21perf11:40:003
3014099107,1cyclictest35-21ksoftirqd/310:50:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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