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2025-10-28 - 02:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Tue Oct 28, 2025 00:45:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
87932221158,49sleep20-21swapper/219:09:242
85442203162,27sleep10-21swapper/119:06:101
86692201161,26sleep00-21swapper/019:07:450
87172199162,24sleep30-21swapper/319:08:243
172772750,0sleep20-21swapper/223:00:002
318012710,0sleep10-21swapper/121:05:001
8937991411,1cyclictest28-21ksoftirqd/220:05:002
8937991312,1cyclictest28-21ksoftirqd/219:15:012
8920991311,1cyclictest9-21ksoftirqd/000:40:010
8937991212,0cyclictest0-21swapper/222:25:192
893799120,0cyclictest0-21swapper/219:35:152
8920991211,1cyclictest9-21ksoftirqd/023:40:010
8920991211,1cyclictest9-21ksoftirqd/023:00:000
8920991211,1cyclictest9-21ksoftirqd/000:00:000
8948991110,1cyclictest35-21ksoftirqd/321:45:003
8948991110,1cyclictest35-21ksoftirqd/319:35:003
892899119,1cyclictest192932sleep123:00:441
892099119,1cyclictest9-21ksoftirqd/000:20:000
8920991110,1cyclictest9-21ksoftirqd/022:20:160
8920991110,1cyclictest9-21ksoftirqd/000:20:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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