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2026-02-24 - 03:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Tue Feb 24, 2026 00:45:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71802208175,21sleep10-21swapper/119:08:061
71612202160,28sleep20-21swapper/219:07:512
70702199156,23sleep00-21swapper/019:06:400
72392198158,26sleep30-21swapper/319:08:513
15012750,1sleep121-21ksoftirqd/121:10:161
3562610,0sleep10-21swapper/121:10:001
157622580,0sleep30-21swapper/319:25:133
7409991312,1cyclictest9-21ksoftirqd/021:50:000
41172130,0sleep10-21swapper/123:15:481
7424991211,1cyclictest35-21ksoftirqd/300:35:003
7418991210,1cyclictest28-21ksoftirqd/221:25:012
740999122,5cyclictest9959-21cat23:25:000
7409991211,1cyclictest9-21ksoftirqd/000:20:010
7424991110,1cyclictest35-21ksoftirqd/321:55:003
7424991110,1cyclictest35-21ksoftirqd/320:30:013
741899110,1cyclictest0-21swapper/223:18:552
740999117,3cyclictest27151-21ssh22:24:300
742499109,1cyclictest35-21ksoftirqd/321:10:003
742499109,1cyclictest35-21ksoftirqd/300:15:003
742499108,1cyclictest561-21nscd22:43:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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