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2026-01-05 - 12:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Mon Jan 05, 2026 00:45:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201892224153,49sleep30-21swapper/319:09:093
199982199160,25sleep10-21swapper/119:06:371
199372199161,24sleep20-21swapper/219:05:492
199332196157,25sleep00-21swapper/019:05:470
119212630,0sleep10-21swapper/121:05:201
20386991312,1cyclictest35-21ksoftirqd/322:20:003
20354991311,1cyclictest9-21ksoftirqd/000:05:010
2037599122,9cyclictest0-21swapper/222:50:162
20386991110,1cyclictest35-21ksoftirqd/320:15:013
2035499119,1cyclictest9-21ksoftirqd/022:00:010
2035499119,1cyclictest9-21ksoftirqd/021:30:000
2035499119,1cyclictest5611-21grep00:15:150
2035499118,2cyclictest0-21swapper/019:15:150
2037599108,1cyclictest28-21ksoftirqd/222:44:592
2036799100,5cyclictest0-21swapper/122:40:141
2035499107,2cyclictest19640-21python23:35:200
2035499107,2cyclictest0-21swapper/021:40:200
2035499103,7cyclictest9-21ksoftirqd/021:45:110
2035499102,8cyclictest9-21ksoftirqd/022:55:100
2035499102,8cyclictest9-21ksoftirqd/022:33:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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