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2025-11-29 - 05:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot1.osadl.org (updated Fri Nov 28, 2025 12:45:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121572238161,26sleep20-21swapper/207:08:162
122832234160,25sleep00-21swapper/007:09:500
122252219148,24sleep30-21swapper/307:09:093
101812199160,26sleep10-21swapper/107:05:041
101521030,0sleep10-21swapper/107:50:201
238562580,0sleep20-21swapper/210:18:022
12405992018,2cyclictest28-21ksoftirqd/209:44:022
167002190,0sleep10-21swapper/111:37:211
300252150,0sleep10-21swapper/110:25:221
12405991512,1cyclictest28-21ksoftirqd/211:57:512
1238399151,13cyclictest0-21swapper/007:15:010
12405991211,1cyclictest28-21ksoftirqd/211:26:312
12405991210,1cyclictest28-21ksoftirqd/211:20:142
12405991210,1cyclictest28-21ksoftirqd/211:05:012
12405991210,1cyclictest28-21ksoftirqd/210:40:012
1238399120,11cyclictest0-21swapper/007:25:180
1240599119,1cyclictest28-21ksoftirqd/211:50:142
1240599119,1cyclictest28-21ksoftirqd/210:45:002
1240599119,1cyclictest28-21ksoftirqd/209:05:142
12405991110,1cyclictest28-21ksoftirqd/212:25:102
12405991110,1cyclictest28-21ksoftirqd/211:05:212
12405991110,1cyclictest28-21ksoftirqd/210:25:232
12405991110,1cyclictest28-21ksoftirqd/210:11:142
12405991110,1cyclictest28-21ksoftirqd/209:55:002
12405991110,1cyclictest28-21ksoftirqd/209:47:282
12405991110,1cyclictest28-21ksoftirqd/209:35:162
12405991110,1cyclictest28-21ksoftirqd/209:20:162
12405991110,1cyclictest28-21ksoftirqd/209:10:232
1238399112,4cyclictest0-21swapper/011:29:590
1238399110,10cyclictest5095-21diskmemload10:30:130
277862100,0sleep00-21swapper/012:39:080
167652100,0sleep20-21swapper/207:15:182
127422100,0sleep05095-21diskmemload10:02:230
1240599109,1cyclictest28-21ksoftirqd/212:35:162
1240599109,1cyclictest28-21ksoftirqd/212:30:182
1240599109,1cyclictest28-21ksoftirqd/212:30:172
1240599109,1cyclictest28-21ksoftirqd/212:20:052
1240599109,1cyclictest28-21ksoftirqd/212:15:122
1240599109,1cyclictest28-21ksoftirqd/212:05:232
1240599109,1cyclictest28-21ksoftirqd/212:00:172
1240599109,1cyclictest28-21ksoftirqd/211:15:172
1240599109,1cyclictest28-21ksoftirqd/210:55:152
1240599109,1cyclictest28-21ksoftirqd/210:45:162
1240599109,1cyclictest28-21ksoftirqd/210:02:132
1240599109,1cyclictest28-21ksoftirqd/209:30:152
1240599109,1cyclictest28-21ksoftirqd/209:15:202
1240599108,1cyclictest28-21ksoftirqd/210:30:172
1240599108,1cyclictest28-21ksoftirqd/208:25:142
1240599108,1cyclictest28-21ksoftirqd/208:20:002
1239899100,4cyclictest0-21swapper/107:35:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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