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2026-01-09 - 02:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot1.osadl.org (updated Fri Jan 09, 2026 00:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
317942199158,27sleep20-21swapper/219:08:512
315942198160,25sleep00-21swapper/019:06:160
315552198159,26sleep10-21swapper/119:05:441
315502196158,24sleep30-21swapper/319:05:423
69542170,0sleep30-21swapper/323:55:143
31995991713,4cyclictest21-21ksoftirqd/120:45:061
31995991713,0cyclictest21-21ksoftirqd/100:06:341
31995991410,0cyclictest21-21ksoftirqd/122:59:261
3199599140,13cyclictest0-21swapper/121:20:181
3198799143,5cyclictest8326-21perf20:35:000
115022140,0sleep00-21swapper/000:05:120
32004991311,1cyclictest28-21ksoftirqd/221:15:012
3199599139,4cyclictest21-21ksoftirqd/122:48:141
3199599139,4cyclictest21-21ksoftirqd/122:14:371
3199599130,13cyclictest21-21ksoftirqd/120:00:181
3199599130,13cyclictest0-21swapper/123:21:501
31987991312,1cyclictest9-21ksoftirqd/022:20:000
3199599120,10cyclictest0-21swapper/122:03:251
3199599120,0cyclictest0-21swapper/122:25:491
3199599120,0cyclictest0-21swapper/121:52:141
31987991210,1cyclictest9-21ksoftirqd/022:35:000
32004991110,1cyclictest28-21ksoftirqd/219:55:002
32004991110,1cyclictest28-21ksoftirqd/200:20:002
31995991111,0cyclictest0-21swapper/100:01:141
3199599110,8cyclictest0-21swapper/123:35:111
3198799113,4cyclictest20925-21perf22:10:010
3200499109,1cyclictest28-21ksoftirqd/220:45:002
3200499109,1cyclictest28-21ksoftirqd/200:30:002
3200499108,1cyclictest28-21ksoftirqd/221:50:002
3199599108,1cyclictest21-21ksoftirqd/121:55:151
3199599100,10cyclictest0-21swapper/120:56:151
3199599100,10cyclictest0-21swapper/120:33:541
3199599100,0cyclictest0-21swapper/123:33:021
3199599100,0cyclictest0-21swapper/123:10:361
3198799108,1cyclictest9-21ksoftirqd/020:00:000
3198799103,6cyclictest10963-21perf00:05:010
320129990,6cyclictest0-21swapper/321:15:103
320049998,1cyclictest28-21ksoftirqd/222:40:132
320049997,1cyclictest28-21ksoftirqd/222:30:132
320049997,1cyclictest28-21ksoftirqd/219:15:012
319959998,1cyclictest21-21ksoftirqd/123:40:161
319959998,1cyclictest21-21ksoftirqd/122:20:121
319959998,1cyclictest21-21ksoftirqd/122:15:161
319959998,1cyclictest21-21ksoftirqd/121:45:141
319959998,1cyclictest21-21ksoftirqd/121:15:101
319959998,1cyclictest21-21ksoftirqd/120:54:591
319959991,8cyclictest21-21ksoftirqd/122:40:151
319959990,5cyclictest0-21swapper/119:37:521
319959990,3cyclictest111rcu_preempt19:55:121
319959990,0cyclictest0-21swapper/119:49:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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