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2026-03-01 - 05:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot1.osadl.org (updated Sun Mar 01, 2026 00:45:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
215772229156,24sleep30-21swapper/319:09:173
214572201164,23sleep00-21swapper/019:07:400
213082201162,26sleep20-21swapper/219:05:452
215802199161,24sleep10-21swapper/119:09:191
8882680,0sleep00-21swapper/022:06:100
29282660,0sleep00-21swapper/023:30:540
277782590,1sleep3341rcuc/323:22:273
21752992018,1cyclictest28-21ksoftirqd/221:39:592
214142200,0sleep0101rcuc/023:55:170
240372180,0sleep00-21swapper/021:15:120
240372180,0sleep00-21swapper/021:15:120
22002170,0sleep20-21swapper/222:09:322
21752991513,1cyclictest28-21ksoftirqd/200:15:132
60862140,0sleep30-21swapper/322:14:303
21752991413,1cyclictest28-21ksoftirqd/200:05:002
203062140,0sleep00-21swapper/022:31:020
21752991313,0cyclictest28-21ksoftirqd/221:45:102
21752991312,1cyclictest28-21ksoftirqd/222:45:232
21752991311,1cyclictest28-21ksoftirqd/223:00:002
21732991312,1cyclictest9-21ksoftirqd/021:34:470
21752991211,1cyclictest28-21ksoftirqd/223:00:112
21752991211,1cyclictest28-21ksoftirqd/222:44:592
21752991211,1cyclictest28-21ksoftirqd/221:30:112
21752991211,1cyclictest28-21ksoftirqd/220:55:012
21752991210,1cyclictest28-21ksoftirqd/223:55:182
21752991210,1cyclictest28-21ksoftirqd/221:20:182
21752991210,1cyclictest28-21ksoftirqd/220:25:012
2176599115,1cyclictest26413-21ssh21:58:323
2175299119,1cyclictest28-21ksoftirqd/222:20:162
2175299119,1cyclictest28-21ksoftirqd/200:35:192
21752991110,1cyclictest28-21ksoftirqd/223:45:142
21752991110,1cyclictest28-21ksoftirqd/223:40:142
21752991110,1cyclictest28-21ksoftirqd/222:00:112
21752991110,1cyclictest28-21ksoftirqd/221:40:202
21752991110,1cyclictest28-21ksoftirqd/200:20:132
2173299119,1cyclictest9-21ksoftirqd/020:00:000
2176599105,1cyclictest707-21snmpd22:25:053
2176599100,5cyclictest19833-21diskmemload23:11:253
2176599100,5cyclictest19833-21diskmemload23:11:243
2175299109,1cyclictest271rcuc/200:05:112
2175299108,1cyclictest28-21ksoftirqd/222:15:012
21752991010,0cyclictest28-21ksoftirqd/222:15:162
21752991010,0cyclictest28-21ksoftirqd/222:15:162
21752991010,0cyclictest0-21swapper/222:30:192
2175299100,7cyclictest28-21ksoftirqd/221:19:492
2175299100,7cyclictest28-21ksoftirqd/221:19:482
2175299100,6cyclictest28-21ksoftirqd/221:55:102
2173299109,1cyclictest9-21ksoftirqd/023:20:000
2173299101,4cyclictest8473-21perf23:39:590
217659997,1cyclictest35-21ksoftirqd/320:39:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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