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2026-04-23 - 03:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot1.osadl.org (updated Thu Apr 23, 2026 00:45:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
55382218152,22sleep20-21swapper/219:09:522
54752218151,53sleep30-21swapper/319:09:043
52412203150,22sleep00-21swapper/019:06:000
54682198161,24sleep10-21swapper/119:08:591
5652991919,0cyclictest28-21ksoftirqd/222:00:342
15332180,0sleep10-21swapper/121:13:371
5652991615,1cyclictest28-21ksoftirqd/223:10:112
5652991514,1cyclictest28-21ksoftirqd/222:35:142
5652991513,1cyclictest28-21ksoftirqd/219:55:202
5647991514,1cyclictest0-21swapper/119:15:111
196152150,0sleep20-21swapper/222:20:062
5652991414,0cyclictest28-21ksoftirqd/200:26:152
5652991312,1cyclictest28-21ksoftirqd/222:55:152
5652991312,1cyclictest28-21ksoftirqd/221:10:122
5652991312,1cyclictest28-21ksoftirqd/219:35:142
5652991311,1cyclictest28-21ksoftirqd/223:30:212
5639991311,1cyclictest9-21ksoftirqd/021:35:000
565299125,6cyclictest28-21ksoftirqd/220:45:002
5652991212,0cyclictest28-21ksoftirqd/223:15:562
5652991212,0cyclictest28-21ksoftirqd/221:57:462
5652991212,0cyclictest28-21ksoftirqd/200:37:122
5652991211,1cyclictest28-21ksoftirqd/221:15:132
5652991211,1cyclictest28-21ksoftirqd/220:11:182
5652991211,1cyclictest28-21ksoftirqd/200:12:062
5652991210,1cyclictest28-21ksoftirqd/222:10:002
563999120,8cyclictest569-21nscd21:45:110
22462120,1sleep32252-21timerandwakeup21:55:203
566199110,10cyclictest13286-21switchtime20:30:193
565299119,1cyclictest28-21ksoftirqd/223:05:142
565299119,1cyclictest28-21ksoftirqd/219:15:182
5652991111,0cyclictest28-21ksoftirqd/200:15:112
5652991110,1cyclictest28-21ksoftirqd/222:40:132
5652991110,1cyclictest28-21ksoftirqd/221:40:132
5652991110,1cyclictest28-21ksoftirqd/221:20:132
5652991110,1cyclictest28-21ksoftirqd/220:05:182
5652991110,1cyclictest28-21ksoftirqd/219:45:192
563999119,1cyclictest9-21ksoftirqd/022:35:210
563999119,1cyclictest9-21ksoftirqd/000:19:590
566199100,6cyclictest561-21nscd22:35:083
565299109,1cyclictest28-21ksoftirqd/223:37:252
565299109,1cyclictest28-21ksoftirqd/223:27:182
565299109,1cyclictest28-21ksoftirqd/223:22:192
565299109,1cyclictest28-21ksoftirqd/222:33:402
565299109,1cyclictest28-21ksoftirqd/222:15:122
565299109,1cyclictest28-21ksoftirqd/222:11:122
565299109,1cyclictest28-21ksoftirqd/222:11:122
565299109,1cyclictest28-21ksoftirqd/221:25:212
565299109,1cyclictest28-21ksoftirqd/200:20:072
565299108,1cyclictest28-21ksoftirqd/223:05:002
565299108,1cyclictest28-21ksoftirqd/221:30:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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