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2026-04-13 - 14:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Mon Apr 13, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71925344,0sleep20-21swapper/207:17:162
89224636,0sleep10-21swapper/107:18:471
81524231,0sleep00-21swapper/007:18:060
57623930,0sleep30-21swapper/307:15:363
8305060,0irq/26-0000:00:9281-21munin-node11:10:292
339960,0migration/38506-21kthreadcore09:35:253
339960,0migration/332278-21sh11:04:013
339960,0migration/330125-21sh10:43:553
339960,0migration/328147-21sh10:24:163
339960,0migration/314557-21sh10:52:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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