You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-02 - 11:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Mon Feb 02, 2026 00:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2701425142,0sleep20-21swapper/219:12:312
2696123524,0sleep00-21swapper/019:11:530
2021823127,0sleep30-21swapper/319:09:193
2682122925,0sleep10-21swapper/119:10:171
27230991010,0cyclictest3524-21snmpd21:17:050
27230991010,0cyclictest0-21swapper/021:03:060
272319976,0cyclictest3571-21lldpd22:24:471
65269760,0rudpserv8667-21kthreadcore20:29:353
65269760,0rudpserv5941-21tr20:49:343
65269760,0rudpserv4675-21ssh22:54:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional