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2026-05-09 - 19:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Sat May 09, 2026 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2566225238,0sleep00-21swapper/007:20:010
2473624738,0sleep30-21swapper/307:17:363
2559123324,0sleep20-21swapper/207:19:152
2550423329,0sleep10-21swapper/107:18:141
25924991313,0cyclictest15143-21sensors10:57:361
25924991010,0cyclictest14907-21sensors09:02:361
339960,0migration/39848-21sh10:00:463
339960,0migration/324257-21sh12:17:393
339960,0migration/314836-21kthreadcore10:22:353
29815060,0irq/29-eth0-tx-11041-21tr09:22:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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