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2026-03-01 - 13:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Sun Mar 01, 2026 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2936323626,0sleep10-21swapper/107:12:491
2942323526,0sleep20-21swapper/207:13:302
2604523222,0sleep30-21swapper/307:11:513
2951223127,0sleep00-21swapper/007:14:320
29755991212,0cyclictest3524-21snmpd12:29:140
297559970,0cyclictest7199-40yum-updatesd-he10:11:290
4160,0ktimersoftd/00-21swapper/011:50:420
35160,0ktimersoftd/322743-21cpu10:01:443
35160,0ktimersoftd/30-21swapper/311:50:423
339960,0migration/330772-21needreboot10:21:503
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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