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2026-01-15 - 07:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Thu Jan 15, 2026 00:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2690326362,0sleep10-21swapper/119:12:341
2000825141,0sleep30-21swapper/319:07:563
2690424837,0sleep20-21swapper/219:12:352
2675623127,0sleep00-21swapper/019:10:530
269929970,0cyclictest20738-21grep20:13:051
269919970,0cyclictest10620-21kthreadcore00:03:020
4160,0ktimersoftd/00-21swapper/000:16:230
35160,0ktimersoftd/30-21swapper/322:23:023
339960,0migration/332236-21sh23:57:073
339960,0migration/327377-21sh22:00:083
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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