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2026-02-05 - 11:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Thu Feb 05, 2026 00:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2919824837,0sleep00-21swapper/019:12:390
2930623627,0sleep20-21swapper/219:13:572
2916823525,0sleep10-21swapper/119:12:201
2860623329,0sleep30-21swapper/319:09:543
339960,0migration/34744-21latency_hist20:49:313
339960,0migration/34433-21sh21:47:423
339960,0migration/330733-21taskset22:04:023
339960,0migration/329178-21kthreadcore23:54:493
339960,0migration/320476-21sh21:39:403
29815060,0irq/29-eth0-tx-19151-21munin-node20:14:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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