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2026-07-31 - 22:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Fri Jul 31, 2026 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2233627874,0sleep10-21swapper/107:28:131
2229926362,0sleep30-21swapper/307:27:473
2229324435,0sleep20-21swapper/207:27:422
2204623424,0sleep00-21swapper/007:24:480
22477991717,0cyclictest0-21swapper/209:29:302
29805070,0irq/28-eth0-rx-8490-21ssh09:30:073
29805070,0irq/28-eth0-rx-22591-21sensors_temp10:34:253
4160,0ktimersoftd/00-21swapper/010:01:350
35160,0ktimersoftd/30-21swapper/312:42:303
35160,0ktimersoftd/30-21swapper/312:42:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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