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2026-04-08 - 00:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Tue Apr 07, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2239828783,0sleep20-21swapper/207:18:452
2244427261,0sleep00-21swapper/007:19:190
2229425453,0sleep10-21swapper/107:17:361
22545994646,0cyclictest2900-21md1_resync09:11:572
2237623627,0sleep30-21swapper/307:18:303
22544992626,0cyclictest191ktimersoftd/109:11:571
8305060,0irq/26-0000:00:3957-21kthreadcore08:09:563
8305060,0irq/26-0000:00:3383-21iostat07:49:533
8305060,0irq/26-0000:00:28444-21crond08:29:373
8305060,0irq/26-0000:00:23126-21port_sshpriv07:59:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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