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2026-01-22 - 09:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Thu Jan 22, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1087323828,0sleep30-21swapper/319:12:233
403723727,0sleep10-21swapper/119:08:321
1057923627,0sleep20-21swapper/219:08:542
1059723524,0sleep00-21swapper/019:09:080
110289976,0cyclictest30694-21kthreadcore20:08:390
8305060,0irq/26-0000:00:2138-21crond00:08:212
339960,0migration/38014-21sh21:03:213
339960,0migration/34671-21kthreadcore22:53:383
339960,0migration/330538-21taskset21:17:213
339960,0migration/316781-21kthreadcore22:03:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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