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2026-02-01 - 10:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Sun Feb 01, 2026 00:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1722824534,0sleep00-21swapper/019:10:250
1485424435,0sleep30-21swapper/319:09:443
1741123627,0sleep10-21swapper/119:12:341
1724723526,0sleep20-21swapper/219:10:392
1762199140,0cyclictest0-21swapper/020:02:590
339970,0migration/319028-21sh22:03:593
8305060,0irq/26-0000:00:18168-21munin-run20:44:113
65269760,0rudpserv9219-21cut22:14:283
65269760,0rudpserv9102-21fschecks_count21:39:243
65269760,0rudpserv8568-21perl20:59:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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