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2026-04-30 - 19:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Thu Apr 30, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
271790,0ktimersoftd/220319-21perf07:21:202
2087123829,0sleep30-21swapper/307:20:323
2092423724,0sleep00-21swapper/007:21:090
2072623725,0sleep10-21swapper/107:18:501
210269999,0cyclictest13969-21sensors10:06:540
210279976,0cyclictest0-21swapper/112:01:511
339960,0migration/36767-21sh10:04:553
339960,0migration/34368-21sh09:44:513
339960,0migration/320960-21aten_r1power_vo10:51:423
339960,0migration/320653-21kthreadcore12:41:483
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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