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2026-07-30 - 22:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Thu Jul 30, 2026 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1518625241,0sleep00-21swapper/007:28:380
1515024233,0sleep10-21swapper/107:28:111
1510023624,0sleep20-21swapper/207:27:402
1490023525,0sleep30-21swapper/307:25:173
15282991616,0cyclictest2964-21sensors09:49:220
339960,0migration/39410-21munin-node12:24:243
339960,0migration/330181-21sh10:07:443
339960,0migration/329065-21sh11:22:523
339960,0migration/321479-21munin-node12:34:143
339960,0migration/318858-21kthreadcore09:59:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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