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2026-01-29 - 09:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Thu Jan 29, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1034825554,0sleep10-21swapper/119:12:451
1017323727,0sleep30-21swapper/319:10:433
1029923626,0sleep20-21swapper/219:12:102
1041623127,0sleep00-21swapper/019:13:330
10521991616,0cyclictest0-21swapper/223:02:132
10521991414,0cyclictest0-21swapper/222:02:132
10521991211,0cyclictest17815-21chrt20:02:372
10521991211,0cyclictest17815-21chrt20:02:372
10519991212,0cyclictest0-21swapper/021:02:340
105199999,0cyclictest0-21swapper/023:02:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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