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2026-08-29 - 02:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Sat Aug 29, 2026 00:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251323627,0sleep20-21swapper/219:26:322
227423526,0sleep10-21swapper/119:26:221
950822925,0sleep00-21swapper/019:31:020
947322925,0sleep30-21swapper/319:30:373
96139966,0cyclictest0-21swapper/200:46:372
96139965,0cyclictest1418-21ssh22:01:142
96049960,0cyclictest0-21swapper/000:41:420
339960,0migration/38119-21sh00:52:053
339960,0migration/37280-21kthreadcore19:51:403
339960,0migration/331038-21sh00:30:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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