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2026-02-26 - 12:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Thu Feb 26, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2121224028,0sleep20-21swapper/219:14:442
2055223425,0sleep10-21swapper/119:11:391
2130523228,0sleep00-21swapper/019:15:500
2101222925,0sleep30-21swapper/319:12:213
8305060,0irq/26-0000:00:8018-21dump-pmu-power22:16:152
339960,0migration/326134-21unixbench_singl23:56:403
339960,0migration/32574-21sh00:02:003
339960,0migration/318887-21sh22:56:363
339960,0migration/31560-21sh23:45:323
29815060,0irq/29-eth0-tx-29338-21munin-node20:51:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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