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2026-04-17 - 12:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Fri Apr 17, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2116524738,0sleep20-21swapper/219:17:262
2116123728,0sleep30-21swapper/319:17:233
2126923624,0sleep00-21swapper/019:18:400
2126523425,0sleep10-21swapper/119:18:371
21511992020,0cyclictest0-21swapper/221:20:512
339960,0migration/330390-21sh00:42:553
339960,0migration/325874-21kthreadcore22:10:423
339960,0migration/324034-21sh23:42:523
339960,0migration/322637-21sh22:09:293
339960,0migration/315443-21sh22:22:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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