You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-19 - 12:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Thu Feb 19, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1199726564,0sleep20-21swapper/219:12:392
1210923928,0sleep00-21swapper/019:13:570
1224023526,0sleep10-21swapper/119:15:301
1212822925,0sleep30-21swapper/319:14:123
123299999,0cyclictest0-21swapper/221:16:072
123289999,0cyclictest3524-21snmpd22:49:441
123289977,0cyclictest3571-21lldpd23:43:381
8305060,0irq/26-0000:00:0-21swapper/221:10:402
339960,0migration/329643-21sh21:40:363
339960,0migration/328775-21sendmail_mailqu00:06:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional