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2026-06-24 - 17:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Wed Jun 24, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
601924939,0sleep30-21swapper/307:23:423
587224937,0sleep20-21swapper/207:22:012
598823430,0sleep10-21swapper/107:23:201
617823127,0sleep00-21swapper/007:25:310
62919970,0cyclictest14702-21grep07:51:200
62939960,0cyclictest0-21swapper/210:04:122
62919960,0cyclictest0-21swapper/010:43:010
339960,0migration/331030-21kthreadcore09:31:203
339960,0migration/327647-21sh10:45:413
339960,0migration/325379-21sh11:39:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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