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2026-07-28 - 22:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Tue Jul 28, 2026 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2969528988,0sleep30-21swapper/307:28:053
2972325958,0sleep00-21swapper/007:28:220
29838995050,0cyclictest3016-21md1_resync12:01:341
29844994141,0cyclictest83050irq/26-0000:00:12:01:342
2941623526,0sleep20-21swapper/207:24:552
2943123329,0sleep10-21swapper/107:25:061
29828993131,0cyclictest30260-21kworker/0:212:01:340
29828991111,0cyclictest5004-21sensors09:19:120
35170,0ktimersoftd/327222-21grep09:14:063
8305060,0irq/26-0000:00:0-21swapper/211:22:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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