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2026-07-05 - 01:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Sat Jul 04, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2700523829,0sleep10-21swapper/107:24:441
2714423728,0sleep30-21swapper/307:26:223
2028023635,0sleep20-21swapper/207:22:012
2682722824,0sleep00-21swapper/007:22:390
339960,0migration/38499-21timerwakeupswit12:12:173
339960,0migration/332473-21sh12:07:453
339960,0migration/322722-21kthreadcore12:22:083
339960,0migration/318773-21sh10:08:243
339960,0migration/314946-21sh10:44:113
339960,0migration/31219-21munin-node08:12:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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