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2026-07-12 - 09:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Sun Jul 12, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
902823829,0sleep20-21swapper/219:24:072
906523728,0sleep10-21swapper/119:24:301
904323524,0sleep00-21swapper/019:24:170
905623228,0sleep30-21swapper/319:24:283
93969960,0cyclictest0-21swapper/200:20:442
93919966,0cyclictest19802-21sensors20:37:491
93919965,0cyclictest0-21swapper/121:17:451
93919965,0cyclictest0-21swapper/121:17:451
93919960,0cyclictest0-21swapper/122:27:271
93919960,0cyclictest0-21swapper/100:15:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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