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2026-04-10 - 10:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Fri Apr 10, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1954724940,0sleep20-21swapper/219:19:482
1917323625,0sleep30-21swapper/319:15:293
1949523329,0sleep10-21swapper/119:19:151
1929322824,0sleep00-21swapper/019:16:540
29805070,0irq/28-eth0-rx-0-21swapper/323:51:583
196169976,0cyclictest4715-21munin-node00:30:121
35160,0ktimersoftd/30-21swapper/321:05:013
339960,0migration/36290-21sh21:22:263
339960,0migration/331617-21kthreadcore19:25:073
339960,0migration/328935-21sh22:13:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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