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2026-06-26 - 18:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Fri Jun 26, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1071725241,0sleep00-21swapper/007:24:150
1055225041,0sleep20-21swapper/207:22:212
1080624435,0sleep10-21swapper/107:25:161
1014823827,0sleep30-21swapper/307:21:373
339960,0migration/34135-21latency_hist08:51:113
339960,0migration/327876-21munin-node10:21:363
339960,0migration/324894-21kthreadcore12:51:293
339960,0migration/320292-21sh11:32:253
339960,0migration/311357-21sh08:56:113
29805060,0irq/28-eth0-rx-5730-21kthreadcore11:06:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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