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2026-06-30 - 22:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot2.osadl.org (updated Tue Jun 30, 2026 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2705627069,0sleep00-21swapper/007:23:200
27416995151,0cyclictest83050irq/26-0000:00:09:32:452
27413994646,0cyclictest522-21kworker/0:009:32:460
2640924635,0sleep10-21swapper/107:21:531
27414994242,0cyclictest28225-21md1_resync09:32:451
2026824140,0sleep20-21swapper/207:21:422
2732223828,0sleep30-21swapper/307:26:193
27416991414,0cyclictest83050irq/26-0000:00:11:05:112
27416991111,0cyclictest83050irq/26-0000:00:10:33:232
27416991111,0cyclictest83050irq/26-0000:00:10:03:512
27416991010,0cyclictest83050irq/26-0000:00:11:36:002
274169999,0cyclictest83050irq/26-0000:00:12:54:352
274169988,0cyclictest83050irq/26-0000:00:12:50:322
274169988,0cyclictest83050irq/26-0000:00:11:53:432
274169988,0cyclictest83050irq/26-0000:00:09:58:512
274169988,0cyclictest83050irq/26-0000:00:09:48:382
4170,0ktimersoftd/00-21swapper/010:24:380
274169977,0cyclictest83050irq/26-0000:00:12:27:302
274169977,0cyclictest83050irq/26-0000:00:12:16:592
274169977,0cyclictest83050irq/26-0000:00:11:25:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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