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2025-11-10 - 23:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot2.osadl.org (updated Mon Nov 10, 2025 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1367523727,0sleep30-21swapper/306:18:543
1347723727,0sleep20-21swapper/206:16:372
1374223625,0sleep00-21swapper/006:19:430
1359823525,0sleep10-21swapper/106:18:001
329970,0watchdog/30-21swapper/309:30:523
329970,0watchdog/30-21swapper/309:27:283
29925070,0irq/32-eth0-rx-9379-21cut10:00:563
29925070,0irq/32-eth0-rx-0-21swapper/311:37:463
29925070,0irq/32-eth0-rx-0-21swapper/311:07:433
138879977,0cyclictest0-21swapper/008:21:000
4160,0ktimersoftd/00-21swapper/010:19:500
339960,0migration/38741-21irqrtprio07:45:543
329960,0watchdog/397912sleep311:17:353
329960,0watchdog/3299250irq/32-eth0-rx-09:12:163
329960,0watchdog/30-21swapper/311:45:353
329960,0watchdog/30-21swapper/311:43:473
329960,0watchdog/30-21swapper/311:25:393
329960,0watchdog/30-21swapper/311:11:483
329960,0watchdog/30-21swapper/311:11:483
329960,0watchdog/30-21swapper/310:57:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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