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2026-02-15 - 23:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot2.osadl.org (updated Sun Feb 15, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
471223723,0sleep00-21swapper/007:14:440
470823624,0sleep10-21swapper/107:14:411
465423627,0sleep20-21swapper/207:14:062
457223026,0sleep30-21swapper/307:13:113
48399960,0cyclictest0-21swapper/112:19:271
48389963,0cyclictest11595-21kworker/0:211:15:480
35160,0ktimersoftd/30-21swapper/312:45:123
35160,0ktimersoftd/30-21swapper/312:32:073
339960,0migration/328877-21munin-node11:10:493
339960,0migration/324027-21taskset11:29:153
339960,0migration/317534-21sh11:43:493
339960,0migration/311318-21sh07:15:463
29815060,0irq/29-eth0-tx-2022-21munin-node09:05:360
29805060,0irq/28-eth0-rx-24677-21sort10:15:373
29805060,0irq/28-eth0-rx-1812-21sh11:52:163
27160,0ktimersoftd/20-21swapper/211:58:222
149960,0migration/013693-21latency_hist11:05:230
48439955,0cyclictest0-21swapper/209:51:582
48439950,0cyclictest0-21swapper/212:32:372
48439950,0cyclictest0-21swapper/211:49:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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