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2026-03-02 - 11:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot2.osadl.org (updated Mon Mar 02, 2026 00:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1954025352,0sleep10-21swapper/119:11:461
2618223726,0sleep30-21swapper/319:13:253
2641623626,0sleep20-21swapper/219:16:082
2619523625,0sleep00-21swapper/019:13:300
339960,0migration/37839-21sh00:05:003
339960,0migration/36249-21sh23:46:323
339960,0migration/331740-21sh22:44:493
339960,0migration/323417-21sh21:26:443
339960,0migration/322399-21sh22:37:413
339960,0migration/322131-21sh21:24:123
339960,0migration/310433-21sh23:11:033
29805060,0irq/28-eth0-rx-12011-21sh22:13:343
29805060,0irq/28-eth0-rx-0-21swapper/323:31:463
265309965,0cyclictest15585-21cat22:16:532
149960,0migration/05864-21sh21:16:410
149960,0migration/026345-21timerwakeupswit22:02:010
149960,0migration/022231-21sh23:53:050
149960,0migration/019286-21latency_hist00:31:360
339950,0migration/34703-21kthreadcore20:51:533
339950,0migration/33903-21kthreadcore22:46:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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