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2026-05-29 - 00:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot2.osadl.org (updated Thu May 28, 2026 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
675428580,0sleep20-21swapper/207:23:072
659724435,0sleep10-21swapper/107:21:181
648423026,0sleep00-21swapper/007:20:010
660422723,0sleep30-21swapper/307:21:243
6893992020,0cyclictest83050irq/26-0000:00:09:35:162
68939960,0cyclictest0-21swapper/210:43:572
68919965,0cyclictest6065-21kworker/0:010:01:520
68919965,0cyclictest6065-21kworker/0:007:34:080
339960,0migration/39051-21rt-features11:44:103
339960,0migration/331501-21sh12:36:003
339960,0migration/328047-21munin-node08:19:133
329960,0watchdog/321411-21sh10:39:043
29805060,0irq/28-eth0-rx-453-21kthreadcore09:09:063
29805060,0irq/28-eth0-rx-24589-21fschecks_time10:04:023
29805060,0irq/28-eth0-rx-19439-21memory10:54:073
149960,0migration/011630-21fschecks_count10:34:020
68939955,0cyclictest18064-21diskmemload09:40:432
68939955,0cyclictest0-21swapper/208:29:182
68939954,0cyclictest3524-21snmpd11:56:162
68939953,0cyclictest3524-21snmpd11:44:162
68939950,0cyclictest0-21swapper/210:34:392
68929950,0cyclictest0-21swapper/112:50:431
68919955,0cyclictest955-21kworker/0:112:48:510
68919955,0cyclictest955-21kworker/0:112:43:590
68919955,0cyclictest955-21kworker/0:112:39:050
68919955,0cyclictest955-21kworker/0:112:34:030
68919955,0cyclictest955-21kworker/0:112:28:590
68919955,0cyclictest955-21kworker/0:112:23:510
68919955,0cyclictest955-21kworker/0:112:18:570
68919955,0cyclictest955-21kworker/0:112:14:210
68919955,0cyclictest955-21kworker/0:112:09:230
68919955,0cyclictest955-21kworker/0:112:03:510
68919955,0cyclictest955-21kworker/0:111:59:270
68919955,0cyclictest955-21kworker/0:111:53:530
68919955,0cyclictest955-21kworker/0:111:49:050
68919955,0cyclictest955-21kworker/0:111:43:500
68919955,0cyclictest955-21kworker/0:111:34:080
68919955,0cyclictest955-21kworker/0:111:28:560
68919955,0cyclictest955-21kworker/0:111:23:520
68919955,0cyclictest955-21kworker/0:111:18:540
68919955,0cyclictest955-21kworker/0:111:13:540
68919955,0cyclictest955-21kworker/0:111:09:040
68919955,0cyclictest955-21kworker/0:110:59:020
68919955,0cyclictest955-21kworker/0:110:53:560
68919955,0cyclictest955-21kworker/0:110:48:500
68919955,0cyclictest955-21kworker/0:110:44:080
68919955,0cyclictest955-21kworker/0:110:38:560
68919955,0cyclictest955-21kworker/0:110:28:560
68919955,0cyclictest955-21kworker/0:110:23:520
68919955,0cyclictest955-21kworker/0:110:18:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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