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2026-08-05 - 07:28

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot2s.osadl.org (updated Wed Aug 05, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304450970,0irq/25-eth10-21swapper/318:47:183
52524938,0sleep00-21swapper/018:44:220
46823531,0sleep20-21swapper/218:43:442
2692823425,0sleep10-21swapper/118:42:511
9359960,0cyclictest31483-21diskmemload22:12:302
9349966,0cyclictest31483-21diskmemload22:51:401
339960,0migration/36473-21sh20:51:333
339960,0migration/32814-21sh23:11:403
339960,0migration/319919-21sh22:19:143
29725060,0irq/27-eth0-tx-25006-21munin-node23:23:082
29715060,0irq/26-eth0-rx-15440-21cut22:38:053
29715060,0irq/26-eth0-rx-1081-21seq23:28:193
29715060,0irq/26-eth0-rx-0-21swapper/322:34:163
9359955,0cyclictest0-21swapper/223:17:092
9359955,0cyclictest0-21swapper/222:49:052
9359955,0cyclictest0-21swapper/221:21:162
9359950,0cyclictest0-21swapper/222:32:222
9359950,0cyclictest0-21swapper/221:39:522
9359950,0cyclictest0-21swapper/220:48:002
9359950,0cyclictest0-21swapper/200:07:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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