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2026-01-16 - 08:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot2s.osadl.org (updated Fri Jan 16, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
784125040,0sleep30-21swapper/319:05:563
771524025,0sleep00-21swapper/019:04:250
784423526,0sleep10-21swapper/119:05:581
779723525,0sleep20-21swapper/219:05:232
7989991313,0cyclictest25584-21kworker/0:019:17:050
7989991212,0cyclictest28361-21kworker/0:123:45:000
7989991111,0cyclictest25584-21kworker/0:019:37:050
7989991010,0cyclictest28361-21kworker/0:123:30:140
7989991010,0cyclictest25584-21kworker/0:021:20:510
79899999,0cyclictest28361-21kworker/0:123:58:140
79899999,0cyclictest28361-21kworker/0:123:04:280
79899999,0cyclictest28361-21kworker/0:122:44:060
79899999,0cyclictest28361-21kworker/0:122:35:460
79899999,0cyclictest28361-21kworker/0:100:34:160
79899999,0cyclictest28361-21kworker/0:100:27:080
79899999,0cyclictest28361-21kworker/0:100:14:280
79899999,0cyclictest25584-21kworker/0:021:42:120
79899999,0cyclictest25584-21kworker/0:021:39:260
79899999,0cyclictest25584-21kworker/0:021:26:550
79899999,0cyclictest25584-21kworker/0:021:22:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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