You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-05 - 09:20

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #1, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot2s.osadl.org (updated Tue May 05, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1111023723,0sleep00-21swapper/018:53:350
304450350,0irq/25-eth10-21swapper/318:52:223
1127923425,0sleep10-21swapper/118:55:331
1113623026,0sleep20-21swapper/218:53:542
11437992121,0cyclictest9667-21sadc20:56:330
11437991212,0cyclictest10809-21kworker/0:222:51:480
11437991212,0cyclictest10809-21kworker/0:222:26:440
11437991111,0cyclictest1400-21kworker/0:019:51:550
11437991111,0cyclictest1400-21kworker/0:019:46:550
11437991111,0cyclictest10809-21kworker/0:221:56:520
11437991010,0cyclictest9512-21kworker/0:023:33:040
11437991010,0cyclictest9512-21kworker/0:023:25:500
11437991010,0cyclictest9512-21kworker/0:000:06:500
11437991010,0cyclictest1400-21kworker/0:020:01:550
11437991010,0cyclictest1400-21kworker/0:019:21:550
11437991010,0cyclictest10809-21kworker/0:222:12:340
11437991010,0cyclictest10809-21kworker/0:221:52:380
114379999,0cyclictest9512-21kworker/0:023:52:500
114379999,0cyclictest9512-21kworker/0:023:11:580
114379999,0cyclictest1400-21kworker/0:021:31:010
114379999,0cyclictest1400-21kworker/0:021:16:510
114379999,0cyclictest1400-21kworker/0:021:06:510
114379999,0cyclictest1400-21kworker/0:020:46:490
114379999,0cyclictest1400-21kworker/0:020:21:550
114379999,0cyclictest1400-21kworker/0:019:27:110
114379999,0cyclictest10809-21kworker/0:222:18:460
114389984,0cyclictest26717-21sadc19:56:331
114389983,0cyclictest16651-21awk00:01:481
114379988,0cyclictest9512-21kworker/0:023:36:460
114379988,0cyclictest9512-21kworker/0:023:31:280
114379988,0cyclictest9512-21kworker/0:023:19:120
114379988,0cyclictest9512-21kworker/0:000:02:580
114379988,0cyclictest1400-21kworker/0:021:31:470
114379988,0cyclictest1400-21kworker/0:021:11:470
114379988,0cyclictest1400-21kworker/0:021:00:490
114379988,0cyclictest1400-21kworker/0:019:56:450
114379988,0cyclictest10809-21kworker/0:222:41:460
114379988,0cyclictest10809-21kworker/0:222:09:320
114379988,0cyclictest10809-21kworker/0:221:49:160
114379988,0cyclictest10809-21kworker/0:221:41:170
114389973,0cyclictest9742-21sadc21:36:331
114389973,0cyclictest3556-21lldpd23:38:111
114389973,0cyclictest3556-21lldpd22:48:411
114389973,0cyclictest18229-21awk22:21:461
114389972,0cyclictest16421-21awk00:21:471
114379977,0cyclictest9512-21kworker/0:023:49:280
114379977,0cyclictest9512-21kworker/0:023:05:500
114379977,0cyclictest9512-21kworker/0:022:59:020
114379977,0cyclictest9512-21kworker/0:000:16:520
114379977,0cyclictest9512-21kworker/0:000:12:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional