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2026-06-18 - 18:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot3.osadl.org (updated Thu Jun 18, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165094899130,11cyclictest0-21swapper/310:45:123
165094899130,11cyclictest0-21swapper/307:45:103
1650948991211,0cyclictest0-21swapper/309:45:103
1650948991210,1cyclictest0-21swapper/309:20:123
1650948991210,1cyclictest0-21swapper/307:55:113
165094899120,11cyclictest0-21swapper/312:25:013
165094899120,11cyclictest0-21swapper/310:55:213
165094899120,11cyclictest0-21swapper/310:20:013
165094899120,11cyclictest0-21swapper/310:15:023
165094899120,11cyclictest0-21swapper/309:35:123
165094899120,11cyclictest0-21swapper/309:00:103
165094899120,11cyclictest0-21swapper/308:45:113
165094899120,10cyclictest0-21swapper/312:15:123
165094899120,10cyclictest0-21swapper/312:10:133
165094899120,10cyclictest0-21swapper/309:10:113
1650948991111,0cyclictest0-21swapper/308:55:193
1650948991110,0cyclictest0-21swapper/312:25:133
165094899110,9cyclictest0-21swapper/310:30:113
165094899110,10cyclictest0-21swapper/308:10:163
165094899110,0cyclictest0-21swapper/307:20:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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