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2026-01-29 - 02:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 376 highest latencies:
System rack1slot6 (updated Thu Jan 29, 2026 00:46:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5413
"cycles":100000000,5412
"load":"idle",5411
"condition":{5410
"clock":"2130"5408
"family":"x86",5407
"vendor":"Intel",5406
"processor":{5404
"dataset":"2024-01-08T15:39:30+0100"5402
"origin":"2024-01-08T12:43:23+0100",5401
"timestamps":{5400
"granularity":"microseconds"5398
8822:50:455396
84,22:50:415395
120,22:51:175394
117,22:51:145393
"maxima":[5392
022:49:175389
0,22:49:175388
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3,22:49:205078
1,22:49:185077
2,22:49:195076
3,22:49:205075
4,22:49:215074
8,22:49:255073
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13,22:49:305071
17,22:49:345070
22,22:49:395069
33,22:49:505068
42,22:49:595067
36,22:49:535066
67,22:50:245065
105,22:51:025064
125,22:51:225063
175,22:52:125062
274,22:53:515061
305,22:54:225060
385,22:55:425059
416,22:56:135058
482,22:57:195057
679,23:00:365056
809,23:02:465055
875,23:03:525054
811,23:02:485053
722,23:01:195052
577,22:58:545051
587,22:59:045050
704,23:01:015049
739,23:01:365048
552,22:58:295047
394,22:55:515046
303,22:54:205045
323,22:54:405044
282,22:53:595043
285,22:54:025042
290,22:54:075041
478,22:57:155040
796,23:02:335039
1442,23:13:195038
2389,23:29:065037
2582,23:32:195036
2320,23:27:575035
2491,23:30:485034
3185,23:42:225033
4154,23:58:315032
5045,00:13:225031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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