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2026-07-15 - 00:24

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot6s.osadl.org (updated Tue Jul 14, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26174991024,91cyclictest0-21swapper/208:57:572
54892970,4sleep05492-21wc08:51:410
2617499943,65cyclictest0-21swapper/211:30:462
26174999411,63cyclictest0-21swapper/210:27:352
2617499934,81cyclictest0-21swapper/211:41:512
2617499924,68cyclictest0-21swapper/209:11:382
26174999114,61cyclictest22869-21df_abs08:31:272
2617499896,65cyclictest0-21swapper/211:48:212
2617499894,63cyclictest0-21swapper/209:19:502
2617499894,55cyclictest0-21swapper/210:16:242
2617499894,52cyclictest0-21swapper/207:14:422
2617499893,79cyclictest0-21swapper/207:10:272
26174998912,52cyclictest14293-21ssh09:06:222
26174998911,53cyclictest0-21swapper/210:01:282
26174998911,53cyclictest0-21swapper/210:01:282
2617499884,64cyclictest0-21swapper/209:57:182
2617499884,64cyclictest0-21swapper/208:40:332
2617499884,59cyclictest0-21swapper/210:21:222
26174998814,49cyclictest0-21swapper/210:59:542
2617499874,63cyclictest0-21swapper/207:16:272
2617499874,62cyclictest0-21swapper/208:46:352
2617499874,62cyclictest0-21swapper/208:46:352
2617499874,53cyclictest0-21swapper/208:51:192
2617499873,8cyclictest9769-21ssh11:21:352
2617499873,7cyclictest13619-21ssh09:51:372
2617499873,52cyclictest0-21swapper/210:53:052
2617499873,17cyclictest0-21swapper/208:12:462
2617499873,11cyclictest0-21swapper/209:30:102
2617499867,63cyclictest0-21swapper/209:47:492
2617499867,55cyclictest0-21swapper/207:36:242
2617499866,62cyclictest0-21swapper/210:33:022
2617499864,68cyclictest0-21swapper/211:06:132
2617499864,59cyclictest0-21swapper/211:20:362
2617499864,59cyclictest0-21swapper/211:20:362
2617499864,58cyclictest0-21swapper/211:05:532
2617499863,73cyclictest0-21swapper/209:21:382
2617499863,73cyclictest0-21swapper/209:21:382
2617499863,59cyclictest0-21swapper/209:38:562
2617499863,57cyclictest0-21swapper/207:21:302
2617499854,8cyclictest18694-21cpuspeed_turbos11:36:192
2617499854,73cyclictest0-21swapper/211:31:262
2617499854,73cyclictest0-21swapper/210:06:292
2617499854,59cyclictest0-21swapper/210:41:192
2617499854,57cyclictest0-21swapper/209:33:512
2617499853,9cyclictest4500-21ssh11:15:342
2617499853,58cyclictest0-21swapper/206:27:542
26174998517,51cyclictest0-21swapper/208:41:482
26174998517,51cyclictest0-21swapper/208:41:482
26174998514,53cyclictest0-21swapper/207:01:322
2617499847,55cyclictest107550irq/46-eth009:03:532
2617499845,63cyclictest0-21swapper/209:43:592
2617499844,72cyclictest0-21swapper/210:46:382
2617499843,57cyclictest0-21swapper/210:40:082
2617499843,57cyclictest0-21swapper/210:40:082
26174998414,47cyclictest0-21swapper/208:26:242
2617499838,51cyclictest27642-21ssh10:11:502
2617499834,10cyclictest29101-21tr06:31:312
2617499833,57cyclictest0-21swapper/207:54:442
2617499824,57cyclictest0-21swapper/211:51:402
2617499823,59cyclictest0-21swapper/208:01:442
2617499823,59cyclictest0-21swapper/208:01:442
2617499814,53cyclictest0-21swapper/206:56:172
2617499813,52cyclictest29924-21munin-node07:41:402
219499810,5rtkit-daemon2193-21rtkit-daemon11:12:531
2617499804,69cyclictest0-21swapper/207:26:572
2617499804,64cyclictest0-21swapper/207:31:482
2617499804,59cyclictest0-21swapper/208:06:482
26171998024,48cyclictest0-21swapper/011:10:140
2617499797,56cyclictest0-21swapper/206:41:292
2617499784,48cyclictest0-21swapper/208:16:322
2617499784,11cyclictest0-21swapper/207:46:442
26171997721,48cyclictest0-21swapper/011:21:180
219499770,5rtkit-daemon2193-21rtkit-daemon10:25:550
26174997615,43cyclictest16784-21telnet08:21:242
2617499754,56cyclictest0-21swapper/206:38:322
2617499754,56cyclictest0-21swapper/206:38:322
26174997518,41cyclictest0-21swapper/206:46:362
26171997523,44cyclictest22674-21ssh10:06:240
2617599744,60cyclictest0-21swapper/309:41:343
26171997328,38cyclictest18714-21ssh11:36:200
26171997326,41cyclictest17404-21grep09:56:440
26171997325,41cyclictest23721-21munin-node10:56:390
26171997325,41cyclictest11711-21gltestperf09:01:300
26171997316,38cyclictest4228-21sshd06:46:330
26171997315,33cyclictest0-21swapper/011:35:060
2617499724,48cyclictest0-21swapper/206:57:402
26171997229,36cyclictest12506-21df_abs08:11:300
26171997221,44cyclictest0-21swapper/009:46:320
26171997219,45cyclictest0-21swapper/008:31:270
2617499716,58cyclictest0-21swapper/207:56:292
26171997122,42cyclictest0-21swapper/010:11:320
26171997121,42cyclictest0-21swapper/007:06:150
26171997121,17cyclictest0-21swapper/009:36:280
26171997115,47cyclictest0-21swapper/009:06:230
26171997022,41cyclictest0-21swapper/010:54:260
26171997022,33cyclictest0-21swapper/011:11:230
26171997021,41cyclictest0-21swapper/008:56:350
26171997021,32cyclictest0-21swapper/011:26:230
26171997021,32cyclictest0-21swapper/011:16:350
26171997021,32cyclictest0-21swapper/011:16:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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