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2026-09-24 - 01:30

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot6s.osadl.org (updated Thu Sep 24, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
47689910321,10cyclictest20467-21missed_timers21:29:181
4768999923,10cyclictest16605-21hwlatdetect18:49:211
476899974,24cyclictest0-21swapper/121:37:131
476899974,24cyclictest0-21swapper/121:37:131
4768999616,13cyclictest0-21swapper/121:54:231
476899954,67cyclictest0-21swapper/122:39:051
476899944,28cyclictest0-21swapper/122:14:101
476899944,28cyclictest0-21swapper/122:14:101
476899943,28cyclictest0-21swapper/120:34:301
476899935,25cyclictest0-21swapper/120:29:141
476899934,24cyclictest0-21swapper/121:18:441
476899934,20cyclictest0-21swapper/122:21:221
476899934,20cyclictest0-21swapper/122:21:221
4768999316,13cyclictest0-21swapper/121:59:071
477099924,81cyclictest0-21swapper/322:05:313
477099923,54cyclictest22195-21gltestperf19:54:183
476899924,28cyclictest0-21swapper/120:02:041
4768999217,60cyclictest0-21swapper/122:32:041
4768999216,13cyclictest0-21swapper/122:09:061
477099914,82cyclictest0-21swapper/319:39:213
476899916,24cyclictest0-21swapper/121:42:091
476899914,28cyclictest0-21swapper/122:24:241
476899914,26cyclictest0-21swapper/119:14:331
476899914,25cyclictest0-21swapper/120:47:261
476899914,25cyclictest0-21swapper/119:26:151
476899914,24cyclictest0-21swapper/120:49:141
476899913,27cyclictest0-21swapper/120:58:571
476899913,27cyclictest0-21swapper/120:58:571
476899913,25cyclictest0-21swapper/122:37:391
477099904,67cyclictest0-21swapper/322:29:073
476899904,29cyclictest0-21swapper/120:13:501
476899904,26cyclictest0-21swapper/121:25:241
476899904,26cyclictest0-21swapper/119:32:171
476899904,25cyclictest0-21swapper/120:17:491
476899904,25cyclictest0-21swapper/120:17:491
477099894,78cyclictest0-21swapper/320:09:303
477099893,53cyclictest0-21swapper/321:48:383
476899895,25cyclictest0-21swapper/121:20:101
476899894,27cyclictest0-21swapper/121:06:381
476899894,25cyclictest0-21swapper/122:06:541
4768998919,12cyclictest0-21swapper/119:24:001
4768998916,13cyclictest0-21swapper/121:49:321
476899884,27cyclictest0-21swapper/120:39:351
4768998820,12cyclictest0-21swapper/122:43:581
477099875,75cyclictest0-21swapper/320:31:153
476899874,28cyclictest0-21swapper/117:34:231
476899874,27cyclictest0-21swapper/118:54:281
476899874,27cyclictest0-21swapper/118:54:281
476899874,25cyclictest0-21swapper/118:22:161
477099864,76cyclictest0-21swapper/318:14:193
477099862,49cyclictest0-21swapper/319:50:593
476899865,23cyclictest0-21swapper/120:04:001
476899865,23cyclictest0-21swapper/119:51:381
476899864,28cyclictest0-21swapper/118:34:191
476899864,26cyclictest0-21swapper/119:57:391
476899864,23cyclictest0-21swapper/121:11:531
476899863,25cyclictest0-21swapper/120:26:071
4768998617,13cyclictest0-21swapper/117:55:271
477099854,75cyclictest0-21swapper/321:58:053
477099854,65cyclictest0-21swapper/319:20:433
477099854,64cyclictest0-21swapper/320:48:283
477099853,74cyclictest21734-21sed20:43:573
476899854,74cyclictest0-21swapper/117:24:351
476899854,74cyclictest0-21swapper/117:24:351
476899854,71cyclictest9980-21ssh19:35:121
476899854,28cyclictest0-21swapper/121:02:151
476899854,28cyclictest0-21swapper/121:02:151
476899854,27cyclictest0-21swapper/117:39:291
476899854,26cyclictest0-21swapper/119:43:111
476899853,29cyclictest0-21swapper/120:20:371
477099845,62cyclictest0-21swapper/321:11:303
477099845,60cyclictest0-21swapper/321:52:183
477099844,75cyclictest0-21swapper/320:07:153
477099844,74cyclictest0-21swapper/322:01:583
477099844,73cyclictest0-21swapper/321:34:263
477099844,73cyclictest0-21swapper/321:34:263
477099844,63cyclictest0-21swapper/319:37:003
477099843,58cyclictest9113-21kworker/3:121:29:133
477099842,59cyclictest0-21swapper/320:25:523
476899845,23cyclictest0-21swapper/119:48:331
4768998421,9cyclictest13591-21cpuspeed_turbos18:44:131
477099834,73cyclictest0-21swapper/320:59:273
477099834,73cyclictest0-21swapper/320:59:273
477099834,73cyclictest0-21swapper/320:51:313
477099834,61cyclictest0-21swapper/321:16:523
477099833,73cyclictest15700-21cut20:34:113
477099833,49cyclictest0-21swapper/321:42:163
477099833,48cyclictest0-21swapper/319:33:143
476899834,71cyclictest0-21swapper/121:43:571
477099825,69cyclictest0-21swapper/321:19:153
477099825,69cyclictest0-21swapper/320:14:093
477099825,69cyclictest0-21swapper/320:14:093
477099825,68cyclictest18506-21yum22:14:303
477099825,68cyclictest18506-21yum22:14:303
477099824,72cyclictest0-21swapper/322:19:063
477099824,72cyclictest0-21swapper/322:19:063
477099824,72cyclictest0-21swapper/321:23:563
477099824,71cyclictest5014-21taskset17:19:153
477099824,71cyclictest0-21swapper/317:19:063
477099824,49cyclictest2807-21aten_r1power_cu21:04:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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