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2026-02-11 - 00:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot6s.osadl.org (updated Tue Feb 10, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174839910330,13cyclictest0-21swapper/006:19:320
17483999810,21cyclictest17790-21munin-node10:49:330
17483999727,13cyclictest0-21swapper/007:54:300
17483999727,13cyclictest0-21swapper/007:54:300
248599950,7rtkit-daemon0-21swapper/108:19:041
1748399953,26cyclictest0-21swapper/009:56:130
1748399953,26cyclictest0-21swapper/009:56:130
1748399933,22cyclictest10211-21diskmemload08:59:100
1748399924,27cyclictest0-21swapper/008:04:420
17483999229,13cyclictest0-21swapper/010:34:540
17483999229,13cyclictest0-21swapper/010:34:540
1748399914,36cyclictest0-21swapper/008:35:510
1748399914,36cyclictest0-21swapper/008:35:510
248599900,6rtkit-daemon0-21swapper/111:09:573
1748399904,35cyclictest0-21swapper/010:56:140
1748399894,27cyclictest0-21swapper/008:14:360
17483998929,12cyclictest0-21swapper/010:24:260
1748399884,26cyclictest0-21swapper/006:33:140
1748399884,26cyclictest0-21swapper/006:33:140
1748399873,26cyclictest0-21swapper/009:44:370
1748399866,24cyclictest0-21swapper/011:16:370
1748399866,24cyclictest0-21swapper/011:16:370
1748399864,28cyclictest0-21swapper/010:29:230
1748399857,23cyclictest0-21swapper/008:48:180
1748399854,25cyclictest0-21swapper/011:37:590
1748399854,25cyclictest0-21swapper/010:43:310
17483998529,13cyclictest0-21swapper/007:34:320
1748399844,25cyclictest0-21swapper/009:15:380
1748399844,25cyclictest0-21swapper/009:15:380
1748399834,25cyclictest0-21swapper/011:23:590
1748399833,29cyclictest0-21swapper/009:37:510
1748399833,27cyclictest0-21swapper/009:09:440
17483998320,13cyclictest0-21swapper/008:09:280
1748399823,28cyclictest0-21swapper/010:59:350
17483998225,12cyclictest0-21swapper/009:19:240
1748399814,34cyclictest0-21swapper/011:24:240
1748399813,26cyclictest0-21swapper/009:59:360
1748399804,25cyclictest0-21swapper/009:09:070
1748399804,14cyclictest0-21swapper/009:53:450
1748399803,34cyclictest0-21swapper/008:20:480
1748399785,15cyclictest0-21swapper/010:19:300
1748399774,15cyclictest0-21swapper/007:19:140
1748399774,15cyclictest0-21swapper/007:19:140
1749199755,62cyclictest0-21swapper/210:48:562
1748399753,24cyclictest0-21swapper/011:05:070
235712740,5sleep023570-21wc06:24:400
98562730,12sleep11748999cyclictest07:04:301
1749199735,59cyclictest0-21swapper/210:44:072
1748999724,50cyclictest0-21swapper/108:25:091
1749199714,59cyclictest0-21swapper/210:24:202
1749199705,57cyclictest0-21swapper/209:19:232
1749199704,59cyclictest0-21swapper/209:03:442
1749199695,58cyclictest0-21swapper/211:34:172
1749199684,56cyclictest20867-21gltestperf10:04:262
1748999685,13cyclictest0-21swapper/109:09:201
1749199654,53cyclictest0-21swapper/209:38:462
1748999653,56cyclictest0-21swapper/110:30:241
1749199644,53cyclictest0-21swapper/210:14:072
1748999644,53cyclictest0-21swapper/110:59:251
1749199636,49cyclictest0-21swapper/208:54:332
1749199636,49cyclictest0-21swapper/206:14:492
1749199635,50cyclictest0-21swapper/206:39:162
17491996344,13cyclictest0-21swapper/209:29:202
1748999635,50cyclictest0-21swapper/107:54:351
1748999635,50cyclictest0-21swapper/107:54:351
1748999634,52cyclictest0-21swapper/108:24:111
1748999634,51cyclictest0-21swapper/110:04:351
1748999634,49cyclictest3232-21cut09:39:201
1749199626,48cyclictest1419-21runrttasks09:48:342
1749199626,48cyclictest0-21swapper/211:04:302
1748999626,49cyclictest0-21swapper/110:09:431
1748999625,50cyclictest13390-21munin-node09:04:361
1748999624,51cyclictest0-21swapper/110:24:291
1748999624,50cyclictest0-21swapper/110:21:251
1748999624,50cyclictest0-21swapper/109:19:361
17489996221,13cyclictest0-21swapper/108:44:341
17492996147,8cyclictest15338-21munin-run11:34:043
1749299614,12cyclictest0-21swapper/309:49:233
17492996132,13cyclictest0-21swapper/309:54:303
17492996132,13cyclictest0-21swapper/309:54:303
1749199615,50cyclictest0-21swapper/209:09:372
1749199615,49cyclictest0-21swapper/210:02:342
1749199615,48cyclictest0-21swapper/206:54:282
1749199614,50cyclictest5568-21munin-node11:19:322
1749199614,50cyclictest0-21swapper/209:43:442
1749199614,50cyclictest0-21swapper/209:07:392
1749199614,50cyclictest0-21swapper/208:49:222
1749199614,50cyclictest0-21swapper/208:49:032
1749199614,50cyclictest0-21swapper/208:37:042
1749199614,50cyclictest0-21swapper/208:37:042
1749199614,49cyclictest0-21swapper/211:14:252
1749199614,49cyclictest0-21swapper/211:14:252
1748999615,49cyclictest0-21swapper/109:14:291
1748999615,49cyclictest0-21swapper/109:14:291
1748999615,49cyclictest0-21swapper/108:54:271
1748999615,14cyclictest0-21swapper/107:39:351
1748999614,50cyclictest0-21swapper/110:49:061
1748999613,53cyclictest0-21swapper/111:06:101
17489996115,8cyclictest26316-21swap06:29:461
17489996115,8cyclictest26316-21swap06:29:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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