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2026-01-19 - 19:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot6s.osadl.org (updated Mon Jan 19, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14299910238,57cyclictest22745-21aten_r1power_en10:04:590
1429999845,45cyclictest0-21swapper/011:35:060
142999974,26cyclictest0-21swapper/010:00:070
1429999739,50cyclictest10598-21ssh10:34:590
142999964,11cyclictest1945-21Xorg09:33:470
1429999545,44cyclictest17757-21chrt09:09:110
142999954,82cyclictest0-21swapper/009:40:140
1429999520,8cyclictest1558-21ssh08:45:060
142999936,32cyclictest0-21swapper/008:40:230
1429999345,42cyclictest0-21swapper/010:17:350
142999934,80cyclictest0-21swapper/010:30:070
142999934,36cyclictest0-21swapper/009:15:240
142999934,27cyclictest0-21swapper/010:42:490
142999934,27cyclictest0-21swapper/010:42:490
142999934,11cyclictest16486-21df_abs09:55:020
1429999339,45cyclictest15732-21crond09:54:480
142999933,83cyclictest0-21swapper/011:15:010
142999924,42cyclictest0-21swapper/012:00:140
142999924,29cyclictest0-21swapper/009:00:210
142999924,27cyclictest0-21swapper/011:40:080
142999923,21cyclictest25728-21ssh09:20:100
142999915,28cyclictest0-21swapper/011:54:290
142999914,80cyclictest0-21swapper/011:00:180
1429999135,49cyclictest0-21swapper/010:10:080
142999913,81cyclictest0-21swapper/011:28:460
142999913,81cyclictest0-21swapper/011:28:460
1429999040,7cyclictest16004-21ssh11:30:050
142999904,79cyclictest0-21swapper/009:45:000
142999904,34cyclictest0-21swapper/010:55:090
142999904,27cyclictest0-21swapper/009:25:300
1429999032,10cyclictest25770-21proc_pri08:30:190
1429999032,10cyclictest25770-21proc_pri08:30:190
1429999029,14cyclictest0-21swapper/008:50:170
1429999026,13cyclictest0-21swapper/009:10:240
1429999026,13cyclictest0-21swapper/009:10:240
142999898,13cyclictest0-21swapper/008:55:230
142999894,33cyclictest0-21swapper/006:35:180
1429998927,12cyclictest0-21swapper/010:50:490
1429998926,13cyclictest0-21swapper/007:20:290
142999884,27cyclictest0-21swapper/009:35:140
142999883,24cyclictest9242-21grep11:20:040
142999883,24cyclictest9242-21grep11:20:040
142999883,24cyclictest0-21swapper/011:55:120
1429998815,65cyclictest0-21swapper/007:45:230
1429998735,10cyclictest0-21swapper/008:37:590
1429998725,15cyclictest0-21swapper/008:28:190
248599860,4rtkit-daemon2484-21rtkit-daemon09:19:513
143299864,74cyclictest0-21swapper/211:22:462
143299864,74cyclictest0-21swapper/211:22:462
143299864,57cyclictest0-21swapper/209:23:212
1429998641,39cyclictest0-21swapper/010:25:080
142999864,33cyclictest0-21swapper/008:08:200
142999864,24cyclictest0-21swapper/007:50:210
142999864,10cyclictest0-21swapper/010:20:050
1429998618,12cyclictest0-21swapper/011:06:060
142999854,26cyclictest0-21swapper/010:45:080
142999854,24cyclictest0-21swapper/011:09:510
1429998528,11cyclictest0-21swapper/011:46:250
1429998528,10cyclictest20263-21tune2fs08:20:100
143299843,73cyclictest0-21swapper/209:18:332
1429998427,13cyclictest0-21swapper/006:54:570
142999834,15cyclictest0-21swapper/007:25:040
142999834,12cyclictest0-21swapper/007:06:230
142999834,12cyclictest0-21swapper/007:06:230
142999824,33cyclictest0-21swapper/008:15:170
143299814,69cyclictest0-21swapper/210:00:062
143299813,71cyclictest0-21swapper/211:11:202
143299813,69cyclictest0-21swapper/208:56:032
143299813,61cyclictest0-21swapper/211:50:142
143299813,60cyclictest0-21swapper/209:40:222
142999814,34cyclictest0-21swapper/007:35:050
142999814,34cyclictest0-21swapper/006:40:130
142999814,27cyclictest0-21swapper/006:50:270
1429998125,12cyclictest0-21swapper/007:30:100
143299804,59cyclictest0-21swapper/210:10:002
248599790,4rtkit-daemon2484-21rtkit-daemon10:10:121
143299794,58cyclictest0-21swapper/210:14:592
143299793,68cyclictest0-21swapper/211:42:372
143299793,68cyclictest0-21swapper/209:26:542
142999794,13cyclictest0-21swapper/008:10:100
248599780,6rtkit-daemon2484-21rtkit-daemon09:40:061
143299784,54cyclictest0-21swapper/211:15:152
143299784,50cyclictest0-21swapper/208:00:092
143299783,57cyclictest0-21swapper/209:58:022
143299778,62cyclictest26586-21diskmemload11:45:452
143299774,63cyclictest0-21swapper/209:06:242
143299774,55cyclictest0-21swapper/209:30:142
143299773,67cyclictest0-21swapper/210:57:022
143299773,67cyclictest0-21swapper/210:40:572
143299773,67cyclictest0-21swapper/210:40:572
143299773,58cyclictest0-21swapper/208:49:052
143299773,38cyclictest31273-21kworker/2:209:45:072
143299768,47cyclictest0-21swapper/208:42:292
143299764,65cyclictest0-21swapper/207:55:112
143299763,63cyclictest27576-21tr10:59:592
143299763,50cyclictest12847-21ssh09:00:172
142999764,33cyclictest0-21swapper/007:55:060
1429997624,12cyclictest0-21swapper/006:45:070
143299754,64cyclictest0-21swapper/211:38:192
143299754,64cyclictest0-21swapper/209:50:192
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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