You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-12 - 16:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot6s.osadl.org (updated Mon Jan 12, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
52499954,83cyclictest0-21swapper/108:41:411
52699934,66cyclictest0-21swapper/309:22:273
52699934,65cyclictest0-21swapper/311:51:483
526999322,48cyclictest12667-21fschecks_count09:56:413
52499914,28cyclictest0-21swapper/108:49:391
524999118,11cyclictest29446-21cpuspeed_turbos12:01:301
52699904,70cyclictest0-21swapper/310:51:213
52699904,64cyclictest0-21swapper/311:42:583
52499904,26cyclictest0-21swapper/109:38:181
52499904,24cyclictest1419-21runrttasks09:58:461
52499904,12cyclictest0-21swapper/111:59:571
52499903,18cyclictest7101-21sadc09:01:251
52699896,63cyclictest0-21swapper/311:49:373
52499894,77cyclictest0-21swapper/109:46:401
52499894,29cyclictest0-21swapper/110:30:471
52499894,11cyclictest0-21swapper/109:04:071
524998917,8cyclictest595-21ssh11:16:211
52699884,60cyclictest0-21swapper/308:41:503
52499883,25cyclictest0-21swapper/107:09:221
524998814,9cyclictest9834-21aten_r1power_fr10:41:331
52699874,61cyclictest0-21swapper/310:51:353
52499874,76cyclictest0-21swapper/109:26:541
52499874,23cyclictest18143-21diskstats11:41:341
52499873,25cyclictest1419-21runrttasks11:06:321
524998725,9cyclictest1419-21runrttasks09:36:131
52699863,76cyclictest1419-21runrttasks09:11:443
526998617,50cyclictest0-21swapper/310:56:343
526998617,50cyclictest0-21swapper/310:56:343
52499865,30cyclictest0-21swapper/111:05:251
52499864,33cyclictest0-21swapper/109:13:131
52499864,26cyclictest0-21swapper/109:52:381
52499863,26cyclictest0-21swapper/110:36:521
524998623,11cyclictest0-21swapper/111:22:281
52699856,63cyclictest0-21swapper/312:09:273
52699855,73cyclictest0-21swapper/311:14:563
52699854,23cyclictest0-21swapper/311:07:273
52699854,22cyclictest0-21swapper/310:08:583
526998521,57cyclictest26674-21gltestperf11:56:373
52499854,73cyclictest0-21swapper/109:25:361
52499854,31cyclictest0-21swapper/111:56:201
52499854,26cyclictest0-21swapper/110:16:451
52499854,23cyclictest0-21swapper/110:01:431
52499854,13cyclictest0-21swapper/110:08:401
52499854,12cyclictest0-21swapper/108:53:291
52499854,12cyclictest0-21swapper/108:53:291
524998523,10cyclictest18148-21unixbench_singl08:22:001
524998515,9cyclictest3459-21aten_r1power_vo06:46:431
524998514,12cyclictest0-21swapper/110:56:531
524998514,12cyclictest0-21swapper/110:56:531
52699844,73cyclictest0-21swapper/311:05:373
52699844,73cyclictest0-21swapper/309:07:333
52699844,22cyclictest0-21swapper/308:56:583
52499845,26cyclictest0-21swapper/111:50:021
52499844,23cyclictest1351-21netstat12:06:431
52499844,23cyclictest0-21swapper/110:26:161
52499844,22cyclictest0-21swapper/110:51:481
52499844,14cyclictest0-21swapper/111:41:191
52499844,14cyclictest0-21swapper/111:41:191
52499843,9cyclictest3449-21sendmail_mailtr09:41:541
52499843,25cyclictest0-21swapper/108:29:441
52499843,19cyclictest25723-21diskmemload09:08:231
524998426,11cyclictest17509-21ssh09:16:351
524998426,10cyclictest1160-21df_abs11:16:351
524998415,12cyclictest0-21swapper/110:49:011
524998410,13cyclictest0-21swapper/111:29:341
52699834,72cyclictest0-21swapper/311:31:313
52699834,72cyclictest0-21swapper/309:34:053
52699834,71cyclictest0-21swapper/307:36:423
52699834,57cyclictest0-21swapper/309:05:183
52699833,73cyclictest0-21swapper/309:45:113
526998319,9cyclictest1052-21rsyslogd09:48:013
526998316,51cyclictest0-21swapper/310:14:373
526998316,51cyclictest0-21swapper/310:14:373
52499834,31cyclictest0-21swapper/107:06:301
52499834,22cyclictest0-21swapper/110:31:351
52499833,8cyclictest8758-21cut06:56:481
52499833,20cyclictest2638-21runrttasks07:51:421
524998317,12cyclictest0-21swapper/107:46:501
52699825,70cyclictest0-21swapper/312:02:263
52699824,72cyclictest0-21swapper/308:55:043
52699824,72cyclictest0-21swapper/308:55:043
52699824,71cyclictest0-21swapper/311:26:303
52699824,71cyclictest0-21swapper/310:28:233
52699824,71cyclictest0-21swapper/310:03:283
52699824,56cyclictest0-21swapper/309:51:503
526998226,50cyclictest0-21swapper/311:18:313
526998217,49cyclictest0-21swapper/310:17:033
52499824,13cyclictest0-21swapper/110:11:521
52499824,13cyclictest0-21swapper/110:11:521
52499824,13cyclictest0-21swapper/108:11:271
52499823,26cyclictest0-21swapper/111:35:291
524998226,10cyclictest24434-21gltestperf08:36:451
524998220,12cyclictest0-21swapper/107:21:561
52699816,15cyclictest0-21swapper/310:21:273
52699814,70cyclictest0-21swapper/310:46:003
52699814,69cyclictest0-21swapper/308:46:383
52699814,24cyclictest0-21swapper/309:40:283
52699814,14cyclictest0-21swapper/310:36:323
526998119,55cyclictest24999-21gltestperf09:26:453
52499813,27cyclictest0-21swapper/107:31:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional