You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-20 - 21:12

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot6s.osadl.org (updated Sat Jun 20, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
115579911216,27cyclictest4078-21munin-plugin-st11:58:390
1302521100,15sleep21156399cyclictest11:23:492
1155799994,28cyclictest0-21swapper/011:43:530
1155799975,28cyclictest0-21swapper/010:33:590
1155799965,26cyclictest0-21swapper/012:11:250
1155799955,23cyclictest23170-21ssh09:14:100
1155799955,23cyclictest23170-21ssh09:14:100
1155799954,28cyclictest0-21swapper/011:58:510
1155799954,28cyclictest0-21swapper/011:58:510
1155799944,27cyclictest0-21swapper/009:59:150
1155799944,27cyclictest0-21swapper/009:09:170
1155799935,27cyclictest0-21swapper/008:09:020
1155799934,28cyclictest0-21swapper/008:59:120
1155799934,28cyclictest0-21swapper/008:19:130
1155799934,28cyclictest0-21swapper/007:59:150
1155799934,27cyclictest0-21swapper/007:24:220
1155799924,27cyclictest0-21swapper/011:39:020
1155799924,27cyclictest0-21swapper/010:12:420
1155799924,27cyclictest0-21swapper/008:29:040
1155799924,27cyclictest0-21swapper/006:54:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional