You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-05-05 - 01:07

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot6s.osadl.org (updated Sun May 04, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
208702760,6sleep220872-21grep07:50:052
61972623,52sleep20-21swapper/206:10:232
877995916,27cyclictest0-21swapper/106:40:141
880995838,15cyclictest0-21swapper/309:37:003
224822583,48sleep30-21swapper/305:39:533
876995739,11cyclictest12525-21grep05:15:280
876995720,23cyclictest23860-21munin-node06:50:210
876995720,13cyclictest0-21swapper/008:10:500
34242573,46sleep30-21swapper/304:59:543
87899565,44cyclictest0-21swapper/206:15:252
87899564,45cyclictest0-21swapper/208:35:162
876995524,13cyclictest0-21swapper/009:14:430
315952553,11sleep10-21swapper/108:10:411
227799550,6rtkit-daemon2276-21rtkit-daemon05:10:153
877995423,13cyclictest0-21swapper/106:10:111
877995420,20cyclictest21532-21uname05:35:201
87699549,27cyclictest0-21swapper/008:24:460
87699545,33cyclictest0-21swapper/008:05:060
87699545,33cyclictest0-21swapper/008:05:060
876995410,27cyclictest0-21swapper/010:14:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional