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2026-07-12 - 17:35

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot6s.osadl.org (updated Sun Jul 12, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2472999954,68cyclictest0-21swapper/308:08:223
2472999934,65cyclictest0-21swapper/311:56:483
2472999934,65cyclictest0-21swapper/309:31:283
24729999319,61cyclictest0-21swapper/309:38:173
24729999319,10cyclictest2628-21aten2.4-expect08:53:173
24729999319,10cyclictest2628-21aten2.4-expect08:53:173
2472999915,64cyclictest0-21swapper/310:23:123
2472999914,60cyclictest0-21swapper/306:53:223
2472999904,63cyclictest0-21swapper/307:25:543
2472999904,62cyclictest0-21swapper/309:21:413
2472999904,61cyclictest0-21swapper/311:07:303
24729999019,47cyclictest0-21swapper/308:29:443
24729999017,8cyclictest17198-21ssh10:03:013
24729998915,58cyclictest0-21swapper/309:01:453
24729998914,10cyclictest1227-21runrttasks10:58:233
2472999884,67cyclictest0-21swapper/310:12:533
2472999884,64cyclictest0-21swapper/311:08:173
2472999884,60cyclictest0-21swapper/309:03:103
2472999876,19cyclictest0-21swapper/309:54:103
2472999874,64cyclictest0-21swapper/311:43:193
2472999874,21cyclictest0-21swapper/310:35:313
2472999873,26cyclictest0-21swapper/311:38:193
2472999873,26cyclictest0-21swapper/311:38:193
24729998716,11cyclictest0-21swapper/310:53:333
24729998716,11cyclictest0-21swapper/310:53:333
24729998712,13cyclictest0-21swapper/309:18:003
2472999866,64cyclictest0-21swapper/310:13:163
2472999866,64cyclictest0-21swapper/310:13:163
2472999864,22cyclictest0-21swapper/310:32:233
2472999863,58cyclictest0-21swapper/310:21:013
2472999863,23cyclictest0-21swapper/311:33:303
24729998617,12cyclictest0-21swapper/309:37:153
24729998617,12cyclictest0-21swapper/309:37:153
24725998621,58cyclictest0-21swapper/008:50:080
219499860,20rtkit-daemon0-21swapper/011:37:290
2472999859,68cyclictest0-21swapper/308:38:373
2472999854,61cyclictest0-21swapper/308:03:533
2472999854,58cyclictest0-21swapper/309:09:413
2472999854,24cyclictest0-21swapper/308:35:053
2472999854,23cyclictest0-21swapper/311:24:113
2472999854,23cyclictest0-21swapper/309:45:043
2472999854,23cyclictest0-21swapper/309:27:273
2472999854,22cyclictest0-21swapper/311:28:583
2472999853,13cyclictest0-21swapper/311:22:053
24729998514,55cyclictest1761-21Xorg10:48:583
219499850,6rtkit-daemon0-21swapper/106:55:401
2472999844,71cyclictest28213-21hddtemp_smartct06:33:303
2472999844,63cyclictest0-21swapper/310:39:183
2472999844,63cyclictest0-21swapper/308:48:253
2472999844,61cyclictest0-21swapper/308:13:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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