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2026-02-06 - 21:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot6s.osadl.org (updated Fri Feb 06, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2485991080,7rtkit-daemon0-21swapper/107:29:131
22530991084,97cyclictest0-21swapper/110:08:051
225309910544,15cyclictest0-21swapper/110:59:561
22530991045,49cyclictest0-21swapper/109:33:131
22530991024,49cyclictest0-21swapper/109:43:411
22530991014,49cyclictest9352-21aten_r1power_cu10:33:031
2253099984,14cyclictest0-21swapper/111:05:031
2252399984,27cyclictest0-21swapper/010:58:210
2253299974,30cyclictest0-21swapper/210:12:012
2253099974,48cyclictest0-21swapper/108:59:501
2253099968,25cyclictest19465-21df_abs11:38:041
2253299954,31cyclictest0-21swapper/211:13:192
2253299954,29cyclictest0-21swapper/210:18:062
22532999512,27cyclictest0-21swapper/210:37:052
2253099954,46cyclictest14508-21unixbench_singl10:38:261
2253099954,28cyclictest0-21swapper/109:17:351
22523999522,8cyclictest1419-21runrttasks07:52:200
22523999522,8cyclictest1419-21runrttasks07:52:200
2252399943,84cyclictest0-21swapper/008:48:130
2253299924,31cyclictest0-21swapper/210:43:212
2253299924,29cyclictest0-21swapper/211:23:172
2253299924,29cyclictest0-21swapper/208:58:222
22532999222,14cyclictest0-21swapper/210:53:372
2253099924,49cyclictest0-21swapper/110:53:071
2253099923,48cyclictest0-21swapper/109:08:541
2253099914,38cyclictest0-21swapper/109:07:331
2253099914,38cyclictest0-21swapper/109:07:331
2253299904,30cyclictest0-21swapper/210:14:542
2253299904,30cyclictest0-21swapper/208:18:202
2253299904,28cyclictest0-21swapper/209:28:192
22532999020,14cyclictest0-21swapper/210:04:122
2252399904,78cyclictest0-21swapper/009:28:090
2252399903,80cyclictest0-21swapper/009:13:140
2253299894,30cyclictest0-21swapper/210:31:332
2253299894,30cyclictest0-21swapper/210:31:332
2253299894,29cyclictest0-21swapper/209:45:392
2253099895,14cyclictest0-21swapper/107:53:231
2252399894,79cyclictest0-21swapper/010:40:240
2252399894,79cyclictest0-21swapper/010:03:170
2252399894,77cyclictest0-21swapper/008:33:210
2252399893,79cyclictest0-21swapper/009:18:280
2252399893,11cyclictest0-21swapper/010:48:010
22523998921,14cyclictest0-21swapper/007:43:130
22523998918,12cyclictest0-21swapper/007:11:390
248599880,12rtkit-daemon2484-21rtkit-daemon11:03:503
2252399884,77cyclictest0-21swapper/009:23:090
2252399884,77cyclictest0-21swapper/008:14:050
2252399883,77cyclictest0-21swapper/008:28:020
2252399883,77cyclictest0-21swapper/008:28:020
22523998823,8cyclictest1261-21munin-node09:33:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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