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2026-04-22 - 06:41

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot6s.osadl.org (updated Wed Apr 22, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2485991120,17rtkit-daemon2484-21rtkit-daemon19:09:370
2485991120,17rtkit-daemon2484-21rtkit-daemon19:09:370
2485991020,4rtkit-daemon12893-21munin-run18:18:021
11748991014,90cyclictest0-21swapper/020:03:160
248599990,7rtkit-daemon0-21swapper/018:39:391
1174899984,85cyclictest5506-21sh22:18:210
1174899973,66cyclictest0-21swapper/021:13:140
11748999516,57cyclictest2875-21aten_r1power_po21:28:070
1174899945,53cyclictest0-21swapper/021:04:210
1174899944,81cyclictest6846-21tune2fs21:33:130
1174899943,84cyclictest0-21swapper/021:02:040
1174899943,84cyclictest0-21swapper/019:18:170
1175399934,81cyclictest0-21swapper/320:13:143
1174899934,74cyclictest0-21swapper/021:27:480
1174899934,68cyclictest0-21swapper/020:18:190
1174899934,64cyclictest0-21swapper/022:23:220
1174899934,14cyclictest0-21swapper/021:53:380
1174899934,12cyclictest0-21swapper/019:24:170
1175399924,69cyclictest0-21swapper/321:43:063
1175399924,69cyclictest0-21swapper/321:43:063
1174899924,12cyclictest0-21swapper/022:33:090
1174899924,12cyclictest0-21swapper/022:03:280
1174899924,12cyclictest0-21swapper/021:48:500
1174899924,12cyclictest0-21swapper/020:23:230
1174899924,12cyclictest0-21swapper/019:43:270
1174899924,12cyclictest0-21swapper/019:28:210
1174899924,12cyclictest0-21swapper/017:18:040
1174899914,68cyclictest0-21swapper/022:31:400
1174899914,65cyclictest0-21swapper/020:28:080
1174899914,65cyclictest0-21swapper/020:28:080
1174899914,61cyclictest0-21swapper/017:53:160
1174899914,12cyclictest0-21swapper/021:18:290
1174899914,12cyclictest0-21swapper/019:08:000
11748999114,69cyclictest0-21swapper/019:17:410
1175399906,77cyclictest0-21swapper/319:23:273
1175399904,79cyclictest0-21swapper/320:18:323
1175399904,66cyclictest0-21swapper/322:26:273
1174899904,79cyclictest0-21swapper/022:09:020
1174899904,65cyclictest0-21swapper/019:40:580
1174899904,13cyclictest0-21swapper/018:28:220
1174899904,13cyclictest0-21swapper/018:28:220
1174899904,12cyclictest0-21swapper/021:58:100
1174899904,12cyclictest0-21swapper/021:46:290
1174899904,12cyclictest0-21swapper/021:46:290
1174899904,12cyclictest0-21swapper/020:38:080
1175399894,78cyclictest0-21swapper/319:18:253
1175399894,77cyclictest0-21swapper/321:52:503
1174899894,12cyclictest0-21swapper/019:35:020
1174899893,62cyclictest32529-21cpuspeed_turbos19:48:130
11748998912,53cyclictest0-21swapper/019:58:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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