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2026-08-08 - 22:55

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot6s.osadl.org (updated Sat Aug 08, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1475321140,5sleep226-21rcuc/208:22:552
8188991034,92cyclictest0-21swapper/011:18:040
8188991023,91cyclictest32549-21cut09:38:000
8188991003,90cyclictest0-21swapper/007:33:080
818899984,87cyclictest0-21swapper/006:58:160
8188999833,7cyclictest15834-21ssh10:02:470
818899974,86cyclictest0-21swapper/009:07:400
818899963,44cyclictest0-21swapper/008:31:140
818899963,37cyclictest0-21swapper/007:48:010
818899963,37cyclictest0-21swapper/007:48:010
818899953,85cyclictest0-21swapper/010:16:590
818899944,83cyclictest0-21swapper/010:52:560
818899943,45cyclictest0-21swapper/011:32:080
818899933,44cyclictest0-21swapper/010:40:360
818899933,43cyclictest0-21swapper/009:33:490
8188999322,13cyclictest0-21swapper/008:10:020
819699924,36cyclictest0-21swapper/310:17:423
818899924,82cyclictest0-21swapper/009:27:580
818899924,24cyclictest0-21swapper/009:59:050
818899923,43cyclictest0-21swapper/008:57:530
818899923,43cyclictest0-21swapper/008:48:470
819699913,26cyclictest0-21swapper/309:48:073
819699913,26cyclictest0-21swapper/309:48:073
8196999122,13cyclictest0-21swapper/310:57:283
818899913,44cyclictest0-21swapper/009:10:070
818899913,44cyclictest0-21swapper/009:10:070
818899913,43cyclictest0-21swapper/010:49:320
818899913,11cyclictest0-21swapper/011:15:200
818899903,42cyclictest0-21swapper/011:03:180
818899903,42cyclictest0-21swapper/011:03:180
818899903,37cyclictest15860-21grep08:23:080
8188999028,8cyclictest20089-21ssh10:08:000
8196998941,42cyclictest23721-21ntp_offset10:13:063
819699894,24cyclictest0-21swapper/308:10:253
8188998926,14cyclictest0-21swapper/008:43:020
818899892,46cyclictest0-21swapper/008:20:120
819699884,29cyclictest0-21swapper/310:58:553
819699883,32cyclictest9002-21cpuspeed_turbos09:02:543
8196998821,14cyclictest0-21swapper/311:08:043
818899883,43cyclictest0-21swapper/010:46:250
818899883,39cyclictest0-21swapper/009:53:230
818899883,27cyclictest0-21swapper/007:38:000
8188998824,12cyclictest0-21swapper/010:18:110
819699876,74cyclictest0-21swapper/308:38:343
819699873,34cyclictest0-21swapper/309:14:413
8196998724,9cyclictest22675-21gltestperf09:22:593
818899873,42cyclictest0-21swapper/010:57:470
818899873,42cyclictest0-21swapper/009:23:220
818899873,38cyclictest0-21swapper/008:05:490
819699864,75cyclictest0-21swapper/310:29:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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