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2026-05-22 - 06:52

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot6s.osadl.org (updated Fri May 22, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3213921040,6sleep232143-21cpuspeed_turbos17:50:042
2972121000,4sleep041ktimersoftd/021:59:420
31816999321,51cyclictest0-21swapper/120:30:161
31816999321,51cyclictest0-21swapper/120:30:161
3181699924,13cyclictest0-21swapper/121:54:021
3181699924,13cyclictest0-21swapper/121:18:021
3181699914,68cyclictest0-21swapper/118:51:571
31816999120,50cyclictest1405-21sed19:40:191
3181699904,68cyclictest0-21swapper/120:41:081
3181699894,67cyclictest0-21swapper/121:22:551
3181699894,17cyclictest11750-21cut20:44:561
3181699894,12cyclictest0-21swapper/120:51:461
3181699894,12cyclictest0-21swapper/119:50:441
3181699894,12cyclictest0-21swapper/119:30:051
3181699894,11cyclictest0-21swapper/121:00:051
3181699884,65cyclictest0-21swapper/121:09:561
3181699884,65cyclictest0-21swapper/121:09:561
3181699884,13cyclictest0-21swapper/120:25:051
3181699884,13cyclictest0-21swapper/120:25:051
3181699884,13cyclictest0-21swapper/120:13:131
3181699884,12cyclictest0-21swapper/120:18:211
3181699884,12cyclictest0-21swapper/120:00:121
3181699884,12cyclictest0-21swapper/119:14:591
3181699883,67cyclictest0-21swapper/121:39:521
3181699877,59cyclictest0-21swapper/121:08:121
3181699874,13cyclictest0-21swapper/121:28:291
3181699874,13cyclictest0-21swapper/119:47:221
3181699874,13cyclictest0-21swapper/119:47:221
3181699874,13cyclictest0-21swapper/118:41:511
3181699874,12cyclictest0-21swapper/120:07:561
3181699873,20cyclictest0-21swapper/119:00:051
3181699865,66cyclictest0-21swapper/120:23:261
3181699864,64cyclictest0-21swapper/119:06:531
3181699864,21cyclictest27132-21df_abs21:54:571
3181699864,12cyclictest0-21swapper/118:47:061
3181699863,64cyclictest0-21swapper/117:30:091
3181699863,61cyclictest0-21swapper/119:20:031
3181699854,61cyclictest0-21swapper/121:38:591
3181699848,12cyclictest0-21swapper/119:57:251
3181699844,65cyclictest0-21swapper/121:44:541
3181699844,62cyclictest0-21swapper/121:32:121
3181699844,12cyclictest0-21swapper/119:25:271
3181699843,7cyclictest121850irq/46-eth019:38:421
31816998416,7cyclictest4126-21ssh22:09:331
3181699834,64cyclictest0-21swapper/117:14:591
3181699834,13cyclictest0-21swapper/120:34:581
3181699834,12cyclictest0-21swapper/122:00:001
3181699834,12cyclictest0-21swapper/120:56:211
3181699834,12cyclictest0-21swapper/116:40:231
3181699824,12cyclictest0-21swapper/119:12:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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