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2026-08-27 - 03:26

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot6s.osadl.org (updated Thu Aug 27, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2194991080,22rtkit-daemon201ktimersoftd/121:26:401
243779910342,22cyclictest12867-21aten_r1power_po22:05:272
243779910342,22cyclictest12867-21aten_r1power_po22:05:272
2194991000,6rtkit-daemon0-21swapper/322:37:223
2437099994,88cyclictest0-21swapper/021:31:330
219499990,5rtkit-daemon0-21swapper/318:19:103
219499980,6rtkit-daemon0-21swapper/320:46:421
219499980,6rtkit-daemon0-21swapper/320:38:273
219499980,6rtkit-daemon0-21swapper/318:12:333
219499980,6rtkit-daemon0-21swapper/317:56:113
219499980,6rtkit-daemon0-21swapper/317:45:563
219499980,5rtkit-daemon0-21swapper/320:40:273
219499980,5rtkit-daemon0-21swapper/320:40:273
219499980,5rtkit-daemon0-21swapper/318:33:321
2437099976,74cyclictest0-21swapper/020:05:000
2437099976,74cyclictest0-21swapper/020:05:000
219499970,7rtkit-daemon0-21swapper/317:51:263
219499970,7rtkit-daemon0-21swapper/317:51:263
219499970,6rtkit-daemon0-21swapper/318:31:173
219499970,6rtkit-daemon0-21swapper/318:23:173
219499970,6rtkit-daemon0-21swapper/318:03:483
219499970,5rtkit-daemon0-21swapper/320:31:273
219499970,5rtkit-daemon0-21swapper/318:29:543
219499970,5rtkit-daemon0-21swapper/318:07:033
2437099964,13cyclictest0-21swapper/020:20:490
219499960,6rtkit-daemon0-21swapper/320:45:273
2437099954,13cyclictest0-21swapper/020:44:480
2437099954,13cyclictest0-21swapper/020:44:480
2437099954,13cyclictest0-21swapper/018:05:430
219499950,5rtkit-daemon0-21swapper/322:34:003
219499950,5rtkit-daemon0-21swapper/321:26:103
2437099947,65cyclictest0-21swapper/022:32:420
2437099944,73cyclictest0-21swapper/022:25:430
219499940,6rtkit-daemon0-21swapper/322:41:073
219499940,6rtkit-daemon0-21swapper/322:41:073
2437099937,12cyclictest0-21swapper/022:39:480
2437099934,68cyclictest0-21swapper/022:09:500
2437099934,68cyclictest0-21swapper/022:09:500
2437099924,70cyclictest0-21swapper/022:00:440
2437099924,66cyclictest0-21swapper/020:36:270
24370999214,9cyclictest20581-21ssh23:05:270
219499920,5rtkit-daemon0-21swapper/320:03:433
219499920,5rtkit-daemon0-21swapper/320:03:433
2437099914,71cyclictest0-21swapper/021:30:160
2437099914,70cyclictest0-21swapper/023:14:380
2437099914,14cyclictest0-21swapper/022:46:010
2437099914,13cyclictest0-21swapper/022:10:310
24370999115,55cyclictest0-21swapper/021:06:020
2437099906,69cyclictest0-21swapper/019:45:480
2437099904,70cyclictest0-21swapper/022:40:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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