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2026-03-10 - 03:58

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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  Intel
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot6s.osadl.org (updated Tue Mar 10, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
291502980,6sleep31583199cyclictest18:13:483
1582799974,85cyclictest0-21swapper/019:03:440
15827999620,57cyclictest4498-21cstates20:28:340
1582799958,80cyclictest0-21swapper/019:59:120
1583199944,24cyclictest0-21swapper/320:40:513
15831999436,50cyclictest0-21swapper/321:19:423
1582799944,83cyclictest0-21swapper/021:32:150
15831999337,49cyclictest21348-21unixbench_singl19:04:023
1582799934,81cyclictest0-21swapper/021:33:290
1582799934,81cyclictest0-21swapper/021:33:290
1582799934,54cyclictest0-21swapper/019:53:220
248599920,18rtkit-daemon0-21swapper/020:59:283
1582799924,80cyclictest0-21swapper/020:33:380
1582799924,69cyclictest0-21swapper/020:24:430
1582799924,55cyclictest0-21swapper/023:03:420
1582799924,50cyclictest0-21swapper/021:23:390
1583199915,22cyclictest0-21swapper/321:08:523
1583199914,39cyclictest29854-21ssh21:53:353
1583199913,9cyclictest121850irq/46-eth022:03:073
1582799915,68cyclictest0-21swapper/023:08:430
1582799914,80cyclictest0-21swapper/022:14:070
1582799914,80cyclictest0-21swapper/022:14:070
1582799914,80cyclictest0-21swapper/020:58:400
1582799905,78cyclictest0-21swapper/020:53:410
1582799905,78cyclictest0-21swapper/020:53:410
1582799904,79cyclictest0-21swapper/021:48:330
1582799904,54cyclictest0-21swapper/020:08:320
1582799904,45cyclictest0-21swapper/022:23:440
248599890,17rtkit-daemon0-21swapper/022:06:333
248599890,17rtkit-daemon0-21swapper/021:35:343
248599890,17rtkit-daemon0-21swapper/021:35:343
1583199894,23cyclictest0-21swapper/320:12:263
1583199894,12cyclictest0-21swapper/320:19:183
15831998930,10cyclictest24025-21gltestperf18:03:443
15831998928,9cyclictest17907-21cut20:48:333
1582799894,77cyclictest0-21swapper/021:13:310
1582799894,64cyclictest0-21swapper/021:38:360
1582799893,80cyclictest0-21swapper/022:53:290
1582799893,80cyclictest0-21swapper/022:53:290
1582799893,79cyclictest0-21swapper/022:43:410
1582799893,78cyclictest0-21swapper/018:58:390
15827998913,53cyclictest28532-21ssh22:38:460
1583199884,26cyclictest0-21swapper/323:15:483
1583199884,24cyclictest0-21swapper/321:50:343
15831998811,14cyclictest0-21swapper/321:03:443
1582799884,77cyclictest0-21swapper/022:33:330
1582799884,77cyclictest0-21swapper/021:44:270
1582799884,77cyclictest0-21swapper/021:08:370
1582799884,77cyclictest0-21swapper/020:03:530
1582799884,76cyclictest0-21swapper/022:48:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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