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2026-02-15 - 13:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot8.osadl.org (updated Sun Feb 15, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20336999372,906cyclictest20524-21telnet19:10:160
2033799800733,51cyclictest0-21swapper/119:10:161
194222645614,21sleep00-21swapper/019:05:210
20337995414,11cyclictest0-21swapper/119:47:211
2033699475387,79cyclictest0-21swapper/019:47:220
200832451432,13sleep10-21swapper/119:07:481
3165421060,3sleep131656-21netstat19:40:211
203379910316,42cyclictest0-21swapper/121:56:591
203369910314,73cyclictest0-21swapper/022:27:580
203379910016,39cyclictest0-21swapper/120:15:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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