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2026-01-15 - 08:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot8.osadl.org (updated Thu Jan 15, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
279099821732,79cyclictest0-21swapper/019:17:000
25302814796,12sleep10-21swapper/119:07:441
279099487411,50cyclictest0-21swapper/019:10:010
25232482460,15sleep00-21swapper/019:07:390
279199422344,46cyclictest0-21swapper/119:10:021
2790999459,29cyclictest0-21swapper/000:33:580
228699920,3rtkit-daemon2712-21kworker/0:223:54:181
159522870,4sleep115953-21sh21:13:191
2791998415,48cyclictest0-21swapper/100:25:581
279199819,56cyclictest0-21swapper/119:38:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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