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2026-01-22 - 09:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot8.osadl.org (updated Thu Jan 22, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
259679917651689,39cyclictest26772-21strings19:10:200
258332823801,16sleep10-21swapper/119:09:011
257002676653,16sleep00-21swapper/019:07:430
25968995375,13cyclictest0-21swapper/119:10:201
228699970,12rtkit-daemon0-21swapper/021:24:310
2596799762,58cyclictest25107-21latency_hist22:45:010
2596799743,65cyclictest28555-21ssh21:50:350
2596799733,45cyclictest14868-21ssh23:24:580
2596799724,41cyclictest5992-21munin-node22:10:150
2596799723,45cyclictest17781-21ssh22:30:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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