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2026-02-25 - 18:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot8.osadl.org (updated Wed Feb 25, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
845799889814,50cyclictest0-21swapper/007:11:060
81662801779,15sleep10-21swapper/107:07:301
845899797724,46cyclictest0-21swapper/107:11:071
8458994724,451cyclictest0-21swapper/108:02:571
845799384333,44cyclictest0-21swapper/008:02:560
84589911912,101cyclictest0-21swapper/111:58:001
84579911814,98cyclictest0-21swapper/012:33:580
8457999711,79cyclictest0-21swapper/011:10:580
192592910,3sleep119300-21date07:40:011
8457998630,49cyclictest0-21swapper/011:49:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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