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2026-07-14 - 17:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot8.osadl.org (updated Tue Jul 14, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
130162715689,16sleep00-21swapper/007:05:580
130172631611,13sleep10-21swapper/107:06:001
1345499481424,26cyclictest13621-21aten_r1power_cu07:10:111
1345399441372,57cyclictest15-21rcuop/107:10:110
1345499370339,17cyclictest12645-21strings08:35:191
2286991010,3rtkit-daemon2285-21rtkit-daemon11:00:330
228699960,4rtkit-daemon2285-21rtkit-daemon07:41:211
228699950,4rtkit-daemon2285-21rtkit-daemon09:33:331
228699940,5rtkit-daemon2285-21rtkit-daemon12:27:111
228699930,4rtkit-daemon2285-21rtkit-daemon11:27:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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