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2026-02-27 - 19:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot8.osadl.org (updated Fri Feb 27, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
543199893831,51cyclictest0-21swapper/008:05:200
543299412342,39cyclictest0-21swapper/107:11:041
543199378310,46cyclictest0-21swapper/007:11:050
51712333312,15sleep10-21swapper/107:07:441
49672307283,17sleep00-21swapper/007:05:400
990621210,3sleep19907-21sh11:51:091
543199995,75cyclictest0-21swapper/007:45:010
543199875,62cyclictest0-21swapper/008:24:000
543199835,62cyclictest0-21swapper/008:41:000
543199807,58cyclictest0-21swapper/012:30:000
543299786,17cyclictest0-21swapper/109:36:551
5432997811,22cyclictest0-21swapper/108:03:331
543299776,30cyclictest0-21swapper/109:59:351
543299769,23cyclictest0-21swapper/111:05:111
543299765,18cyclictest0-21swapper/111:12:261
543299765,14cyclictest0-21swapper/110:19:491
543299759,19cyclictest0-21swapper/107:20:011
543299758,18cyclictest0-21swapper/111:40:151
543299757,28cyclictest0-21swapper/110:51:461
543299757,20cyclictest0-21swapper/107:46:061
543299756,20cyclictest0-21swapper/112:21:571
543299756,17cyclictest0-21swapper/111:25:161
543299756,17cyclictest0-21swapper/110:32:221
543299747,28cyclictest0-21swapper/109:25:151
543299747,20cyclictest0-21swapper/110:40:011
5432997411,18cyclictest0-21swapper/109:40:111
543299739,18cyclictest0-21swapper/110:24:381
543299738,20cyclictest0-21swapper/111:55:171
543299738,20cyclictest0-21swapper/109:45:141
543299738,18cyclictest0-21swapper/110:40:131
543299737,19cyclictest0-21swapper/112:10:181
543299737,19cyclictest0-21swapper/110:10:111
543299737,18cyclictest0-21swapper/111:34:511
543299736,28cyclictest0-21swapper/112:40:001
543299736,25cyclictest0-21swapper/110:00:111
543299736,20cyclictest0-21swapper/107:35:161
543299736,19cyclictest0-21swapper/109:05:141
543299736,18cyclictest0-21swapper/111:47:151
5432997317,16cyclictest0-21swapper/112:09:471
5432997316,8cyclictest14920-21sensors_temp12:00:231
5432997315,15cyclictest0-21swapper/110:05:171
5432997310,19cyclictest0-21swapper/109:50:101
5432997310,19cyclictest0-21swapper/109:50:101
5432997310,19cyclictest0-21swapper/107:50:181
5432997310,18cyclictest0-21swapper/111:02:371
543299729,18cyclictest0-21swapper/111:35:111
543299728,18cyclictest0-21swapper/110:27:561
543299727,22cyclictest0-21swapper/110:55:281
543299727,21cyclictest0-21swapper/112:25:181
543299727,21cyclictest0-21swapper/112:15:141
543299727,19cyclictest0-21swapper/110:46:141
543299727,19cyclictest0-21swapper/107:40:171
543299727,18cyclictest0-21swapper/112:30:231
543299727,17cyclictest0-21swapper/107:21:141
543299726,28cyclictest0-21swapper/111:20:341
543299726,25cyclictest0-21swapper/111:15:061
543299726,19cyclictest0-21swapper/107:55:131
543299726,17cyclictest0-21swapper/109:00:451
543299725,29cyclictest0-21swapper/109:15:441
543299725,27cyclictest0-21swapper/109:22:031
5432997213,18cyclictest0-21swapper/109:30:171
543199726,53cyclictest0-21swapper/007:47:000
228699720,3rtkit-daemon2285-21rtkit-daemon08:53:581
543299717,18cyclictest0-21swapper/108:31:071
543299716,28cyclictest0-21swapper/108:55:191
543299716,19cyclictest0-21swapper/108:35:191
543299716,19cyclictest0-21swapper/108:25:211
543299716,19cyclictest0-21swapper/107:27:431
543299715,27cyclictest0-21swapper/108:45:011
5432997114,13cyclictest0-21swapper/108:48:331
5432997112,13cyclictest0-21swapper/109:15:011
5432997110,23cyclictest0-21swapper/108:10:031
543299707,17cyclictest0-21swapper/108:05:141
543299706,18cyclictest0-21swapper/108:15:171
543199702,53cyclictest12159-21latency_hist10:00:010
543199702,37cyclictest32350-21ssh11:35:000
543199696,44cyclictest0-21swapper/009:40:270
5431996943,16cyclictest0-21swapper/011:17:250
5431996942,17cyclictest0-21swapper/010:30:150
543199693,58cyclictest19189-21idleruntime-cro09:15:010
99502680,13sleep0543199cyclictest11:51:180
543299686,19cyclictest0-21swapper/108:20:141
5432996815,14cyclictest0-21swapper/107:30:121
543199685,56cyclictest0-21swapper/012:15:260
5431996844,18cyclictest0-21swapper/011:36:090
543199674,57cyclictest0-21swapper/010:45:040
5431996739,22cyclictest0-21swapper/010:52:420
543199673,57cyclictest19999-21munin-node07:50:160
5431996713,33cyclictest0-21swapper/009:55:020
5431996713,33cyclictest0-21swapper/009:55:010
5431996644,16cyclictest0-21swapper/009:46:380
5431996643,17cyclictest0-21swapper/010:14:510
543199662,58cyclictest26728-21ssh12:21:570
543199662,57cyclictest14479-21latency_hist07:35:020
543199662,51cyclictest18655-21ssh12:07:420
543199662,42cyclictest14588-21munin-node07:35:260
543199652,57cyclictest32608-21switchtime10:35:250
543199652,56cyclictest26938-21munin-node11:25:140
5431996442,17cyclictest0-21swapper/009:15:010
5431996442,16cyclictest0-21swapper/007:25:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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