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2026-01-28 - 20:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Wed Jan 28, 2026 12:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
258482966947,12sleep10-21swapper/107:05:491
260472603580,16sleep00-21swapper/007:07:480
2631199495425,47cyclictest0-21swapper/107:10:071
2631099490408,76cyclictest0-21swapper/007:28:400
2631199400332,35cyclictest0-21swapper/107:28:401
2631099371304,50cyclictest0-21swapper/007:10:070
263119910012,66cyclictest0-21swapper/108:36:591
263119910012,66cyclictest0-21swapper/108:36:591
228699960,3rtkit-daemon2285-21rtkit-daemon10:23:320
2631199959,62cyclictest0-21swapper/109:20:591
26311999529,46cyclictest0-21swapper/110:05:581
26311998816,52cyclictest0-21swapper/112:39:581
26310998118,56cyclictest0-21swapper/008:44:590
26310998118,56cyclictest0-21swapper/008:44:590
228699800,5rtkit-daemon2285-21rtkit-daemon09:30:261
26310997923,48cyclictest0-21swapper/011:32:590
26311997817,40cyclictest0-21swapper/109:04:591
26311997815,41cyclictest0-21swapper/107:42:591
228699780,5rtkit-daemon2285-21rtkit-daemon12:05:581
26311997616,39cyclictest0-21swapper/107:46:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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