You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-26 - 01:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Thu Feb 26, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
182199847780,59cyclictest0-21swapper/020:05:200
182299816762,28cyclictest0-21swapper/120:05:191
16352766745,15sleep10-21swapper/119:08:341
1821995522,6cyclictest23102sleep019:10:140
182299514436,45cyclictest0-21swapper/119:10:151
15712505481,16sleep00-21swapper/019:07:510
1326721520,11sleep1182299cyclictest19:40:151
2036121030,4sleep020363-21munin-plugin-st23:20:010
228699870,3rtkit-daemon2285-21rtkit-daemon23:15:101
1821998328,49cyclictest88850irq/46-eth0-tx-21:32:250
182199733,44cyclictest2160-21ssh21:47:340
182199733,44cyclictest12868-21diskmemload23:46:480
182199732,64cyclictest23753-21ssh22:25:370
182199725,51cyclictest0-21swapper/019:24:400
182199723,53cyclictest21694-21latency_hist20:05:010
182199723,49cyclictest13123-21ssh00:05:070
182199723,43cyclictest30069-21ssh22:38:200
182199722,64cyclictest30204-21ssh23:35:560
182199722,45cyclictest15359-21ssh21:14:190
182199722,44cyclictest29262-21ssh21:38:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional