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2026-03-03 - 17:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Tue Mar 03, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
215559919754,13cyclictest0-21swapper/007:10:140
2155699895831,26cyclictest0-21swapper/107:43:491
213492520501,13sleep10-21swapper/107:08:201
2155699478432,32cyclictest0-21swapper/107:10:141
210892158135,15sleep00-21swapper/007:05:450
2286991030,10rtkit-daemon0-21swapper/008:21:140
228699960,10rtkit-daemon0-21swapper/008:49:090
228699940,10rtkit-daemon0-21swapper/008:28:540
228699940,10rtkit-daemon0-21swapper/007:45:590
228699930,10rtkit-daemon0-21swapper/009:06:490
228699930,10rtkit-daemon0-21swapper/007:53:440
2155699865,58cyclictest0-21swapper/107:35:001
2155599867,19cyclictest0-21swapper/009:55:200
2155599859,70cyclictest27560-21timerandwakeup10:55:240
2155599838,21cyclictest0-21swapper/011:30:240
2155599837,18cyclictest0-21swapper/012:08:440
2155599835,15cyclictest0-21swapper/010:28:040
2155599825,19cyclictest0-21swapper/010:52:190
2155599824,20cyclictest30538-21ssh11:00:280
2155599817,17cyclictest0-21swapper/011:47:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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