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2026-01-27 - 20:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Tue Jan 27, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1208521020998,15sleep10-21swapper/107:08:111
1229899903825,54cyclictest0-21swapper/107:41:191
1229799813737,51cyclictest0-21swapper/007:41:190
119642495472,16sleep00-21swapper/007:07:020
1229899468398,49cyclictest0-21swapper/107:10:091
1229799384312,53cyclictest0-21swapper/007:10:090
12297999960,24cyclictest0-21swapper/009:51:590
12297999675,15cyclictest0-21swapper/012:38:580
1229799956,17cyclictest0-21swapper/011:50:010
228699890,7rtkit-daemon0-21swapper/010:31:340
12297998815,67cyclictest0-21swapper/011:25:580
1229799879,60cyclictest0-21swapper/008:23:000
1229799877,17cyclictest0-21swapper/008:15:150
1229799866,73cyclictest0-21swapper/012:15:110
228699850,4rtkit-daemon2285-21rtkit-daemon09:00:180
12298998313,50cyclictest0-21swapper/109:59:581
1229799827,22cyclictest0-21swapper/012:30:000
228699810,3rtkit-daemon15476-21ssh09:52:341
1229799816,19cyclictest0-21swapper/008:35:220
228699800,4rtkit-daemon7666-21ssh10:36:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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