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2026-01-24 - 18:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sat Jan 24, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2518799933849,54cyclictest0-21swapper/007:11:190
2518899801719,49cyclictest0-21swapper/107:11:181
249122574554,13sleep10-21swapper/107:07:341
2518799485419,55cyclictest0-21swapper/009:35:170
2518899350287,28cyclictest0-21swapper/109:35:171
2286991020,4rtkit-daemon2285-21rtkit-daemon09:56:091
25070210077,15sleep00-21swapper/007:09:070
2286991000,4rtkit-daemon2285-21rtkit-daemon09:20:081
228699970,4rtkit-daemon2285-21rtkit-daemon09:46:491
25187999613,76cyclictest0-21swapper/010:36:000
228699950,4rtkit-daemon2285-21rtkit-daemon12:24:511
228699950,4rtkit-daemon2285-21rtkit-daemon08:09:331
228699940,4rtkit-daemon2285-21rtkit-daemon10:22:041
228699930,4rtkit-daemon2285-21rtkit-daemon10:12:191
25187999114,57cyclictest0-21swapper/007:31:590
228699910,5rtkit-daemon2285-21rtkit-daemon08:40:321
228699910,4rtkit-daemon2285-21rtkit-daemon12:02:001
228699900,4rtkit-daemon2285-21rtkit-daemon08:37:481
228699890,4rtkit-daemon2285-21rtkit-daemon11:56:261
228699890,4rtkit-daemon2285-21rtkit-daemon10:27:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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