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2026-01-15 - 21:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Thu Jan 15, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
260079918531771,75cyclictest0-21swapper/007:45:210
257142939921,12sleep10-21swapper/107:07:281
258872641619,16sleep00-21swapper/007:09:100
26007995475,520cyclictest0-21swapper/007:10:190
2600899440357,38cyclictest26814-21strings07:10:191
2600899334277,15cyclictest7139-21strings07:45:211
2286991130,4rtkit-daemon2285-21rtkit-daemon07:16:461
2286991110,3rtkit-daemon2285-21rtkit-daemon08:45:531
2286991100,4rtkit-daemon2285-21rtkit-daemon11:15:401
2286991090,4rtkit-daemon2285-21rtkit-daemon09:41:481
2286991090,4rtkit-daemon2285-21rtkit-daemon07:44:061
2286991070,4rtkit-daemon2285-21rtkit-daemon12:29:251
2286991070,4rtkit-daemon2285-21rtkit-daemon12:18:501
2286991070,4rtkit-daemon2285-21rtkit-daemon08:20:511
2286991070,4rtkit-daemon2285-21rtkit-daemon07:52:411
2286991070,3rtkit-daemon2285-21rtkit-daemon09:03:171
2286991070,3rtkit-daemon2285-21rtkit-daemon08:14:561
2286991060,4rtkit-daemon2285-21rtkit-daemon11:30:341
2286991060,4rtkit-daemon2285-21rtkit-daemon08:58:581
2286991050,4rtkit-daemon2285-21rtkit-daemon07:28:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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