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2026-01-23 - 04:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Fri Jan 23, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1126499884762,92cyclictest0-21swapper/019:10:190
1126499858762,63cyclictest0-21swapper/019:35:120
1126599801674,25cyclictest12069-21strings19:10:191
1126599787690,65cyclictest0-21swapper/119:35:121
110522464441,16sleep00-21swapper/019:08:150
11265999012,59cyclictest0-21swapper/122:56:591
228699840,8rtkit-daemon2285-21rtkit-daemon23:36:311
11265998213,55cyclictest0-21swapper/120:01:591
228699810,4rtkit-daemon2285-21rtkit-daemon00:35:170
11265998019,38cyclictest0-21swapper/121:10:001
11265998018,42cyclictest0-21swapper/119:21:591
228699790,12rtkit-daemon0-21swapper/019:20:120
11265997934,28cyclictest0-21swapper/123:59:591
11265997920,37cyclictest0-21swapper/100:12:591
11265997916,43cyclictest0-21swapper/120:41:001
228699780,5rtkit-daemon2285-21rtkit-daemon21:20:191
11265997817,40cyclictest0-21swapper/120:50:591
11264997815,55cyclictest0-21swapper/021:21:590
274982770,4sleep027499-21ssh00:15:010
228699770,4rtkit-daemon2285-21rtkit-daemon22:02:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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