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2026-01-26 - 06:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Mon Jan 26, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
106509918161745,43cyclictest0-21swapper/019:11:310
1065099848770,52cyclictest0-21swapper/019:47:510
1065199796716,48cyclictest0-21swapper/119:47:511
103392676653,16sleep00-21swapper/019:07:150
1065199358290,39cyclictest0-21swapper/119:11:311
2286991290,44rtkit-daemon23524-21ssh21:12:071
106519912615,65cyclictest0-21swapper/123:10:591
2286991200,4rtkit-daemon2285-21rtkit-daemon20:39:161
2889421160,4sleep028893-21aten_r1power_fr20:00:110
2286991110,4rtkit-daemon2285-21rtkit-daemon23:18:541
10651999612,61cyclictest0-21swapper/123:24:591
10651999014,61cyclictest0-21swapper/121:22:591
228699840,3rtkit-daemon18939-21open_files21:00:220
1065199815,59cyclictest0-21swapper/122:41:001
228699780,5rtkit-daemon2285-21rtkit-daemon23:06:390
10651997819,35cyclictest0-21swapper/121:35:001
228699770,4rtkit-daemon2285-21rtkit-daemon21:58:280
228699760,4rtkit-daemon2285-21rtkit-daemon23:55:201
228699760,4rtkit-daemon2285-21rtkit-daemon21:52:181
228699760,4rtkit-daemon2285-21rtkit-daemon19:59:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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