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2026-01-24 - 06:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sat Jan 24, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
54909917881729,48cyclictest0-21swapper/019:10:030
433221018989,13sleep10-21swapper/119:05:161
549199396334,46cyclictest0-21swapper/119:10:031
549199393324,48cyclictest0-21swapper/119:43:441
549099383315,54cyclictest0-21swapper/019:43:440
5331211087,16sleep00-21swapper/019:08:450
291612890,4sleep029159-21head22:30:130
291612890,4sleep029159-21head22:30:120
205992790,2sleep0221rcuc/023:12:190
5490997445,22cyclictest0-21swapper/020:09:230
5490997445,22cyclictest0-21swapper/020:09:220
5490997245,21cyclictest0-21swapper/023:04:450
5490997145,20cyclictest0-21swapper/023:35:160
137212710,4sleep113724-21sendmail_mailqu19:30:221
5490997051,13cyclictest0-21swapper/000:15:460
5490996948,16cyclictest0-21swapper/020:20:210
5490996945,17cyclictest0-21swapper/022:12:090
5490996844,19cyclictest0-21swapper/019:25:250
5490996743,19cyclictest0-21swapper/021:35:320
5490996645,16cyclictest0-21swapper/023:50:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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