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2026-01-17 - 10:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sat Jan 17, 2026 00:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3159899915807,75cyclictest20129-21processes20:05:291
3159799907838,61cyclictest0-21swapper/019:11:200
3159799881774,77cyclictest0-21swapper/020:05:290
3159899762691,58cyclictest0-21swapper/119:11:201
31273273723,705sleep00-21swapper/019:07:060
312652122101,14sleep10-21swapper/119:07:011
228699940,4rtkit-daemon0-21swapper/023:36:100
31598999013,44cyclictest0-21swapper/120:38:591
228699880,4rtkit-daemon2285-21rtkit-daemon21:01:470
3159799879,66cyclictest0-21swapper/022:40:590
228699870,13rtkit-daemon0-21swapper/122:53:141
228699870,11rtkit-daemon0-21swapper/121:56:281
31598998614,43cyclictest0-21swapper/121:43:591
228699860,8rtkit-daemon0-21swapper/119:47:261
228699820,4rtkit-daemon2285-21rtkit-daemon21:36:321
228699810,4rtkit-daemon2285-21rtkit-daemon23:56:450
228699810,11rtkit-daemon0-21swapper/122:13:041
31597998010,53cyclictest0-21swapper/020:27:590
228699800,3rtkit-daemon2285-21rtkit-daemon00:00:200
228699800,11rtkit-daemon0-21swapper/120:48:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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