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2026-01-12 - 23:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Mon Jan 12, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1489999877794,51cyclictest0-21swapper/107:28:451
1489999877794,51cyclictest0-21swapper/107:28:441
1489899838756,54cyclictest0-21swapper/007:28:450
1489899838756,54cyclictest0-21swapper/007:28:440
132132663642,15sleep10-21swapper/107:05:081
1489999439359,47cyclictest0-21swapper/107:10:361
1489899400322,52cyclictest0-21swapper/007:10:360
145112268243,18sleep00-21swapper/007:06:330
2286991000,4rtkit-daemon2285-21rtkit-daemon09:15:170
228699930,10rtkit-daemon0-21swapper/108:05:161
1489899846,58cyclictest0-21swapper/012:34:590
1489899829,57cyclictest0-21swapper/007:22:010
1489899829,57cyclictest0-21swapper/007:22:000
252192800,3sleep1271ktimersoftd/112:03:241
228699770,5rtkit-daemon2285-21rtkit-daemon08:23:300
228699720,10rtkit-daemon0-21swapper/011:26:000
228699720,10rtkit-daemon0-21swapper/011:25:590
269972710,3sleep1271ktimersoftd/109:10:241
228699710,10rtkit-daemon0-21swapper/109:20:110
1489999715,58cyclictest0-21swapper/110:09:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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