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2026-02-25 - 01:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Tue Feb 24, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
285112847827,13sleep10-21swapper/107:07:561
284072488467,15sleep00-21swapper/007:06:520
2875699468391,71cyclictest0-21swapper/007:10:500
2875799443380,47cyclictest0-21swapper/108:31:261
2875699389325,49cyclictest0-21swapper/008:31:250
2875699126104,15cyclictest0-21swapper/008:49:590
287569910284,13cyclictest0-21swapper/011:41:580
287569910014,70cyclictest0-21swapper/009:02:000
28757999116,46cyclictest0-21swapper/109:18:001
228699910,48rtkit-daemon2285-21rtkit-daemon12:20:251
228699900,4rtkit-daemon2285-21rtkit-daemon10:35:020
7262850,4sleep0725-21netstat07:20:190
28756998512,59cyclictest0-21swapper/011:29:590
228699850,10rtkit-daemon0-21swapper/109:50:331
228699840,12rtkit-daemon0-21swapper/111:46:431
228699840,12rtkit-daemon0-21swapper/110:36:171
28757998316,38cyclictest0-21swapper/108:04:011
28756998312,58cyclictest0-21swapper/012:13:590
228699830,13rtkit-daemon0-21swapper/108:41:571
228699830,12rtkit-daemon0-21swapper/111:58:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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