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2026-05-31 - 00:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sat May 30, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7201999414,857cyclictest0-21swapper/007:22:590
720299889840,24cyclictest0-21swapper/107:22:591
720199883806,40cyclictest7297-21latency_hist07:10:010
720299823779,29cyclictest0-21swapper/107:10:011
1305321610,15sleep1720299cyclictest08:55:121
228699980,5rtkit-daemon2285-21rtkit-daemon09:00:241
720299855,63cyclictest0-21swapper/112:15:581
720299835,58cyclictest0-21swapper/109:22:581
720199805,17cyclictest0-21swapper/012:33:230
7201998031,41cyclictest88850irq/46-eth0-tx-10:15:150
7201998031,41cyclictest88850irq/46-eth0-tx-10:15:140
720199793,18cyclictest8822-21ps11:45:210
720199786,17cyclictest0-21swapper/010:50:010
720199776,16cyclictest0-21swapper/010:43:350
7201997630,38cyclictest88850irq/46-eth0-tx-10:50:150
720199763,20cyclictest30162-21df_inode09:30:160
7201997611,50cyclictest3990-21ssh09:40:230
272422760,4sleep127241-21sed09:25:151
720199756,62cyclictest0-21swapper/011:05:280
720199756,16cyclictest0-21swapper/011:35:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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