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2026-03-12 - 20:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Thu Mar 12, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
209552975954,15sleep10-21swapper/107:06:261
2134099871797,38cyclictest2481-21strings07:45:190
2134199786743,28cyclictest0-21swapper/107:45:191
2134099459379,54cyclictest0-21swapper/007:10:170
196572434412,15sleep00-21swapper/007:05:090
2134199402321,48cyclictest0-21swapper/107:10:181
2286991280,3rtkit-daemon2285-21rtkit-daemon08:32:380
1111621010,4sleep111115-21iostat11:25:171
112492950,5sleep111250-21sh10:26:361
228699920,9rtkit-daemon0-21swapper/110:41:070
21341999212,65cyclictest0-21swapper/108:53:591
2134099895,26cyclictest0-21swapper/011:00:330
21341998814,56cyclictest0-21swapper/111:02:591
2134099886,29cyclictest0-21swapper/009:25:300
2134099876,32cyclictest0-21swapper/011:15:100
228699860,6rtkit-daemon2285-21rtkit-daemon10:35:211
228699860,6rtkit-daemon2285-21rtkit-daemon10:35:211
2134099866,25cyclictest0-21swapper/009:41:090
2134099866,25cyclictest0-21swapper/009:41:080
21340998565,16cyclictest0-21swapper/011:06:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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