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2026-03-02 - 17:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Mon Mar 02, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1313499897813,50cyclictest10944-21grep08:30:260
1313499875796,52cyclictest0-21swapper/007:11:180
1313599792710,50cyclictest0-21swapper/107:11:191
1313599781718,46cyclictest10945-21unixbench_multi08:30:271
126552703679,16sleep10-21swapper/107:05:311
129892450428,15sleep00-21swapper/007:08:530
131359910315,67cyclictest0-21swapper/109:16:001
13135999415,58cyclictest0-21swapper/108:12:011
1313499917,73cyclictest0-21swapper/012:05:590
13134998815,29cyclictest0-21swapper/010:36:000
1313499866,74cyclictest0-21swapper/008:59:590
228699840,4rtkit-daemon2285-21rtkit-daemon10:04:480
228699830,5rtkit-daemon2285-21rtkit-daemon12:24:261
228699830,5rtkit-daemon2285-21rtkit-daemon12:24:261
13134998314,28cyclictest0-21swapper/011:33:000
228699820,4rtkit-daemon2285-21rtkit-daemon10:40:141
13134998211,58cyclictest0-21swapper/007:26:590
13134998030,36cyclictest0-21swapper/008:50:590
228699790,4rtkit-daemon2285-21rtkit-daemon11:17:301
13135997920,35cyclictest0-21swapper/112:18:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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