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2026-06-29 - 19:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Mon Jun 29, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
159899768707,27cyclictest0-21swapper/107:10:051
159799761685,70cyclictest0-21swapper/007:10:060
159799358311,42cyclictest19654-21latency_hist08:00:010
159899343299,14cyclictest19786-21latency_hist08:00:011
13212330311,13sleep10-21swapper/107:07:471
12632278256,15sleep00-21swapper/007:07:170
1597991195,15cyclictest0-21swapper/012:25:590
23062910,4sleep02305-21aten_r1power_cu11:45:120
200642700,7sleep0159799cyclictest12:15:260
1597996320,28cyclictest0-21swapper/010:16:330
228699620,5rtkit-daemon2285-21rtkit-daemon11:55:430
1597996127,27cyclictest0-21swapper/011:06:070
1597996118,37cyclictest0-21swapper/010:54:350
228699600,5rtkit-daemon2285-21rtkit-daemon12:11:240
228699600,5rtkit-daemon2285-21rtkit-daemon09:35:350
1597996032,22cyclictest0-21swapper/011:24:050
1597996019,36cyclictest0-21swapper/011:38:240
1597995939,15cyclictest0-21swapper/008:17:090
1597995921,10cyclictest30162-21ssh09:40:150
1597995920,8cyclictest22011-21df12:20:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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