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2026-01-27 - 07:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Tue Jan 27, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2621899859771,50cyclictest88750irq/45-eth0-rx-21:10:191
2621799847752,84cyclictest4911-21diskmemload21:10:200
2621899534435,26cyclictest0-21swapper/119:10:571
2621799510409,17cyclictest1189-21snmpd19:10:580
260342457437,13sleep10-21swapper/119:08:291
26217991334,29cyclictest0-21swapper/023:18:580
26217991205,109cyclictest0-21swapper/019:18:000
26217991086,96cyclictest0-21swapper/022:48:580
26217991066,94cyclictest0-21swapper/000:16:580
26217991025,73cyclictest0-21swapper/019:24:000
26217991004,65cyclictest0-21swapper/022:52:590
26217999816,39cyclictest0-21swapper/000:13:590
228699950,8rtkit-daemon0-21swapper/023:48:190
2621799926,27cyclictest0-21swapper/022:16:580
228699840,44rtkit-daemon2285-21rtkit-daemon19:56:380
228699830,35rtkit-daemon2285-21rtkit-daemon19:48:330
228699810,4rtkit-daemon2285-21rtkit-daemon20:38:040
228699810,35rtkit-daemon2285-21rtkit-daemon21:26:250
228699770,4rtkit-daemon2285-21rtkit-daemon22:01:010
228699770,3rtkit-daemon2285-21rtkit-daemon00:29:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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