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2026-03-01 - 03:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sun Mar 01, 2026 00:44:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1153821006985,14sleep10-21swapper/119:06:441
116602926904,16sleep00-21swapper/019:07:590
1189899856779,53cyclictest0-21swapper/019:10:190
1189999788710,48cyclictest0-21swapper/119:10:191
1189999476415,29cyclictest0-21swapper/119:55:071
1189899360284,70cyclictest0-21swapper/019:55:080
2286991350,4rtkit-daemon2285-21rtkit-daemon21:36:510
2286991280,4rtkit-daemon2285-21rtkit-daemon23:39:030
2286991100,4rtkit-daemon2285-21rtkit-daemon23:40:131
2286991100,4rtkit-daemon2285-21rtkit-daemon23:29:381
2286991090,4rtkit-daemon2285-21rtkit-daemon23:09:231
2286991090,4rtkit-daemon2285-21rtkit-daemon22:56:121
2286991090,4rtkit-daemon2285-21rtkit-daemon22:26:171
2286991080,5rtkit-daemon2285-21rtkit-daemon21:54:161
2286991080,4rtkit-daemon2285-21rtkit-daemon22:38:121
2286991080,4rtkit-daemon2285-21rtkit-daemon22:11:311
2286991080,4rtkit-daemon2285-21rtkit-daemon19:27:131
2286991070,4rtkit-daemon2285-21rtkit-daemon22:40:021
2286991070,4rtkit-daemon2285-21rtkit-daemon21:18:001
2286991070,4rtkit-daemon2285-21rtkit-daemon21:06:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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