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2026-01-20 - 02:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Tue Jan 20, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
286199920386,2025cyclictest0-21swapper/019:10:190
286209919431904,25cyclictest88750irq/45-eth0-rx-19:10:191
286199917951735,50cyclictest0-21swapper/019:42:160
285582634615,12sleep10-21swapper/119:09:451
28620994754,12cyclictest0-21swapper/119:42:161
2861999816,68cyclictest0-21swapper/021:19:590
28620997721,44cyclictest0-21swapper/121:11:591
2861999773,68cyclictest23357-21ssh22:35:260
2861999742,49cyclictest4070-21ssh23:59:550
2861999733,40cyclictest14180-21ssh00:16:510
28620997220,38cyclictest0-21swapper/122:55:591
28620997217,39cyclictest0-21swapper/122:28:001
2861999728,56cyclictest0-21swapper/023:40:250
2861999728,56cyclictest0-21swapper/023:40:240
28619997224,43cyclictest0-21swapper/023:30:160
2861999716,57cyclictest0-21swapper/000:40:010
2861999715,59cyclictest0-21swapper/020:20:190
28620997016,38cyclictest0-21swapper/120:15:591
2861999709,56cyclictest88850irq/46-eth0-tx-23:25:120
28619997019,45cyclictest88850irq/46-eth0-tx-21:56:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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