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2026-02-15 - 00:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sat Feb 14, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
249799878797,49cyclictest0-21swapper/107:46:541
249699876798,52cyclictest0-21swapper/007:46:530
249699875779,90cyclictest0-21swapper/007:10:210
249799847763,43cyclictest3341-21netstat07:10:201
23882598577,15sleep10-21swapper/107:09:191
20492401378,16sleep00-21swapper/007:06:130
2286991330,12rtkit-daemon0-21swapper/011:02:290
249699896,32cyclictest0-21swapper/012:09:240
249699886,28cyclictest0-21swapper/011:45:570
2496998713,25cyclictest0-21swapper/011:15:320
2496998712,30cyclictest0-21swapper/011:05:150
249699866,32cyclictest0-21swapper/010:33:360
2496998615,27cyclictest0-21swapper/009:13:030
249699855,36cyclictest0-21swapper/012:02:240
249699839,28cyclictest0-21swapper/012:23:560
249699829,30cyclictest0-21swapper/011:42:340
2496998216,28cyclictest0-21swapper/009:37:260
2496998212,27cyclictest0-21swapper/009:50:210
249699818,33cyclictest0-21swapper/009:45:010
249699816,31cyclictest0-21swapper/011:23:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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