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2026-01-19 - 01:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sun Jan 18, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1996199446386,45cyclictest0-21swapper/107:10:181
1996199364330,18cyclictest30794-21taskset07:40:021
1995799355297,48cyclictest0-21swapper/007:10:180
195962129105,17sleep00-21swapper/007:06:460
1995799974,76cyclictest8145-21ssh12:27:590
228699950,4rtkit-daemon2285-21rtkit-daemon09:44:181
1980029517,23sleep10-21swapper/107:08:511
228699840,5rtkit-daemon2285-21rtkit-daemon12:31:570
228699840,4rtkit-daemon2285-21rtkit-daemon09:24:040
1995799832,66cyclictest8767-21ssh09:33:270
208342820,4sleep120836-21sed08:45:251
228699800,5rtkit-daemon2285-21rtkit-daemon09:39:380
228699800,4rtkit-daemon2285-21rtkit-daemon09:59:390
1995799806,54cyclictest0-21swapper/007:23:590
228699790,4rtkit-daemon2285-21rtkit-daemon10:19:490
228699790,4rtkit-daemon2285-21rtkit-daemon08:52:130
228699790,4rtkit-daemon2285-21rtkit-daemon08:35:470
228699780,4rtkit-daemon2285-21rtkit-daemon12:21:170
228699780,4rtkit-daemon2285-21rtkit-daemon11:02:060
228699780,4rtkit-daemon2285-21rtkit-daemon10:42:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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