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2026-03-09 - 07:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Mon Mar 09, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3232099929828,73cyclictest0-21swapper/019:30:190
3232199837738,70cyclictest8053-21strings19:30:181
318982646622,17sleep00-21swapper/019:06:090
3232099497425,43cyclictest0-21swapper/019:10:070
3232199410340,41cyclictest0-21swapper/119:10:061
319802253234,13sleep10-21swapper/119:06:571
407421460,3sleep14073-21ssh22:52:181
32320991037,88cyclictest0-21swapper/022:22:590
323209910188,6cyclictest30469-21ssh22:41:000
32320998868,14cyclictest0-21swapper/022:00:000
32320998810,70cyclictest3957-21ssh21:54:590
32321998727,45cyclictest0-21swapper/122:25:581
32321998711,57cyclictest0-21swapper/100:22:581
228699870,4rtkit-daemon2285-21rtkit-daemon21:34:461
228699860,4rtkit-daemon2285-21rtkit-daemon21:59:031
253512850,4sleep041ktimersoftd/021:35:050
228699830,4rtkit-daemon2285-21rtkit-daemon22:44:341
228699820,4rtkit-daemon2285-21rtkit-daemon23:09:431
32320998130,37cyclictest0-21swapper/000:22:590
228699810,3rtkit-daemon2285-21rtkit-daemon22:14:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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