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2026-03-19 - 09:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Thu Mar 19, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
242502660634,20sleep00-21swapper/019:07:590
2448799455370,51cyclictest0-21swapper/119:41:401
2448799414335,45cyclictest0-21swapper/119:10:081
2448599410327,54cyclictest0-21swapper/019:41:400
240572405383,15sleep10-21swapper/119:06:031
2448599370292,49cyclictest0-21swapper/019:10:080
2286991290,5rtkit-daemon0-21swapper/022:03:380
244859912512,107cyclictest0-21swapper/022:50:590
2286991030,3rtkit-daemon2285-21rtkit-daemon22:34:291
2286991030,10rtkit-daemon0-21swapper/120:58:011
228699950,11rtkit-daemon0-21swapper/100:35:401
228699850,5rtkit-daemon3208-21diskmemload23:35:240
228699850,5rtkit-daemon3208-21diskmemload23:35:240
2448599848,59cyclictest0-21swapper/022:11:590
24485998411,59cyclictest0-21swapper/020:37:590
24485998223,42cyclictest0-21swapper/021:30:000
2448799817,28cyclictest0-21swapper/100:20:111
2448799808,35cyclictest0-21swapper/120:10:221
2448799807,31cyclictest0-21swapper/123:35:141
2448799807,31cyclictest0-21swapper/123:35:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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