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2026-01-16 - 22:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Fri Jan 16, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
275072722698,16sleep00-21swapper/007:08:510
2766099459389,61cyclictest0-21swapper/007:10:170
2766099458373,76cyclictest0-21swapper/007:38:560
2766199308267,25cyclictest28463-21strings07:10:181
273222204182,15sleep10-21swapper/107:07:001
276609910916,29cyclictest0-21swapper/010:46:590
276609910887,15cyclictest0-21swapper/012:18:590
2286991010,4rtkit-daemon2285-21rtkit-daemon07:42:441
228699970,4rtkit-daemon2285-21rtkit-daemon07:22:591
228699960,4rtkit-daemon2285-21rtkit-daemon11:48:491
228699950,4rtkit-daemon2285-21rtkit-daemon12:22:131
228699940,4rtkit-daemon2285-21rtkit-daemon08:55:101
228699940,4rtkit-daemon2285-21rtkit-daemon08:52:201
228699940,4rtkit-daemon2285-21rtkit-daemon08:46:251
228699930,4rtkit-daemon2285-21rtkit-daemon10:56:371
228699930,4rtkit-daemon2285-21rtkit-daemon10:32:321
228699930,4rtkit-daemon2285-21rtkit-daemon09:02:401
228699930,4rtkit-daemon2285-21rtkit-daemon08:26:441
228699930,4rtkit-daemon2285-21rtkit-daemon07:55:541
228699920,4rtkit-daemon2285-21rtkit-daemon12:05:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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