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2026-01-25 - 18:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sun Jan 25, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
261989918261764,49cyclictest15-21rcuop/109:35:200
2609721009986,16sleep10-21swapper/107:09:241
2619899489409,49cyclictest0-21swapper/007:11:020
2619999488407,51cyclictest0-21swapper/107:11:031
2619999381305,21cyclictest19957-21strings09:35:201
2286991460,12rtkit-daemon0-21swapper/011:59:180
100772850,3sleep010076-21ssh12:14:120
26198997528,9cyclictest835-21lldpad09:55:240
26198997139,12cyclictest8788-21ps09:15:230
26198997130,34cyclictest11768-21munin-node10:20:130
26198997043,22cyclictest4910-21diskmemload12:05:290
26198997029,25cyclictest13742-21latency_hist08:05:010
26198996939,16cyclictest88850irq/46-eth0-tx-09:53:490
26198996934,10cyclictest23784-21df11:40:130
26198996830,32cyclictest20388-21unixbench_multi08:20:250
26198996822,39cyclictest21990-21sendmail_mailtr08:25:230
26198996745,17cyclictest0-21swapper/008:05:170
26198996737,24cyclictest11135-21gltestperf09:20:150
26198996734,9cyclictest14043-21ntp_states12:20:220
26198996730,10cyclictest15320-21ssh11:25:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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