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2025-06-28 - 23:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sat Jun 28, 2025 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4504999514,14cyclictest0-21swapper/107:10:101
450399928855,65cyclictest0-21swapper/007:10:100
450499820777,29cyclictest0-21swapper/107:50:271
450399815742,37cyclictest19748-21strings07:50:270
44432673654,13sleep10-21swapper/107:09:451
294982840,3sleep129500-21sed11:20:301
249432830,17sleep0450399cyclictest12:09:320
216899830,4rtkit-daemon2167-21rtkit-daemon12:10:221
450399794,69cyclictest0-21swapper/010:58:580
450499788,21cyclictest0-21swapper/112:35:291
450499788,21cyclictest0-21swapper/112:35:291
450499776,18cyclictest0-21swapper/109:53:301
450499766,17cyclictest0-21swapper/110:55:011
450499766,17cyclictest0-21swapper/108:00:191
450499765,17cyclictest0-21swapper/111:17:521
4504997631,38cyclictest4649-21ksmtuned09:45:011
4504997612,23cyclictest0-21swapper/109:45:191
216899760,4rtkit-daemon0-21swapper/009:52:240
450499756,29cyclictest0-21swapper/109:30:191
450499756,28cyclictest0-21swapper/111:35:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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