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2026-03-02 - 04:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Mon Mar 02, 2026 00:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2736799897814,77cyclictest0-21swapper/019:29:260
2736899837768,35cyclictest0-21swapper/119:29:261
268922636613,15sleep10-21swapper/119:05:341
2736799452381,51cyclictest0-21swapper/019:10:100
2736899404335,47cyclictest0-21swapper/119:10:091
2475321260,4sleep024754-21sh23:40:000
273689911610,68cyclictest0-21swapper/100:03:581
2286991060,11rtkit-daemon0-21swapper/020:19:051
2712029673,15sleep00-21swapper/019:07:520
228699890,4rtkit-daemon2285-21rtkit-daemon21:52:160
27368998534,35cyclictest0-21swapper/123:44:591
228699840,3rtkit-daemon28601-21ssh21:49:560
5972810,4sleep1598-21munin-run23:55:001
27367997864,9cyclictest0-21swapper/000:02:580
228699780,4rtkit-daemon2285-21rtkit-daemon21:33:310
228699780,4rtkit-daemon2285-21rtkit-daemon21:19:210
228699770,4rtkit-daemon2285-21rtkit-daemon22:36:581
228699770,4rtkit-daemon2285-21rtkit-daemon00:27:001
27368997613,56cyclictest0-21swapper/123:15:001
228699760,4rtkit-daemon2285-21rtkit-daemon23:47:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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