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2026-03-09 - 15:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Mon Mar 09, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157422923904,12sleep10-21swapper/107:05:591
1617999826745,52cyclictest0-21swapper/007:10:010
1618099496418,46cyclictest0-21swapper/107:19:271
1617999423346,54cyclictest0-21swapper/007:19:260
16179991235,99cyclictest0-21swapper/009:29:590
2377021050,3sleep123771-21ssh11:56:201
161799910016,66cyclictest0-21swapper/012:35:580
228699990,4rtkit-daemon2285-21rtkit-daemon09:34:491
228699980,4rtkit-daemon2285-21rtkit-daemon10:04:091
228699950,4rtkit-daemon2285-21rtkit-daemon09:57:041
228699940,4rtkit-daemon2285-21rtkit-daemon11:44:011
228699940,4rtkit-daemon2285-21rtkit-daemon07:41:121
228699930,5rtkit-daemon2285-21rtkit-daemon10:41:051
228699930,4rtkit-daemon2285-21rtkit-daemon12:05:011
228699930,4rtkit-daemon2285-21rtkit-daemon11:50:411
228699930,4rtkit-daemon2285-21rtkit-daemon11:33:411
228699930,4rtkit-daemon2285-21rtkit-daemon10:52:351
228699930,4rtkit-daemon2285-21rtkit-daemon10:39:301
228699930,4rtkit-daemon2285-21rtkit-daemon07:49:371
228699920,5rtkit-daemon2285-21rtkit-daemon08:57:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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