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2026-02-07 - 22:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sat Feb 07, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
645299802725,44cyclictest0-21swapper/107:49:511
645199781706,47cyclictest0-21swapper/007:49:510
61262718695,16sleep00-21swapper/007:07:060
62592676657,13sleep10-21swapper/107:08:281
645199407329,64cyclictest6657-21aten_r1power_en07:10:130
645299405339,27cyclictest6639-21aten_r1power_en07:10:121
6451998716,16cyclictest0-21swapper/011:29:050
188582850,7sleep10-21swapper/112:05:271
645199848,69cyclictest0-21swapper/009:55:230
645299827,34cyclictest0-21swapper/110:44:151
645299817,35cyclictest0-21swapper/111:40:271
645199805,28cyclictest0-21swapper/009:37:180
6451998017,14cyclictest0-21swapper/010:15:350
6451998016,15cyclictest0-21swapper/011:12:550
645199797,17cyclictest0-21swapper/012:30:210
6451997917,15cyclictest0-21swapper/012:02:250
645199785,27cyclictest0-21swapper/011:22:530
645199785,25cyclictest0-21swapper/009:15:020
6451997818,15cyclictest0-21swapper/011:15:360
6451997818,13cyclictest0-21swapper/011:04:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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