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2026-02-22 - 01:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sat Feb 21, 2026 12:43:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70659919241851,38cyclictest11345-21irqstats07:20:170
706699883839,28cyclictest0-21swapper/107:10:021
66082846824,15sleep10-21swapper/107:05:461
706599767693,63cyclictest0-21swapper/007:10:020
706699426385,26cyclictest0-21swapper/107:20:171
68772389365,17sleep00-21swapper/007:08:270
2286991570,24rtkit-daemon0-21swapper/009:46:400
7066999513,64cyclictest0-21swapper/112:10:581
7066999414,59cyclictest0-21swapper/109:46:001
7066999227,44cyclictest0-21swapper/109:37:001
7065999174,12cyclictest0-21swapper/008:41:000
7065998563,17cyclictest17337-21ssh11:04:590
228699850,5rtkit-daemon2285-21rtkit-daemon09:31:590
228699820,5rtkit-daemon2285-21rtkit-daemon09:16:001
228699790,5rtkit-daemon2285-21rtkit-daemon09:20:541
228699780,4rtkit-daemon2285-21rtkit-daemon10:00:501
228699760,4rtkit-daemon2285-21rtkit-daemon07:31:480
706699757,45cyclictest0-21swapper/111:46:591
7066997316,38cyclictest0-21swapper/111:35:591
228699720,5rtkit-daemon2285-21rtkit-daemon08:15:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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