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2026-02-11 - 23:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Wed Feb 11, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154222879860,13sleep10-21swapper/107:08:481
1557699868787,49cyclictest0-21swapper/108:18:581
1557599807727,53cyclictest0-21swapper/008:18:580
1557599528451,52cyclictest0-21swapper/007:10:110
151922394370,17sleep00-21swapper/007:06:280
1557699384306,45cyclictest0-21swapper/107:10:111
2286991080,3rtkit-daemon2285-21rtkit-daemon09:57:011
228699980,4rtkit-daemon2285-21rtkit-daemon12:03:291
228699970,4rtkit-daemon2285-21rtkit-daemon07:21:331
228699970,4rtkit-daemon2285-21rtkit-daemon07:18:541
228699930,4rtkit-daemon2285-21rtkit-daemon12:15:481
228699920,4rtkit-daemon2285-21rtkit-daemon12:37:041
1557599876,29cyclictest0-21swapper/011:55:220
1557599859,57cyclictest0-21swapper/010:25:210
1557599856,59cyclictest0-21swapper/008:05:000
15575998314,19cyclictest0-21swapper/012:12:390
1557599828,26cyclictest0-21swapper/010:15:350
1557599826,28cyclictest0-21swapper/007:30:190
15575998218,15cyclictest0-21swapper/007:25:140
15575998111,7cyclictest11813-21idleruntime-cro10:40:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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