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2026-01-31 - 21:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sat Jan 31, 2026 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
295699918931831,55cyclictest0-21swapper/007:21:250
290892890872,13sleep10-21swapper/107:05:351
291992688665,16sleep00-21swapper/007:06:410
2957099458403,41cyclictest0-21swapper/107:21:251
2956999385319,60cyclictest0-21swapper/007:10:030
2957099384329,40cyclictest0-21swapper/107:10:031
2956999825,61cyclictest0-21swapper/011:55:010
2956999755,54cyclictest0-21swapper/012:35:000
29569997510,58cyclictest7895-21ssh10:25:480
2956999733,54cyclictest8387-21latency_hist09:10:020
2956999712,63cyclictest1189-21snmpd12:37:010
2956999712,62cyclictest25857-21runrttasks08:27:200
2956999702,62cyclictest28928-21ssh11:03:110
2956999702,61cyclictest8278-21diskmemload10:46:470
2956999702,50cyclictest6355-21latency_hist10:25:010
2956999702,44cyclictest30266-21ssh12:00:430
2957099693,48cyclictest14773-21munin-node11:35:131
2957099692,8cyclictest19008-21runrttasks09:39:101
2956999692,61cyclictest17857-21ssh10:44:270
2956999692,61cyclictest17857-21ssh10:44:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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