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2026-01-18 - 12:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Sun Jan 18, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2286998960,876rtkit-daemon0-21swapper/119:06:051
629699859762,88cyclictest14858-21sort19:35:010
629799794704,61cyclictest14857-21ls19:35:021
629699440347,86cyclictest0-21swapper/019:10:180
58512419396,16sleep00-21swapper/019:05:540
629799346281,26cyclictest6964-21iostat19:10:191
6297999063,21cyclictest0-21swapper/123:46:001
228699840,4rtkit-daemon2285-21rtkit-daemon21:25:170
228699830,4rtkit-daemon2285-21rtkit-daemon00:38:410
228699810,4rtkit-daemon2285-21rtkit-daemon22:44:431
228699810,4rtkit-daemon2285-21rtkit-daemon20:09:060
228699790,4rtkit-daemon2285-21rtkit-daemon23:13:590
228699750,4rtkit-daemon2285-21rtkit-daemon22:22:280
228699730,4rtkit-daemon2285-21rtkit-daemon23:33:140
228699730,4rtkit-daemon2285-21rtkit-daemon22:00:231
6297997113,47cyclictest0-21swapper/121:41:001
228699710,5rtkit-daemon2285-21rtkit-daemon22:08:040
228699710,4rtkit-daemon2285-21rtkit-daemon20:10:121
6297997016,37cyclictest0-21swapper/119:54:001
6296997018,46cyclictest0-21swapper/021:54:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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