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2026-02-10 - 22:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Tue Feb 10, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31922998916,867cyclictest0-21swapper/110:28:461
3192199811734,40cyclictest22429-21ssh10:28:460
317032635613,15sleep10-21swapper/107:08:111
3192199530436,87cyclictest0-21swapper/007:10:520
3192299433357,51cyclictest0-21swapper/107:10:521
319219910013,82cyclictest0-21swapper/010:00:000
31922999310,68cyclictest0-21swapper/109:44:591
31921998657,24cyclictest0-21swapper/010:01:590
31921998514,30cyclictest0-21swapper/010:31:000
228699810,4rtkit-daemon2285-21rtkit-daemon11:22:541
228699800,4rtkit-daemon2285-21rtkit-daemon11:34:001
31922997923,35cyclictest0-21swapper/109:56:591
31922997918,40cyclictest0-21swapper/109:52:591
31922997819,39cyclictest0-21swapper/107:53:001
31922997819,37cyclictest0-21swapper/108:46:591
31921997812,51cyclictest0-21swapper/011:26:590
228699780,4rtkit-daemon2285-21rtkit-daemon10:31:531
228699780,4rtkit-daemon2285-21rtkit-daemon09:49:320
228699780,4rtkit-daemon2285-21rtkit-daemon08:30:371
31922997717,38cyclictest0-21swapper/107:48:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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