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2026-04-20 - 11:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot8.osadl.org (updated Mon Apr 20, 2026 00:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1762599888784,74cyclictest18250-21if_eth019:10:161
1762499869763,78cyclictest0-21swapper/019:10:160
1762599859793,35cyclictest0-21swapper/119:44:331
1762499828756,45cyclictest0-21swapper/019:44:330
175542720698,15sleep00-21swapper/019:09:390
174392538516,14sleep10-21swapper/119:08:301
2286991260,3rtkit-daemon2285-21rtkit-daemon23:46:021
2286991020,10rtkit-daemon0-21swapper/119:39:091
279842960,4sleep127983-210anacron00:01:001
228699960,3rtkit-daemon2285-21rtkit-daemon19:56:141
1762499945,64cyclictest0-21swapper/019:48:010
170372830,4sleep10-21swapper/123:41:361
1762599827,30cyclictest0-21swapper/121:50:191
1762599807,17cyclictest0-21swapper/122:25:011
1762599796,28cyclictest0-21swapper/121:49:331
1762599786,33cyclictest0-21swapper/121:00:141
17625997817,13cyclictest0-21swapper/123:58:331
1762599777,29cyclictest0-21swapper/100:25:201
1762599776,18cyclictest0-21swapper/100:17:511
1762599768,27cyclictest0-21swapper/100:30:171
1762499762,68cyclictest835-21lldpad21:05:210
1762599757,28cyclictest0-21swapper/121:30:211
1762599756,30cyclictest0-21swapper/121:11:391
1762599756,28cyclictest0-21swapper/123:52:491
1762599756,18cyclictest0-21swapper/119:15:171
1762599755,26cyclictest0-21swapper/122:44:271
1762599755,15cyclictest0-21swapper/122:52:141
17625997516,14cyclictest0-21swapper/123:17:441
17625997515,24cyclictest0-21swapper/100:05:241
1762599748,30cyclictest0-21swapper/100:10:181
1762599747,18cyclictest0-21swapper/122:55:301
1762599746,29cyclictest0-21swapper/123:36:391
1762599746,27cyclictest0-21swapper/123:25:131
1762599746,27cyclictest0-21swapper/123:25:121
1762599746,27cyclictest0-21swapper/120:34:581
1762599745,35cyclictest0-21swapper/122:48:231
1762599745,18cyclictest0-21swapper/120:20:011
17625997411,23cyclictest0-21swapper/121:35:151
17625997410,21cyclictest0-21swapper/123:05:181
1762599736,29cyclictest0-21swapper/122:27:481
1762599736,27cyclictest0-21swapper/122:19:281
1762599736,25cyclictest0-21swapper/122:02:411
1762599735,29cyclictest0-21swapper/120:25:141
1762599735,28cyclictest0-21swapper/121:55:451
1762599735,27cyclictest0-21swapper/121:05:211
1762599735,27cyclictest0-21swapper/120:00:281
1762599735,26cyclictest0-21swapper/120:45:001
17625997316,21cyclictest28198-21ssh23:05:001
1762499732,65cyclictest4157-21missed_timers20:00:200
1762599729,20cyclictest0-21swapper/123:10:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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