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2026-01-11 - 06:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun Jan 11, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
223782900,0sleep122277-21sshd23:16:251
7132750,2sleep31332499cyclictest23:09:113
18722740,2sleep01331199cyclictest00:28:500
11432560,0sleep10-21swapper/122:50:011
294492540,0sleep10-21swapper/122:49:421
294492540,0sleep10-21swapper/122:49:421
180442540,0sleep20-21swapper/222:21:222
80272520,1sleep38030-21lspci23:20:403
40592520,0sleep3391rcuc/300:29:003
309652520,0sleep20-21swapper/223:36:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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