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2026-05-04 - 06:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon May 04, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38121020,0sleep00-21swapper/023:27:480
10382690,0sleep30-21swapper/300:20:183
106772560,0sleep20-21swapper/221:54:492
251502550,1sleep025152-21sed21:30:190
217262540,0sleep00-21swapper/023:43:260
70262530,1sleep10-21swapper/122:46:551
178832530,0sleep30-21swapper/322:31:193
78102520,0sleep30-21swapper/300:18:083
280632520,0sleep20-21swapper/221:36:592
178602520,2sleep13257499cyclictest21:36:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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