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2025-12-19 - 21:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri Dec 19, 2025 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
166562830,0sleep30-21swapper/310:31:023
140342720,1sleep03221699cyclictest09:51:490
53502610,1sleep2311rcuc/212:33:042
80662580,0sleep10-21swapper/112:39:131
290422580,0sleep10-21swapper/110:52:421
167132570,1sleep016693-21sshd10:18:570
16542560,1sleep0111rcuc/010:38:310
41672530,1sleep34170-21nfsd409:20:163
320712530,1sleep332073-21grep12:12:043
204272530,0sleep00-21swapper/011:21:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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