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2026-05-21 - 11:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu May 21, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
92802720,0sleep30-21swapper/322:54:513
211162720,1sleep09-21ksoftirqd/023:45:550
244212590,0sleep00-21swapper/022:56:040
213052580,0sleep30-21swapper/322:55:463
112062580,0sleep30-21swapper/323:28:233
275012560,0sleep30-21swapper/321:38:203
53712540,1sleep0699-21gdbus22:51:390
52042540,0sleep10-21swapper/121:41:581
2395925342,7sleep20-21swapper/219:06:482
240502520,0sleep00-21swapper/022:47:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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