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2026-05-02 - 18:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat May 02, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2084821140,0sleep20-21swapper/210:23:032
210321070,0sleep00-21swapper/010:35:270
83922720,0sleep08391-21bash12:22:490
45132710,0sleep00-21swapper/010:24:290
274632560,0sleep327361-21sshd11:36:433
165502560,0sleep00-21swapper/011:32:590
252292550,1sleep0674-21dbus-daemon11:47:490
259582540,0sleep10-21swapper/111:16:531
147582530,1sleep0674-21dbus-daemon10:28:100
138542530,1sleep313852-21sshd10:19:403
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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