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2026-05-24 - 22:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun May 24, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300732730,1sleep1902699cyclictest09:10:141
22062560,2sleep1902699cyclictest10:54:401
252242550,1sleep025219-21bash11:18:580
249822550,1sleep224980-21lspci10:28:492
207132550,0sleep00-21swapper/012:33:520
301812540,0sleep20-21swapper/210:12:352
301812540,0sleep20-21swapper/210:12:352
200422540,0sleep20-21swapper/210:22:492
200422540,0sleep20-21swapper/210:22:482
127772530,0sleep30-21swapper/309:40:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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