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2026-01-23 - 03:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri Jan 23, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
162412920,0sleep10-21swapper/121:31:441
45762760,0sleep30-21swapper/300:33:223
107452580,0sleep20-21swapper/222:55:082
156412560,0sleep3391rcuc/321:45:243
200802550,1sleep220076-21sshd23:12:152
134992550,0sleep00-21swapper/021:15:290
276752540,0sleep10-21swapper/123:15:331
221762540,0sleep00-21swapper/023:45:160
167362540,0sleep30-21swapper/322:31:013
240522520,0sleep30-21swapper/322:37:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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