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2026-01-23 - 15:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri Jan 23, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26271997171,0cyclictest527-40kipmi012:27:341
26270996060,0cyclictest1002-21snmpd12:27:340
26272995656,0cyclictest12951-21kworker/2:312:27:312
103782550,1sleep010362-21cp10:05:340
249382540,0sleep10-21swapper/109:12:161
190392540,0sleep20-21swapper/209:59:442
84582530,0sleep10-21swapper/110:25:331
101402520,1sleep20-21swapper/212:20:212
101332520,2sleep12627199cyclictest07:45:191
69302510,0sleep16933-21tail10:05:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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