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2026-01-08 - 19:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu Jan 08, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
99272910,0sleep09928-21sshd11:12:450
167762830,0sleep00-21swapper/010:31:020
172962720,0sleep10-21swapper/110:58:551
100872710,1sleep310089-21latency10:05:153
320622560,0sleep30-21swapper/311:00:093
258852550,0sleep20-21swapper/212:20:562
169492540,0sleep00-21swapper/009:45:010
133782540,0sleep20-21swapper/210:16:022
166182520,0sleep30-21swapper/310:42:073
52582500,0sleep00-21swapper/010:52:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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