You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-27 - 05:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue Jan 27, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
99372830,0sleep30-21swapper/323:13:553
213232780,0sleep20-21swapper/200:15:342
98462750,0sleep00-21swapper/022:38:110
117672600,0sleep10-21swapper/121:40:371
47182580,10sleep375750irq/24-eno1-rx-00:25:163
71022570,0sleep20-21swapper/200:03:202
6112530,1sleep3391rcuc/323:54:323
124762530,1sleep0111rcuc/020:45:140
162882510,1sleep229977-21packagekitd22:35:572
54972500,0sleep30-21swapper/323:08:023
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional