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2026-01-24 - 03:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Jan 24, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127942950,1sleep1520599cyclictest22:11:531
134122930,0sleep10-21swapper/121:44:181
190772850,0sleep219078-21sshd21:34:292
123832710,0sleep10-21swapper/123:33:291
213432620,0sleep10-21swapper/123:03:561
322412570,1sleep132244-21bash21:53:121
95182560,1sleep09510-21sshd23:30:230
91802520,0sleep30-21swapper/300:36:303
70562520,1sleep10-21swapper/100:11:341
180882520,0sleep10-21swapper/119:40:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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