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2026-02-21 - 14:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Feb 21, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
187382840,0sleep018737-21sshd11:58:230
171412800,1sleep3674-21dbus-daemon09:13:363
327422720,0sleep20-21swapper/211:44:232
311672570,0sleep30-21swapper/309:38:153
41942520,1sleep14196-21bash11:21:141
173792520,0sleep10-21swapper/112:21:431
58682510,1sleep01108499cyclictest10:30:350
295362510,0sleep10-21swapper/112:35:051
231312510,0sleep10-21swapper/111:58:561
1064025140,7sleep20-21swapper/207:05:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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