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2025-12-22 - 15:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Dec 22, 2025 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
79712970,0sleep07880-21sshd10:59:300
9002780,0sleep20-21swapper/209:46:462
42322770,1sleep3391rcuc/310:37:303
13912760,0sleep20-21swapper/209:40:022
69562650,0sleep20-21swapper/211:26:362
132912580,0sleep213268-21sshd11:59:492
47782550,0sleep10-21swapper/107:30:141
248332540,0sleep0111rcuc/010:06:280
118452530,1sleep2321ktimersoftd/212:02:202
231072520,0sleep00-21swapper/011:41:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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