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2026-01-16 - 01:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri Jan 16, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1128721040,2sleep175850irq/25-eno1-tx-23:33:061
270052940,2sleep03040899cyclictest22:31:320
82772650,0sleep10-21swapper/100:13:551
131062620,0sleep20-21swapper/200:30:372
109622580,1sleep31-21systemd00:22:183
16212570,0sleep30-21swapper/323:05:003
58472560,0sleep00-21swapper/000:32:490
22152560,1sleep20-21swapper/223:56:582
151812550,0sleep30-21swapper/322:16:023
203542540,0sleep00-21swapper/000:39:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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