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2026-05-17 - 16:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun May 17, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
56142960,0sleep00-21swapper/011:34:040
254552940,0sleep20-21swapper/210:01:252
192112850,0sleep119075-21sshd11:01:521
275252810,0sleep20-21swapper/209:58:532
191462760,0sleep00-21swapper/011:43:330
89102580,0sleep10-21swapper/112:02:081
264462570,0sleep20-21swapper/210:23:442
217712570,0sleep00-21swapper/012:03:160
38182540,0sleep10-21swapper/110:55:031
38182540,0sleep10-21swapper/110:55:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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