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2026-04-16 - 14:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu Apr 16, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
61292890,0sleep01-21systemd09:16:120
150062850,0sleep115005-21sshd12:30:241
123892680,1sleep2674-21dbus-daemon11:33:212
277202560,0sleep00-21swapper/010:54:450
139872560,0sleep20-21swapper/211:36:532
228822550,1sleep2660-21avahi-daemon10:57:082
166342550,0sleep316635-21sshd10:39:383
132062550,1sleep01-21systemd12:13:160
118902550,1sleep211893-21grep11:01:522
54572540,1sleep0663-21ModemManager12:06:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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