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2026-01-12 - 08:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Jan 12, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157192840,0sleep2642-21systemd-logind21:26:402
246622740,1sleep3674-21dbus-daemon22:10:403
16382600,0sleep20-21swapper/222:41:062
317182570,0sleep00-21swapper/022:15:000
257032570,0sleep20-21swapper/221:11:422
157932560,0sleep20-21swapper/223:12:512
24532540,0sleep00-21swapper/023:42:160
99242530,0sleep20-21swapper/222:58:282
45742520,0sleep10-21swapper/100:18:351
220342520,0sleep00-21swapper/023:49:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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