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2025-08-27 - 02:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Aug 27, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126772810,0sleep0101ktimersoftd/023:45:080
164852790,0sleep10-21swapper/122:28:061
223172640,4sleep10-21swapper/121:17:481
193742590,0sleep00-21swapper/021:36:020
191592590,0sleep00-21swapper/000:21:520
72602580,0sleep20-21swapper/200:24:072
305642580,1sleep130535-21sshd00:13:011
172162550,0sleep30-21swapper/322:56:043
6132540,0sleep30-21swapper/321:31:083
146482540,5sleep00-21swapper/000:04:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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