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2026-05-25 - 23:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon May 25, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
310432890,1sleep3674-21dbus-daemon09:33:103
126832600,0sleep10-21swapper/111:53:451
169372590,0sleep10-21swapper/109:51:361
235722580,0sleep00-21swapper/012:28:050
51412570,0sleep30-21swapper/311:08:313
36932560,0sleep20-21swapper/211:00:062
198582560,0sleep20-21swapper/210:33:382
68762550,0sleep00-21swapper/010:51:590
68762550,0sleep00-21swapper/010:51:580
51862540,0sleep10-21swapper/111:14:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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