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2026-02-25 - 15:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Feb 25, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
125672740,0sleep0101ktimersoftd/012:16:250
189972610,0sleep20-21swapper/212:13:172
179022540,0sleep10-21swapper/111:13:531
95372520,2sleep12615699cyclictest10:45:131
78822520,0sleep10-21swapper/110:52:551
41042510,0sleep30-21swapper/310:24:563
236612490,0sleep30-21swapper/310:31:093
112542490,0sleep20-21swapper/212:04:292
112542490,0sleep20-21swapper/212:04:282
91512480,0sleep10-21swapper/111:16:421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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