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2026-01-02 - 06:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri Jan 02, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
319942940,0sleep331977-21sshd22:26:563
18262730,0sleep30-21swapper/323:38:433
81902570,0sleep20-21swapper/222:11:222
279492560,0sleep00-21swapper/000:00:370
311472550,1sleep131139-21sshd23:52:301
246762550,0sleep3401ktimersoftd/323:29:213
174042550,0sleep00-21swapper/023:31:310
44472520,0sleep10-21swapper/123:24:421
33952520,0sleep00-21swapper/023:27:250
208492520,0sleep00-21swapper/000:31:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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