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2026-01-26 - 13:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Jan 26, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251472910,0sleep00-21swapper/011:16:410
131782860,0sleep313179-21grep12:29:543
235092790,2sleep31538399cyclictest10:27:213
60742570,0sleep3391rcuc/310:45:013
32102570,0sleep20-21swapper/210:50:112
266282570,1sleep3401ktimersoftd/311:14:083
261832570,1sleep20-21swapper/209:54:572
99842520,0sleep30-21swapper/310:37:073
77172510,1sleep17719-21bash09:32:081
58462510,0sleep00-21swapper/011:53:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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