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2026-03-25 - 19:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Mar 25, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26132730,0sleep00-21swapper/010:55:060
29992630,0sleep10-21swapper/111:19:471
29992630,0sleep10-21swapper/111:19:461
103182580,0sleep30-21swapper/309:22:323
172782570,1sleep2321ktimersoftd/209:34:212
108542550,0sleep30-21swapper/312:09:553
289592540,0sleep30-21swapper/311:49:213
217922540,1sleep2321ktimersoftd/210:34:532
81562530,0sleep00-21swapper/010:33:430
159692530,0sleep10-21swapper/109:58:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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