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2025-12-09 - 00:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Dec 08, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
107022970,0sleep21345999cyclictest09:14:422
223532930,0sleep00-21swapper/009:15:480
295182920,0sleep30-21swapper/310:53:353
175782880,0sleep317579-21sshd11:42:373
51452770,0sleep20-21swapper/210:47:132
232192750,1sleep01344899cyclictest07:30:160
165882600,0sleep20-21swapper/211:14:122
304202590,0sleep00-21swapper/011:50:550
27712590,0sleep20-21swapper/211:44:362
183082570,1sleep341-21ksoftirqd/310:09:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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