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2026-01-07 - 16:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Jan 07, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
302422870,0sleep330202-21sshd11:56:593
182862760,1sleep018288-21bash11:31:170
179012620,0sleep00-21swapper/010:39:060
122912620,1sleep212284-21sshd11:39:052
161072540,0sleep00-21swapper/012:01:170
140012540,1sleep2311rcuc/212:31:282
249772530,0sleep20-21swapper/211:34:392
3162925240,7sleep30-21swapper/307:08:433
27142520,0sleep10-21swapper/109:33:021
218922520,3sleep2674-21dbus-daemon11:12:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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