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2026-04-15 - 14:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Apr 15, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184252610,1sleep318411-21sshd12:01:183
184252610,1sleep318411-21sshd12:01:173
112892570,0sleep00-21swapper/012:17:480
43112560,0sleep30-21swapper/310:00:293
326702560,1sleep032669-21sshd11:51:140
286582540,0sleep30-21swapper/310:57:533
194372540,0sleep30-21swapper/310:54:203
185002540,1sleep118491-21lspci11:24:501
168642520,0sleep11-21systemd10:29:151
162002520,0sleep30-21swapper/311:19:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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