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2026-05-01 - 17:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri May 01, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
189862750,0sleep00-21swapper/011:23:290
242832740,0sleep10-21swapper/109:54:421
20492740,0sleep10-21swapper/111:19:091
91892610,1sleep3674-21dbus-daemon10:57:123
310652590,1sleep131042-21sshd10:25:381
16745995757,0cyclictest335-21scsi_eh_212:25:462
324542560,1sleep332447-21bash10:34:093
8492550,0sleep30-21swapper/312:15:043
136252550,0sleep20-21swapper/211:00:202
193442530,1sleep10-21swapper/110:52:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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