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2026-04-23 - 09:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu Apr 23, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
123462970,0sleep312347-21sshd22:50:493
309612940,0sleep20-21swapper/221:19:162
15102910,0sleep00-21swapper/021:31:240
68682590,0sleep20-21swapper/222:17:002
58632590,1sleep0674-21dbus-daemon23:37:360
307422570,0sleep10-21swapper/121:56:441
287982570,0sleep20-21swapper/221:42:392
82662530,0sleep18264-21sshd22:28:171
178412530,0sleep10-21swapper/121:52:521
298622520,0sleep10-21swapper/121:34:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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