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2026-05-27 - 00:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue May 26, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
319862960,0sleep30-21swapper/311:30:043
315402570,0sleep131538-21lspci10:54:001
93542560,2sleep11386299cyclictest12:01:181
59712560,0sleep10-21swapper/111:38:551
32772540,0sleep10-21swapper/109:14:191
300772520,0sleep10-21swapper/109:17:311
230452520,0sleep20-21swapper/211:54:132
101322520,1sleep2699-21gdbus11:08:482
101072520,0sleep30-21swapper/309:56:433
101072520,0sleep30-21swapper/309:56:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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