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2026-01-22 - 03:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu Jan 22, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231832950,0sleep00-21swapper/022:59:110
247912940,2sleep13101499cyclictest21:46:131
119352790,0sleep20-21swapper/200:37:342
61542750,1sleep33102499cyclictest00:20:293
253142750,0sleep10-21swapper/100:11:051
308102650,0sleep20-21swapper/200:14:222
304702620,1sleep3401ktimersoftd/323:24:283
253342620,0sleep025332-21grep00:22:090
273242600,0sleep30-21swapper/322:17:473
62912590,0sleep30-21swapper/322:08:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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