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2025-12-12 - 11:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri Dec 12, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
539821140,0sleep15326-21sshd23:01:231
165722970,0sleep20-21swapper/223:52:362
119852940,0sleep00-21swapper/021:31:320
109172940,0sleep00-21swapper/023:42:080
52922830,2sleep01106699cyclictest23:24:580
306772700,0sleep00-21swapper/021:20:100
307492600,0sleep20-21swapper/223:14:142
219252600,0sleep20-21swapper/222:56:252
100302590,0sleep30-21swapper/323:25:213
60932580,1sleep06090-21sshd23:25:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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