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2025-11-10 - 06:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Nov 10, 2025 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131012830,0sleep013102-21sshd00:28:280
240642720,0sleep00-21swapper/021:59:330
160392620,1sleep20-21swapper/221:45:092
217332600,0sleep00-21swapper/021:19:000
235332570,0sleep30-21swapper/321:19:123
322352540,0sleep30-21swapper/321:53:393
128112540,0sleep30-21swapper/300:12:133
129702530,1sleep125-21ksoftirqd/119:10:001
89202520,0sleep20-21swapper/200:28:022
28372520,0sleep1231rcuc/100:30:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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