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2026-05-12 - 14:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue May 12, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
606621050,0sleep2311rcuc/210:15:492
1434221020,0sleep20-21swapper/210:33:132
1152521000,0sleep20-21swapper/210:41:132
175902820,0sleep20-21swapper/212:08:122
92412740,0sleep30-21swapper/310:38:183
245332730,0sleep10-21swapper/111:32:241
207942590,2sleep3980199cyclictest10:44:503
27902580,1sleep11-21systemd10:48:501
215432570,0sleep00-21swapper/009:52:160
182802570,0sleep0111rcuc/009:16:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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