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2026-04-19 - 16:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun Apr 19, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139162950,2sleep1358999cyclictest11:48:181
277722810,0sleep10-21swapper/111:24:421
33302630,1sleep1241ktimersoftd/112:09:331
110162560,1sleep011012-21sshd10:52:490
116942550,1sleep21-21systemd09:46:152
116342550,1sleep11-21systemd10:02:561
326332530,0sleep00-21swapper/009:48:050
257352530,0sleep20-21swapper/211:46:312
268072520,0sleep30-21swapper/311:57:413
140052510,0sleep20-21swapper/210:22:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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