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2026-04-27 - 14:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Apr 27, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36262980,0sleep30-21swapper/310:17:483
264442820,2sleep01319099cyclictest12:07:400
155232730,0sleep20-21swapper/209:37:342
48452640,0sleep30-21swapper/310:04:103
277182580,0sleep327713-21lspci11:59:293
314692570,0sleep30-21swapper/310:06:233
287952570,0sleep20-21swapper/212:33:092
149192560,2sleep21320299cyclictest09:45:432
75512550,0sleep30-21swapper/310:43:033
45022550,1sleep24501-21grepconf.sh12:19:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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