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2026-01-14 - 08:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Jan 14, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214672940,0sleep00-21swapper/000:12:000
94092790,0sleep00-21swapper/000:27:260
140832780,0sleep10-21swapper/123:44:001
207302770,0sleep220695-21sshd22:19:432
34022590,0sleep20-21swapper/200:13:142
50872580,0sleep20-21swapper/221:50:192
324142570,0sleep20-21swapper/221:32:372
222472570,1sleep0710-21NetworkManager23:41:550
290762560,1sleep329070-21sshd23:06:543
240632550,0sleep00-21swapper/000:39:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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