You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-12 - 23:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Jan 12, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
43972780,0sleep04291-21sshd11:54:300
180202600,0sleep20-21swapper/209:35:302
164232580,0sleep10-21swapper/112:17:221
36702550,1sleep33665-21lspci11:13:313
298492550,0sleep329847-21sshd09:13:203
316062530,0sleep0111rcuc/011:43:090
31342530,0sleep20-21swapper/210:54:282
122572520,1sleep012254-21sshd09:59:060
325952510,0sleep30-21swapper/311:56:483
199042510,0sleep20-21swapper/209:22:402
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional