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2026-04-05 - 11:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun Apr 05, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246242870,0sleep024610-21sshd22:52:230
130302700,1sleep113022-21sshd22:54:121
227012630,0sleep20-21swapper/222:52:132
144032610,1sleep114396-21sshd22:40:221
50872600,1sleep2674-21dbus-daemon00:27:492
36932590,0sleep20-21swapper/200:08:232
308092580,1sleep0674-21dbus-daemon21:16:380
44082560,0sleep30-21swapper/323:43:323
56342540,0sleep20-21swapper/200:11:152
294852540,0sleep10-21swapper/122:55:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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