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2026-05-13 - 14:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed May 13, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
80772970,2sleep3356199cyclictest11:42:443
42092950,2sleep2356099cyclictest10:44:002
27522920,1sleep1355999cyclictest09:59:371
27522920,1sleep1355999cyclictest09:59:371
244002770,0sleep20-21swapper/211:46:562
231592620,0sleep20-21swapper/210:09:392
5882570,1sleep3674-21dbus-daemon10:43:413
117872560,0sleep2311rcuc/211:23:332
108722560,0sleep010864-21sshd09:35:200
134842540,0sleep30-21swapper/312:11:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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