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2026-01-29 - 20:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu Jan 29, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
291482880,0sleep029149-21sshd12:33:460
263202570,0sleep00-21swapper/012:03:170
193922560,0sleep10-21swapper/112:16:251
126522560,0sleep20-21swapper/211:45:332
93942530,2sleep02196399cyclictest09:42:000
228072530,2sleep322804-21lspci12:16:433
227412530,1sleep1674-21dbus-daemon11:54:461
83732520,0sleep10-21swapper/111:59:021
300452520,0sleep00-21swapper/011:03:110
17612520,0sleep30-21swapper/310:30:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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