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2026-02-07 - 12:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Feb 07, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1775521070,0sleep30-21swapper/300:30:313
1436421020,0sleep114352-21sshd23:46:231
244002780,0sleep00-21swapper/022:12:450
175132750,0sleep00-21swapper/022:41:010
315512640,0sleep20-21swapper/222:23:092
207312570,0sleep30-21swapper/322:52:133
41722560,0sleep20-21swapper/222:39:592
256812550,1sleep0699-21gdbus00:20:140
49532540,2sleep0931599cyclictest00:37:450
81072530,1sleep38101-21sshd23:15:493
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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