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2026-01-13 - 20:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue Jan 13, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38052750,0sleep30-21swapper/311:04:093
274582730,2sleep21167699cyclictest10:55:122
274582730,2sleep21167699cyclictest10:55:122
161142570,0sleep10-21swapper/109:40:211
44982540,0sleep10-21swapper/109:39:121
317092540,1sleep031710-21kworker/u8:010:55:300
317092540,1sleep031710-21kworker/u8:010:55:290
272332530,0sleep0111rcuc/012:17:170
240312520,0sleep30-21swapper/309:55:013
224152520,0sleep00-21swapper/009:47:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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