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2026-05-28 - 00:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed May 27, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21572770,0sleep20-21swapper/211:50:162
325712720,1sleep1241ktimersoftd/109:25:521
34112660,0sleep20-21swapper/212:07:152
236582590,0sleep2311rcuc/211:43:472
102302580,0sleep1241ktimersoftd/111:31:211
269702570,0sleep10-21swapper/111:46:511
163622550,0sleep10-21swapper/110:19:351
146542550,1sleep214652-21sshd10:33:182
273532540,0sleep00-21swapper/010:51:020
23872540,0sleep1231rcuc/111:00:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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