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2026-05-18 - 19:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon May 18, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
46382660,0sleep10-21swapper/111:55:311
67242600,1sleep36718-21sshd10:12:273
125642590,1sleep0674-21dbus-daemon11:56:140
170042580,1sleep017002-21sshd09:45:330
236872570,0sleep10-21swapper/112:38:531
114562560,0sleep211458-21grepconf.sh11:28:092
76702550,0sleep30-21swapper/311:22:133
109152550,0sleep00-21swapper/010:46:090
94302540,0sleep2311rcuc/210:29:242
31302530,0sleep20-21swapper/209:47:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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