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2025-11-23 - 06:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun Nov 23, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
195452980,0sleep02720699cyclictest22:37:160
315152920,2sleep12721099cyclictest00:19:191
173292840,2sleep12721099cyclictest23:09:221
298752720,0sleep30-21swapper/323:00:503
276212670,0sleep227576-21sshd00:25:362
276212670,0sleep227576-21sshd00:25:362
216232660,2sleep2321ktimersoftd/200:38:422
66242650,0sleep20-21swapper/223:56:292
302212630,0sleep10-21swapper/100:22:301
209352620,0sleep00-21swapper/023:28:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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