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2025-10-14 - 02:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue Oct 14, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1551321000,0sleep10-21swapper/123:54:501
221662970,0sleep30-21swapper/300:15:153
276432780,1sleep027637-21lspci23:52:450
243762680,1sleep324379-21grep23:36:063
262112670,1sleep326108-21sshd23:10:103
179862590,0sleep10-21swapper/122:13:491
325892580,0sleep1231rcuc/121:13:401
186242560,0sleep10-21swapper/123:12:361
15412560,0sleep30-21swapper/322:38:093
260492550,2sleep11521099cyclictest23:46:041
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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