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2026-01-11 - 00:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Jan 10, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
223132960,0sleep022312-21grep11:19:250
223132960,0sleep022312-21grep11:19:240
155802960,0sleep10-21swapper/112:38:211
94022920,0sleep3401ktimersoftd/310:42:473
85372830,0sleep18538-21sshd12:04:521
205502710,0sleep20-21swapper/211:24:442
175652580,0sleep20-21swapper/210:15:032
136752570,0sleep20-21swapper/212:32:412
243922560,2sleep3677799cyclictest11:46:553
242072540,1sleep024203-21sshd12:06:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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