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2026-02-22 - 15:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun Feb 22, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121942790,0sleep30-21swapper/311:10:543
129972580,0sleep10-21swapper/110:35:471
295762560,1sleep0101ktimersoftd/009:50:010
28532560,0sleep10-21swapper/111:01:591
174642550,1sleep117463-21sshd09:59:041
97062520,2sleep2609999cyclictest10:14:262
189002520,1sleep018895-21sshd11:47:040
183962520,0sleep20-21swapper/210:28:482
63962510,0sleep20-21swapper/212:09:042
31372510,2sleep3610299cyclictest10:07:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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