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2026-01-15 - 09:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu Jan 15, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3194721240,0sleep00-21swapper/021:59:070
91452930,0sleep20-21swapper/222:59:082
91782900,0sleep3391rcuc/323:23:533
172852540,0sleep00-21swapper/022:00:550
44782530,0sleep00-21swapper/023:26:100
16582530,0sleep00-21swapper/023:03:590
131402530,0sleep20-21swapper/200:38:342
316292520,0sleep30-21swapper/321:10:113
271322510,0sleep30-21swapper/323:19:573
205392510,1sleep220542-21latency_hist21:25:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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