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2026-01-05 - 20:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Jan 05, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3041821040,1sleep02347099cyclictest10:31:260
38202590,1sleep3674-21dbus-daemon12:13:273
142352580,0sleep00-21swapper/010:52:290
246722560,0sleep20-21swapper/212:15:142
61042550,1sleep16106-21bash09:38:011
245582550,0sleep20-21swapper/212:20:522
18402540,0sleep30-21swapper/312:24:373
289432530,1sleep2311rcuc/211:19:232
25292530,0sleep00-21swapper/010:02:550
23162530,0sleep00-21swapper/010:06:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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