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2026-05-09 - 13:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat May 09, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
57621270,0sleep10-21swapper/110:46:191
1194521220,0sleep10-21swapper/112:10:301
1194521220,0sleep10-21swapper/112:10:301
2464921070,0sleep124595-21sshd10:23:271
59832950,2sleep1560999cyclictest10:13:341
120602950,0sleep2562199cyclictest12:21:242
115632950,2sleep2562199cyclictest10:47:162
77042770,1sleep2674-21dbus-daemon11:14:472
291622770,0sleep10-21swapper/109:45:061
266202620,0sleep10-21swapper/110:40:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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