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2026-01-28 - 06:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Jan 28, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1459921070,2sleep33047899cyclictest00:15:383
96762840,0sleep20-21swapper/223:31:112
130232780,0sleep30-21swapper/323:17:423
173002740,0sleep30-21swapper/322:16:503
56922590,1sleep3401ktimersoftd/300:28:443
86122580,1sleep08605-21bash21:44:430
170252580,1sleep3391rcuc/323:07:013
269242570,0sleep30-21swapper/322:32:053
193882570,0sleep20-21swapper/221:45:462
163242570,0sleep00-21swapper/023:01:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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