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2026-05-15 - 16:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri May 15, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2920021060,0sleep30-21swapper/311:48:343
221112980,0sleep00-21swapper/009:57:120
252902700,0sleep00-21swapper/009:12:340
47722620,0sleep30-21swapper/309:47:243
146982600,0sleep20-21swapper/210:04:552
303452590,17sleep375750irq/24-eno1-rx-11:56:553
207582580,0sleep20-21swapper/209:59:542
315442560,0sleep20-21swapper/209:38:392
245112550,1sleep024508-21sshd10:19:350
198942550,0sleep10-21swapper/110:49:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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