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2025-12-20 - 23:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Dec 20, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2027821030,0sleep20-21swapper/211:09:422
261732900,0sleep10-21swapper/110:48:391
195412830,1sleep319539-21lspci10:21:043
30432630,1sleep019295-1kworker/0:1H12:23:450
326812580,0sleep30-21swapper/309:55:133
65462540,0sleep0111rcuc/012:26:420
252692540,0sleep20-21swapper/212:25:332
234922540,1sleep10-21swapper/110:59:121
212882540,0sleep30-21swapper/311:52:523
134252540,0sleep2311rcuc/210:52:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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