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2025-12-07 - 09:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun Dec 07, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
200632990,2sleep158499cyclictest22:10:461
264272920,0sleep20-21swapper/200:15:322
26502750,1sleep10-21swapper/123:29:571
223032740,0sleep00-21swapper/021:43:510
3762720,0sleep30-21swapper/321:55:143
77202650,0sleep30-21swapper/300:03:473
39282650,0sleep13917-21lspci21:45:151
201682640,0sleep20-21swapper/200:01:422
21302620,0sleep00-21swapper/023:56:360
166872620,0sleep20-21swapper/221:33:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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