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2026-01-28 - 19:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Jan 28, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290712630,0sleep10-21swapper/109:53:581
43432560,0sleep20-21swapper/211:49:032
177962550,0sleep10-21swapper/110:52:471
68722540,1sleep16871-21systemd-cgroups12:30:231
272192540,0sleep10-21swapper/111:56:221
38172530,1sleep1231rcuc/110:24:311
266622530,0sleep3401ktimersoftd/311:12:403
30132520,0sleep2311rcuc/210:08:212
241622520,0sleep20-21swapper/211:20:352
127982520,0sleep30-21swapper/311:27:543
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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