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2025-12-08 - 12:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Dec 08, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214252990,0sleep30-21swapper/321:27:483
165812820,1sleep0101ktimersoftd/000:32:250
39662770,0sleep00-21swapper/021:57:570
187102630,0sleep2311rcuc/222:18:382
105992610,0sleep20-21swapper/222:30:232
19542600,0sleep10-21swapper/100:34:351
70042580,0sleep00-21swapper/023:05:180
163982570,1sleep016391-21lspci21:36:510
246972540,0sleep30-21swapper/322:15:593
33292530,1sleep03328-21sshd22:36:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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