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2025-12-14 - 05:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun Dec 14, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9582990,0sleep30-21swapper/323:04:433
145442790,0sleep20-21swapper/221:27:132
113332770,0sleep011301-21sshd00:37:350
21952750,2sleep02524599cyclictest22:41:490
115952740,2sleep32526699cyclictest22:51:173
168592710,0sleep00-21swapper/000:23:540
263142580,0sleep10-21swapper/100:21:541
177682540,0sleep00-21swapper/022:22:580
59622530,0sleep10-21swapper/123:05:091
13222530,0sleep30-21swapper/323:30:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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