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2026-05-29 - 17:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu May 28, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
223812800,1sleep396499cyclictest00:15:323
119552780,0sleep11-21systemd00:20:151
59632570,0sleep00-21swapper/021:24:140
283912560,2sleep396499cyclictest22:07:473
263262550,1sleep0101ktimersoftd/021:42:370
140702540,0sleep00-21swapper/000:25:590
43732530,0sleep30-21swapper/322:25:143
269232530,0sleep10-21swapper/122:21:351
295772520,1sleep0101ktimersoftd/023:20:220
117712520,0sleep211765-21lspci22:20:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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