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2026-05-06 - 03:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed May 06, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
274702950,2sleep22407099cyclictest22:27:122
225032760,0sleep20-21swapper/221:41:502
225032760,0sleep20-21swapper/221:41:492
93832720,0sleep00-21swapper/023:58:130
223732580,0sleep30-21swapper/322:29:373
146702570,1sleep0674-21dbus-daemon21:19:360
253152540,0sleep1231rcuc/122:41:011
112132530,0sleep10-21swapper/100:04:001
249832520,0sleep00-21swapper/022:24:140
100282520,0sleep20-21swapper/222:34:092
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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