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2025-12-03 - 07:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Dec 03, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2953021010,0sleep20-21swapper/222:11:062
2921221000,0sleep20-21swapper/221:58:152
107112960,0sleep11128999cyclictest22:38:111
87822910,1sleep21129699cyclictest22:34:532
121052900,0sleep20-21swapper/200:02:042
128292890,2sleep21129699cyclictest21:18:072
225392760,2sleep11128999cyclictest00:37:081
25882700,0sleep32586-21lspci21:13:523
195072680,0sleep319505-21sshd21:41:143
109822660,1sleep0101ktimersoftd/023:10:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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