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2026-01-13 - 02:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue Jan 13, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
119852990,0sleep211984-21grepconf.sh23:15:012
283862690,2sleep22022099cyclictest23:49:182
197782610,2sleep02020999cyclictest23:15:350
322732590,1sleep2674-21dbus-daemon21:41:092
77092580,0sleep10-21swapper/123:09:121
24242560,1sleep22022099cyclictest22:09:052
62102540,0sleep10-21swapper/123:20:011
54502540,0sleep20-21swapper/200:14:502
33402520,0sleep10-21swapper/123:52:381
134322520,0sleep00-21swapper/000:26:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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