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2025-12-09 - 14:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue Dec 09, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
153742950,0sleep01695999cyclictest11:46:000
130332930,1sleep213031-21sshd11:35:092
176622830,1sleep2311rcuc/209:51:442
208162650,0sleep30-21swapper/310:24:203
221632630,0sleep00-21swapper/009:19:220
140572600,0sleep30-21swapper/310:34:133
240282580,0sleep30-21swapper/310:55:403
189062580,0sleep10-21swapper/108:30:171
241872570,0sleep10-21swapper/110:31:441
177342550,0sleep10-21swapper/111:28:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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