You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-25 - 18:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun Jan 25, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
199621190,0sleep21994-21lspci12:25:122
270092570,0sleep10-21swapper/111:40:221
15362570,0sleep00-21swapper/011:49:170
80212560,0sleep00-21swapper/010:32:480
34642540,0sleep30-21swapper/310:59:583
311632540,1sleep331161-21sshd09:53:333
227482540,0sleep20-21swapper/211:37:182
107922540,0sleep10-21swapper/112:03:521
125712510,0sleep10-21swapper/110:46:541
113712510,0sleep00-21swapper/010:15:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional