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2026-05-08 - 01:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu May 07, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2777821290,0sleep20-21swapper/210:55:492
3227721250,2sleep01347699cyclictest11:26:390
232482940,0sleep20-21swapper/211:28:412
255612830,0sleep1231rcuc/112:38:061
53622810,2sleep01347699cyclictest10:09:480
157642790,0sleep20-21swapper/212:06:422
284922760,0sleep00-21swapper/011:56:430
178052740,0sleep10-21swapper/112:29:081
226812620,0sleep30-21swapper/310:41:363
163642610,0sleep00-21swapper/010:19:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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