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2026-02-14 - 13:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Feb 14, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
266822810,0sleep20-21swapper/200:38:072
56412730,0sleep00-21swapper/021:28:490
115092580,0sleep00-21swapper/022:15:110
201662570,0sleep10-21swapper/121:48:131
143162560,1sleep21073-21nfsd00:01:112
238202530,0sleep30-21swapper/323:15:063
247862520,0sleep00-21swapper/021:48:440
42172510,1sleep21073-21nfsd23:54:552
256882500,1sleep10-21swapper/122:55:531
214062490,0sleep10-21swapper/100:07:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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