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2026-02-17 - 13:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue Feb 17, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30052910,0sleep10-21swapper/110:32:031
261182750,0sleep00-21swapper/011:49:130
319432570,0sleep00-21swapper/010:58:590
8442550,0sleep20-21swapper/209:29:562
265212550,0sleep20-21swapper/212:16:352
179072540,0sleep10-21swapper/111:32:281
138352520,0sleep013836-21sshd10:37:160
49762510,0sleep10-21swapper/109:13:541
185802510,0sleep20-21swapper/210:17:382
33182500,0sleep30-21swapper/311:03:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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