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2026-05-25 - 10:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon May 25, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
273092890,0sleep127216-21sshd23:00:051
178522760,1sleep09-21ksoftirqd/023:15:510
176512760,2sleep2297399cyclictest22:48:092
204292750,0sleep10-21swapper/122:15:081
295942730,0sleep30-21swapper/322:24:153
145852710,0sleep00-21swapper/000:11:030
39492580,0sleep20-21swapper/221:15:362
273202540,0sleep20-21swapper/223:44:292
224832540,0sleep0111rcuc/000:22:520
121612540,0sleep00-21swapper/023:12:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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