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2025-12-26 - 12:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri Dec 26, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
284802910,0sleep10-21swapper/123:23:381
95932790,0sleep30-21swapper/300:14:233
160892780,0sleep216050-21sshd23:58:232
260082540,1sleep1674-21dbus-daemon23:31:391
92742530,1sleep09262-21sshd22:29:450
30372530,0sleep20-21swapper/200:00:042
282502530,1sleep028212-21sshd00:35:140
256162520,0sleep00-21swapper/021:45:090
172632520,2sleep01187499cyclictest21:54:450
138592520,0sleep30-21swapper/300:09:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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