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2025-12-27 - 13:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Dec 27, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
988321110,1sleep03064599cyclictest10:21:530
269342760,2sleep03064599cyclictest11:51:330
243242630,0sleep00-21swapper/010:53:250
175322600,2sleep23065999cyclictest10:50:082
205702560,0sleep1231rcuc/110:42:061
64242540,0sleep30-21swapper/312:17:313
222942540,0sleep222235-21sshd11:18:022
146472540,1sleep014644-21sshd11:06:200
281472530,1sleep3674-21dbus-daemon11:15:443
12042510,0sleep00-21swapper/012:30:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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