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2026-05-07 - 12:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu May 07, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
77082780,2sleep22548299cyclictest22:33:492
77082780,2sleep22548299cyclictest22:33:492
71082640,0sleep20-21swapper/223:47:072
71082640,0sleep20-21swapper/223:47:072
48822560,0sleep10-21swapper/122:23:471
123522550,1sleep312350-21lspci21:37:023
123522550,1sleep312350-21lspci21:37:023
39132540,0sleep10-21swapper/122:36:361
234432540,0sleep10-21swapper/122:28:511
100652540,0sleep10-21swapper/121:55:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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