You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-24 - 16:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Jan 24, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
186092920,1sleep12854799cyclictest11:45:081
134272860,2sleep22855199cyclictest10:44:222
275362690,1sleep227538-21lspci10:56:262
215082630,0sleep20-21swapper/210:16:572
232872610,1sleep123281-21sshd09:56:261
272892590,2sleep32855799cyclictest12:13:183
247032590,2sleep12854799cyclictest11:04:311
50452560,0sleep20-21swapper/209:33:522
260752560,0sleep00-21swapper/011:59:300
9752550,0sleep0971-21sshd09:47:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional