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2026-04-19 - 05:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun Apr 19, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
240982760,0sleep024084-21sshd21:20:560
270282550,0sleep30-21swapper/323:20:193
20672550,0sleep10-21swapper/123:03:551
30762540,0sleep10-21swapper/100:21:331
151542540,1sleep00-21swapper/000:29:010
128462520,0sleep10-21swapper/123:05:031
116882520,0sleep111652-21sshd00:25:251
305612500,0sleep10-21swapper/123:53:081
14082500,0sleep30-21swapper/322:05:173
132452500,0sleep20-21swapper/200:31:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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