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2025-12-06 - 08:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Dec 06, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
444421060,0sleep10-21swapper/100:22:191
1871521000,2sleep02552399cyclictest22:43:450
76852970,0sleep30-21swapper/323:45:523
92442960,0sleep30-21swapper/321:28:543
220012790,0sleep10-21swapper/123:50:311
229662680,0sleep10-21swapper/100:00:281
80172630,0sleep10-21swapper/122:59:121
129972620,1sleep312995-21lspci23:43:123
270942590,1sleep127087-21sshd23:44:431
262672590,0sleep20-21swapper/221:36:502
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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