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2026-01-19 - 02:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Jan 19, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
144772830,1sleep1241ktimersoftd/123:01:231
298362810,1sleep0674-21dbus-daemon21:57:330
137062750,1sleep12747699cyclictest00:15:371
295222740,0sleep1231rcuc/121:24:101
325812560,0sleep00-21swapper/000:31:020
221842560,0sleep00-21swapper/022:03:420
221842560,0sleep00-21swapper/022:03:420
307462540,4sleep030742-21lspci23:57:490
59212530,0sleep00-21swapper/000:20:280
279142520,0sleep10-21swapper/100:05:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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