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2026-02-03 - 09:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue Feb 03, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1654521050,1sleep0622-13audispd22:28:070
2580721040,0sleep225806-21sshd00:12:582
848521010,0sleep18482-21bash00:30:411
148912990,0sleep00-21swapper/023:33:400
295682920,2sleep182499cyclictest22:07:201
139482700,2sleep081799cyclictest22:52:260
144932630,0sleep20-21swapper/200:09:192
108712630,0sleep30-21swapper/300:09:003
224512610,0sleep10-21swapper/121:10:341
231252600,1sleep10-21swapper/123:50:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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