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2026-05-06 - 23:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed May 06, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
249072560,0sleep00-21swapper/011:30:550
196592560,0sleep0111rcuc/012:30:520
194882560,1sleep3622-13audispd09:35:273
42422540,1sleep24238-21lspci10:32:452
240612540,0sleep30-21swapper/310:34:313
214702540,1sleep121466-21bash11:07:571
67142520,0sleep30-21swapper/312:09:473
274322520,0sleep30-21swapper/311:42:403
241892520,2sleep3968499cyclictest10:23:183
12252520,0sleep30-21swapper/312:20:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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