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2026-03-04 - 16:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Wed Mar 04, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
306212910,0sleep10-21swapper/110:55:491
224002820,0sleep022401-21sshd09:41:220
156292770,0sleep015630-21grep11:35:370
97362740,2sleep31466099cyclictest10:37:403
7392590,0sleep10-21swapper/111:56:211
68832530,1sleep26783-21sshd10:40:122
5602530,0sleep20-21swapper/211:09:482
64032520,0sleep00-21swapper/011:54:070
158542510,0sleep00-21swapper/008:30:100
149312510,0sleep20-21swapper/209:12:342
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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