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2026-05-04 - 18:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon May 04, 2026 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13232980,2sleep32887699cyclictest12:10:523
11662770,1sleep32887699cyclictest11:20:213
12442740,0sleep30-21swapper/309:52:413
171882600,1sleep017183-21sshd11:35:480
300382590,9sleep375750irq/24-eno1-rx-10:24:003
250602550,0sleep325054-21lspci10:03:473
229052540,0sleep30-21swapper/311:36:193
22442540,1sleep02241-21sshd10:44:050
96942530,0sleep20-21swapper/209:43:232
274882530,0sleep10-21swapper/111:05:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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