You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-22 - 05:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Thu Jan 22, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231832950,0sleep00-21swapper/022:59:110
247912940,2sleep13101499cyclictest21:46:131
119352790,0sleep20-21swapper/200:37:342
61542750,1sleep33102499cyclictest00:20:293
253142750,0sleep10-21swapper/100:11:051
308102650,0sleep20-21swapper/200:14:222
304702620,1sleep3401ktimersoftd/323:24:283
253342620,0sleep025332-21grep00:22:090
273242600,0sleep30-21swapper/322:17:473
62912590,0sleep30-21swapper/322:08:343
110652580,0sleep30-21swapper/321:44:513
252072550,0sleep10-21swapper/122:23:381
50222510,0sleep00-21swapper/023:27:530
287882510,10sleep375750irq/24-eno1-rx-00:03:093
82832500,1sleep18284-21grep00:31:431
62582500,0sleep00-21swapper/021:47:440
311852500,0sleep10-21swapper/123:49:381
270082490,0sleep30-21swapper/322:10:423
241502490,0sleep10-21swapper/100:27:351
77212480,0sleep30-21swapper/321:58:173
65362480,0sleep10-21swapper/123:33:391
73682470,0sleep00-21swapper/022:35:460
308992470,0sleep20-21swapper/223:46:462
255202470,2sleep23101999cyclictest00:02:522
224702470,0sleep1231rcuc/122:26:061
143432410,0sleep10-21swapper/123:17:331
182782370,1sleep03100799cyclictest23:51:130
13302370,1sleep09-21ksoftirqd/022:32:350
3075623214,14sleep10-21swapper/119:08:021
131832310,0sleep31-21systemd00:15:313
306712297,7sleep00-21swapper/019:06:560
204042260,2sleep23101999cyclictest00:16:102
3063422210,7sleep30-21swapper/319:06:273
3057222210,7sleep20-21swapper/219:05:432
188602220,1sleep318854-21lspci23:06:583
287492200,0sleep30-21swapper/300:11:223
241152200,0sleep00-21swapper/023:10:110
110522180,0sleep30-21swapper/323:25:283
78612170,0sleep00-21swapper/021:58:180
3762170,0sleep00-21swapper/000:03:300
280762170,0sleep228071-21lspci22:14:262
149732160,0sleep00-21swapper/000:32:180
256332150,0sleep00-21swapper/023:18:320
122332150,0sleep30-21swapper/323:36:543
3102499140,2cyclictest6261-21sshd21:33:543
3101999140,12cyclictest24864-21sshd23:04:482
28472140,0sleep20-21swapper/223:41:372
264322140,0sleep20-21swapper/200:25:032
255102140,0sleep1231rcuc/121:11:321
185932140,0sleep20-21swapper/222:06:212
129532140,0sleep20-21swapper/222:55:272
12422140,0sleep00-21swapper/021:36:470
112122140,1sleep011209-21lspci22:52:370
31019991311,1cyclictest26782-21sshd22:20:582
31014991312,1cyclictest21684-21kworker/1:200:38:461
31014991312,0cyclictest31366-21kworker/1:323:44:511
31014991312,0cyclictest2627-21kworker/1:123:37:451
31014991312,0cyclictest14849-21kworker/1:121:43:211
31014991312,0cyclictest14849-21kworker/1:121:39:431
31014991311,1cyclictest22488-21sshd00:21:531
31024991210,1cyclictest14923-21lspci23:59:153
3102499120,1cyclictest20319-21sshd22:42:253
31019991211,0cyclictest0-21swapper/200:23:392
31019991210,1cyclictest15310-21sshd22:52:582
31019991210,1cyclictest1181-21bash23:30:192
31019991210,1cyclictest0-21swapper/223:55:292
3101999120,11cyclictest33-21ksoftirqd/222:41:492
3101999120,11cyclictest0-21swapper/222:30:182
31014991211,1cyclictest6370-21kworker/1:022:30:191
31014991211,0cyclictest2244-21kworker/1:100:05:491
31014991210,1cyclictest20196-21id23:56:531
31014991210,1cyclictest16353-21kworker/1:122:11:151
31014991210,1cyclictest14452-21lspci21:15:151
3101499120,11cyclictest0-21swapper/123:03:431
31007991210,1cyclictest0-21swapper/021:10:510
3100799120,1cyclictest21608-21sshd21:32:010
3100799120,1cyclictest0-21swapper/000:16:420
3100799120,11cyclictest674-21dbus-daemon00:10:020
3100799120,11cyclictest5974-21lspci21:19:320
3100799120,11cyclictest17334-21bash21:52:220
3102499119,1cyclictest674-21dbus-daemon22:58:143
3102499119,1cyclictest22293-21lspci22:53:343
31024991110,0cyclictest0-21swapper/323:14:443
3102499110,10cyclictest0-21swapper/319:20:143
3101999119,1cyclictest2414-21bash23:52:382
3101999119,1cyclictest15076-21sshd23:23:082
31019991110,0cyclictest0-21swapper/223:35:582
31019991110,0cyclictest0-21swapper/221:25:292
3101999110,1cyclictest2510-21lspci00:06:232
3101999110,10cyclictest0-21swapper/223:11:582
3101999110,10cyclictest0-21swapper/221:48:082
31014991110,0cyclictest3946-21kworker/1:022:52:311
31014991110,0cyclictest14930-21kworker/1:422:57:431
3101499110,1cyclictest25880-21bash22:42:531
3101499110,10cyclictest0-21swapper/123:10:531
3101499110,10cyclictest0-21swapper/121:55:331
3101499110,10cyclictest0-21swapper/100:02:331
3101499110,0cyclictest0-21swapper/100:18:431
3100799119,1cyclictest27908-21grep22:17:520
31007991110,0cyclictest0-21swapper/021:05:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional