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2026-04-20 - 17:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Mon Apr 20, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214112960,2sleep21372299cyclictest09:28:202
162982910,0sleep10-21swapper/112:01:281
214022770,1sleep021387-21sshd10:52:370
287132590,0sleep028706-21sshd12:24:460
38512580,0sleep30-21swapper/309:47:363
102372560,0sleep20-21swapper/211:33:172
227972550,0sleep30-21swapper/311:56:293
25562540,1sleep22554-21lspci10:37:092
15532540,0sleep20-21swapper/212:11:182
134222540,0sleep30-21swapper/310:32:343
239022530,0sleep20-21swapper/211:15:022
239022530,0sleep20-21swapper/211:15:022
205432530,0sleep30-21swapper/310:55:173
171822530,0sleep00-21swapper/012:12:400
72382520,0sleep20-21swapper/212:33:572
314862520,0sleep00-21swapper/011:46:090
300142520,2sleep31372799cyclictest12:24:533
310862510,0sleep20-21swapper/210:42:222
113652500,0sleep10-21swapper/111:22:141
113652500,0sleep10-21swapper/111:22:141
235342490,0sleep20-21swapper/210:19:392
191262490,0sleep00-21swapper/012:26:380
182952490,0sleep30-21swapper/311:31:103
33502480,0sleep00-21swapper/010:15:080
206112480,1sleep220609-21sshd11:45:142
177012440,0sleep00-21swapper/010:55:060
158942410,2sleep31372799cyclictest09:31:343
133962298,7sleep30-21swapper/307:07:193
133462299,6sleep20-21swapper/207:06:412
1328122716,7sleep10-21swapper/107:05:531
326042210,0sleep30-21swapper/312:16:443
132702219,7sleep00-21swapper/007:05:440
275402190,0sleep30-21swapper/310:25:253
13722991716,0cyclictest12609-21lspci10:54:412
107942170,0sleep010782-21cp12:09:240
297252160,2sleep3674-21dbus-daemon11:21:003
297252160,2sleep3674-21dbus-daemon11:21:003
253172160,0sleep20-21swapper/209:20:512
13722991514,0cyclictest321ktimersoftd/211:01:182
13710991514,0cyclictest19744-21kworker/0:409:18:140
103622150,0sleep20-21swapper/209:50:512
101932150,1sleep0620-17auditd10:24:020
36492140,0sleep00-21swapper/012:03:110
137922140,0sleep10-21swapper/110:54:471
1372799142,1cyclictest10753-21sshd11:13:543
13722991413,0cyclictest321ktimersoftd/211:28:542
13722991413,0cyclictest29225-21lspci09:47:002
13717991412,1cyclictest20129-21sshd11:28:371
13710991412,1cyclictest24701-21kworker/0:011:24:260
13710991412,1cyclictest24701-21kworker/0:011:24:250
95942130,0sleep30-21swapper/311:27:413
76902130,0sleep20-21swapper/210:59:482
304792130,0sleep030477-21sshd11:37:470
260372130,0sleep10-21swapper/110:03:161
13722991313,0cyclictest321ktimersoftd/207:24:582
1372299130,1cyclictest22956-21lspci10:05:412
13710991311,1cyclictest31633-21kworker/0:109:25:000
242232120,0sleep2311rcuc/209:57:362
160732120,0sleep10-21swapper/110:49:261
1372299121,9cyclictest31898-21sshd12:25:012
1372299121,1cyclictest33-21ksoftirqd/210:30:002
13722991211,0cyclictest321ktimersoftd/212:02:022
13722991211,0cyclictest321ktimersoftd/210:22:092
13722991211,0cyclictest29338-21lspci12:38:372
13722991211,0cyclictest15221-21lspci09:11:512
1372299120,1cyclictest29979-21gdbus11:53:412
1372299120,1cyclictest26999-21lspci10:03:212
1372299120,0cyclictest0-21swapper/212:16:212
13717991210,1cyclictest19639-21ntp_states08:40:171
13717991210,1cyclictest10611-21lspci10:18:311
13717991210,1cyclictest0-21swapper/109:26:171
1371799120,1cyclictest13348-21sshd09:15:271
1371799120,0cyclictest0-21swapper/111:58:171
13710991211,0cyclictest25169-21kworker/0:511:33:060
13710991211,0cyclictest18137-21kworker/0:109:46:080
13710991211,0cyclictest13968-21lspci11:14:110
13710991210,1cyclictest27695-21sshd11:43:050
13710991210,1cyclictest1-21systemd09:41:450
13710991210,1cyclictest0-21swapper/010:09:250
1371099120,11cyclictest2894-21sshd10:01:150
1372799119,1cyclictest0-21swapper/310:38:543
13727991110,0cyclictest0-21swapper/309:56:043
13727991110,0cyclictest0-21swapper/309:18:143
1372799110,10cyclictest0-21swapper/312:04:343
1372799110,10cyclictest0-21swapper/309:26:043
1372299119,1cyclictest33-21ksoftirqd/209:44:432
1372299111,1cyclictest131rcu_sched11:39:102
1372299111,1cyclictest131rcu_sched11:10:282
13722991110,0cyclictest0-21swapper/209:18:512
1372299110,1cyclictest13371-21lspci11:22:252
1372299110,1cyclictest13371-21lspci11:22:252
1372299110,0cyclictest0-21swapper/212:05:112
1371799119,1cyclictest9549-21sshd11:35:571
1371799119,1cyclictest674-21dbus-daemon12:24:571
1371799119,1cyclictest22524-21bash10:44:271
1371799119,1cyclictest0-21swapper/110:23:271
1371799110,10cyclictest9124-21sshd12:14:471
1371799110,10cyclictest0-21swapper/112:05:571
1371799110,0cyclictest0-21swapper/110:33:471
1371799110,0cyclictest0-21swapper/110:06:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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