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2025-12-14 - 07:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Sun Dec 14, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9582990,0sleep30-21swapper/323:04:433
145442790,0sleep20-21swapper/221:27:132
113332770,0sleep011301-21sshd00:37:350
21952750,2sleep02524599cyclictest22:41:490
115952740,2sleep32526699cyclictest22:51:173
168592710,0sleep00-21swapper/000:23:540
263142580,0sleep10-21swapper/100:21:541
177682540,0sleep00-21swapper/022:22:580
59622530,0sleep10-21swapper/123:05:091
13222530,0sleep30-21swapper/323:30:413
243722520,0sleep10-21swapper/122:37:561
248762510,1sleep324872-21lspci23:12:323
125782510,1sleep3401ktimersoftd/321:15:013
92532500,0sleep29211-21sshd23:31:252
247012500,0sleep10-21swapper/100:38:471
197822500,2sleep12525299cyclictest23:43:541
139412500,0sleep3391rcuc/322:09:073
6052490,0sleep0606-21bash23:45:050
36422490,0sleep10-21swapper/119:35:001
299952490,0sleep129996-21grep00:25:021
220202490,1sleep122019-21bash23:52:431
52612480,0sleep00-21swapper/000:34:150
248302480,0sleep024825-21sshd22:55:180
248302480,0sleep024825-21sshd22:55:170
202552480,0sleep20-21swapper/200:24:122
115482480,0sleep10-21swapper/122:54:061
63792470,0sleep10-21swapper/121:20:151
320862470,1sleep2311rcuc/200:08:022
297172470,0sleep1241ktimersoftd/123:18:461
244432470,0sleep224436-21sshd23:06:492
80412460,0sleep20-21swapper/219:46:532
33222460,0sleep00-21swapper/022:04:030
276992460,0sleep00-21swapper/021:55:310
241012400,0sleep00-21swapper/021:51:180
215232370,0sleep00-21swapper/021:35:430
2506023110,7sleep20-21swapper/219:09:112
233972237,11sleep30-21swapper/319:05:523
2345322211,7sleep00-21swapper/019:06:330
2333322210,7sleep10-21swapper/119:05:021
105302170,0sleep10-21swapper/123:48:491
219262160,0sleep0101ktimersoftd/023:29:380
51632150,0sleep15164-21tty21:52:481
317602150,1sleep031761-21sshd23:18:570
302082150,0sleep20-21swapper/223:10:092
300982150,0sleep30-21swapper/321:44:203
252912150,1sleep3401ktimersoftd/322:14:163
25245991514,0cyclictest26387-21lspci00:13:170
213752150,0sleep20-21swapper/200:18:352
127452150,0sleep3391rcuc/323:25:573
94292140,0sleep00-21swapper/021:20:540
92852140,0sleep10-21swapper/122:16:151
25252991413,0cyclictest0-21swapper/121:25:191
209542140,0sleep30-21swapper/323:52:373
199492140,0sleep00-21swapper/022:13:360
157302140,0sleep00-21swapper/022:16:580
146782140,0sleep10-21swapper/100:06:321
114212140,0sleep30-21swapper/321:53:343
296012130,0sleep329599-21sshd23:24:323
25245991313,0cyclictest32550irq/27-ahci[00022:05:300
25245991312,0cyclictest6067-21lspci23:51:210
2524599130,12cyclictest623-17sedispatch23:32:450
222352130,0sleep10-21swapper/121:35:491
204952130,0sleep00-21swapper/022:49:100
14642130,0sleep10-21swapper/122:21:341
57682120,0sleep30-21swapper/322:30:343
25266991210,1cyclictest0-21swapper/323:59:223
25266991210,1cyclictest0-21swapper/321:35:533
2526699120,1cyclictest23765-21sshd22:55:133
2526699120,1cyclictest23765-21sshd22:55:123
2526699120,11cyclictest9332-21sed19:47:023
25258991210,1cyclictest6581-21sshd22:00:402
25258991210,1cyclictest30996-21sshd21:05:292
25258991210,1cyclictest23218-21bash22:55:102
25258991210,1cyclictest23218-21bash22:55:092
2525899120,11cyclictest0-21swapper/222:50:192
25252991210,1cyclictest0-21swapper/100:34:191
2525299120,11cyclictest29460-21lspci21:40:291
25245991211,0cyclictest844-21lspci23:13:160
25245991211,0cyclictest30816-21lspci21:29:130
2526699119,1cyclictest0-21swapper/322:25:133
25266991110,0cyclictest0-21swapper/322:15:333
2526699110,10cyclictest13777-21lspci21:31:023
2526699110,10cyclictest10072-21bash21:21:033
2526699110,10cyclictest0-21swapper/321:45:533
2525899119,1cyclictest0-21swapper/222:45:092
2525899119,1cyclictest0-21swapper/221:15:292
25258991110,0cyclictest0-21swapper/223:54:302
25258991110,0cyclictest0-21swapper/222:25:302
25258991110,0cyclictest0-21swapper/221:30:392
2525899110,10cyclictest0-21swapper/222:35:292
2525899110,10cyclictest0-21swapper/220:50:002
2525899110,10cyclictest0-21swapper/200:04:292
2525899110,0cyclictest0-21swapper/221:55:492
2525899110,0cyclictest0-21swapper/221:00:002
2525299119,1cyclictest0-21swapper/122:59:491
2525299119,1cyclictest0-21swapper/122:59:481
25252991110,0cyclictest0-21swapper/122:40:091
25252991110,0cyclictest0-21swapper/121:45:181
2525299110,10cyclictest0-21swapper/100:19:291
2524599119,1cyclictest0-21swapper/022:27:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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