You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-26 - 07:13
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Thu Mar 26, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3046721080,0sleep030466-21bash22:59:460
115912810,0sleep00-21swapper/022:00:420
246892580,1sleep324602-21sshd22:15:273
172122580,0sleep20-21swapper/200:17:542
17132560,0sleep10-21swapper/123:57:281
191312550,0sleep20-21swapper/223:31:332
140812550,0sleep30-21swapper/320:10:123
155132540,0sleep00-21swapper/000:09:350
131282540,0sleep10-21swapper/122:50:051
290102530,1sleep129011-21bash23:32:241
254192530,0sleep00-21swapper/022:31:580
34902520,0sleep00-21swapper/021:49:120
293832520,0sleep30-21swapper/321:48:403
201562520,1sleep30-21swapper/319:05:173
209592510,1sleep020951-21bash23:42:400
187732510,1sleep01-21systemd23:20:330
81382500,1sleep21-21systemd00:33:332
246572500,0sleep30-21swapper/323:01:573
20372500,1sleep12034-21sshd23:35:321
186782500,0sleep00-21swapper/021:26:540
236152490,0sleep30-21swapper/322:01:463
217172490,0sleep221721-21bash21:42:332
2071724937,7sleep00-21swapper/019:08:240
256462470,1sleep325644-21lspci23:18:283
2072123928,6sleep20-21swapper/219:08:262
267302360,2sleep32097299cyclictest00:26:533
230672350,0sleep30-21swapper/323:48:193
37802340,0sleep0111rcuc/021:43:480
204992299,7sleep10-21swapper/119:05:361
127152220,0sleep00-21swapper/023:28:180
265782200,0sleep10-21swapper/120:40:131
41832180,0sleep00-21swapper/000:25:010
28122180,0sleep20-21swapper/222:51:562
236682180,0sleep30-21swapper/300:37:343
226482170,1sleep1674-21dbus-daemon23:48:171
2096899170,1cyclictest1-21systemd21:16:002
2097299162,1cyclictest674-21dbus-daemon21:28:283
170222160,0sleep30-21swapper/322:58:373
303722150,0sleep330370-21sshd00:05:193
2096399150,14cyclictest0-21swapper/122:23:051
113192150,1sleep2311rcuc/221:47:062
78662140,1sleep3391rcuc/323:33:213
319602140,1sleep131958-21lspci21:59:471
303022140,0sleep10-21swapper/122:18:461
20972991412,1cyclictest674-21dbus-daemon23:53:083
9972130,0sleep30-21swapper/321:38:063
37592130,0sleep13749-21sshd21:17:251
34192130,0sleep10-21swapper/119:45:011
269952130,0sleep1241ktimersoftd/121:43:001
20972991311,1cyclictest0-21swapper/323:59:483
20968991311,1cyclictest32406-21systemd-cgroups22:02:312
2096899130,1cyclictest15137-21sshd23:36:412
20962991311,1cyclictest26101-21lspci23:54:040
157012130,0sleep10-21swapper/121:33:551
15642130,0sleep30-21swapper/321:51:443
50832120,0sleep10-21swapper/122:08:241
2097299120,11cyclictest0-21swapper/322:54:093
2097299120,11cyclictest0-21swapper/322:37:483
20968991210,1cyclictest674-21dbus-daemon22:14:102
2096899120,1cyclictest1-21systemd22:59:512
2096899120,11cyclictest0-21swapper/223:14:412
2096399120,11cyclictest27971-21sshd22:56:451
2096399120,0cyclictest0-21swapper/121:05:151
2096299120,11cyclictest31455-21sshd23:46:160
220112110,0sleep2311rcuc/222:07:052
20972991110,0cyclictest6317-21lspci22:27:393
20972991110,0cyclictest0-21swapper/300:23:283
20972991110,0cyclictest0-21swapper/300:14:183
2097299110,10cyclictest0-21swapper/322:06:283
2096899119,1cyclictest393-21sshd22:16:102
2096899119,1cyclictest30834-21lspci21:59:402
2096899119,1cyclictest0-21swapper/223:26:412
20968991110,0cyclictest0-21swapper/223:54:012
20968991110,0cyclictest0-21swapper/200:24:422
2096899110,10cyclictest0-21swapper/200:03:012
2096399119,1cyclictest0-21swapper/123:27:351
2096399119,1cyclictest0-21swapper/100:12:551
20963991110,0cyclictest0-21swapper/121:11:061
2096399110,10cyclictest22772-21sshd21:48:051
2096399110,10cyclictest0-21swapper/123:19:351
2096399110,10cyclictest0-21swapper/121:53:051
2096299119,1cyclictest24978-21sshd23:15:350
2096299119,1cyclictest22989-21sshd22:29:050
2096299119,1cyclictest0-21swapper/021:52:260
2096299111,1cyclictest131rcu_sched22:37:270
20962991110,0cyclictest0-21swapper/023:38:450
20962991110,0cyclictest0-21swapper/022:09:350
2096299110,10cyclictest0-21swapper/022:13:350
2097299109,0cyclictest0-21swapper/322:49:183
2097299109,0cyclictest0-21swapper/321:17:083
2097299100,0cyclictest0-21swapper/323:42:593
2097299100,0cyclictest0-21swapper/321:43:383
2096899109,0cyclictest0-21swapper/223:20:412
2096899109,0cyclictest0-21swapper/223:08:412
2096899109,0cyclictest0-21swapper/221:52:102
2096899109,0cyclictest0-21swapper/200:38:412
2096899100,0cyclictest0-21swapper/223:16:422
2096399109,0cyclictest0-21swapper/123:03:351
2096399109,0cyclictest0-21swapper/122:45:251
2096399109,0cyclictest0-21swapper/122:40:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional