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2026-05-05 - 21:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Tue May 05, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64432940,0sleep10-21swapper/110:03:211
42232760,0sleep00-21swapper/012:39:370
322372590,0sleep20-21swapper/211:51:312
73842580,0sleep10-21swapper/112:28:411
57192540,0sleep00-21swapper/009:16:060
183382540,0sleep00-21swapper/011:07:320
69092530,1sleep16910-21bash09:12:181
280872530,0sleep00-21swapper/009:49:170
272262530,0sleep20-21swapper/209:10:472
10242530,0sleep30-21swapper/309:15:283
280182520,0sleep20-21swapper/210:50:562
240682520,0sleep10-21swapper/111:10:581
42682510,1sleep24241-21sshd11:03:212
227972510,1sleep222792-21sshd12:30:012
63252490,0sleep00-21swapper/011:43:400
22012490,0sleep10-21swapper/112:39:261
202072490,0sleep320204-21lspci10:35:503
129672490,0sleep00-21swapper/010:43:530
112812490,0sleep20-21swapper/210:23:252
151822480,0sleep0111rcuc/010:07:400
49822470,0sleep10-21swapper/112:00:211
21932470,0sleep00-21swapper/009:56:070
148632470,0sleep00-21swapper/012:12:290
144522470,2sleep0156099cyclictest10:29:380
324082460,0sleep20-21swapper/211:14:432
159082460,2sleep3156399cyclictest11:04:263
145752430,0sleep20-21swapper/209:51:042
273882360,2sleep3156399cyclictest09:30:463
16512350,1sleep21649-21lspci12:22:332
33392330,2sleep2156299cyclictest12:05:492
277532320,1sleep2156299cyclictest11:48:242
14242297,7sleep20-21swapper/207:09:442
12152276,7sleep00-21swapper/007:07:090
139222312,7sleep10-21swapper/107:09:231
283032220,1sleep31-21systemd12:13:403
209252220,0sleep30-21swapper/309:58:013
123322211,7sleep30-21swapper/307:07:243
71222190,0sleep00-21swapper/009:35:240
279352170,1sleep127933-21lspci10:18:511
193232170,0sleep10-21swapper/111:53:161
69042150,1sleep30-21swapper/309:50:213
185632150,1sleep218569-21bash10:38:382
16762150,0sleep30-21swapper/312:36:323
135982150,1sleep20-21swapper/211:21:362
107842150,0sleep10-21swapper/108:50:121
267242140,0sleep00-21swapper/012:33:080
69222130,0sleep20-21swapper/211:18:122
296692130,0sleep00-21swapper/011:31:310
174712130,0sleep10-21swapper/110:24:001
171622130,0sleep30-21swapper/307:45:143
156399130,11cyclictest4535-21sshd10:31:353
1562991313,0cyclictest321ktimersoftd/208:57:192
156099132,1cyclictest131rcu_sched12:22:230
116912130,0sleep0101ktimersoftd/011:12:490
314312120,0sleep30-21swapper/311:28:533
308072120,0sleep20-21swapper/211:31:382
286202120,1sleep128607-21sshd10:36:361
156399120,1cyclictest31680-21lspci10:22:143
156399120,11cyclictest75750irq/24-eno1-rx-11:38:253
156399120,11cyclictest0-21swapper/309:45:453
156299125,1cyclictest33-21ksoftirqd/212:01:322
156299123,3cyclictest33-21ksoftirqd/211:08:302
1562991211,0cyclictest321ktimersoftd/212:38:502
1562991210,1cyclictest321ktimersoftd/211:43:072
1562991210,1cyclictest11952-21sshd12:29:052
1562991210,1cyclictest0-21swapper/209:36:452
156299120,11cyclictest12245-21grep10:17:152
156299120,11cyclictest0-21swapper/209:32:042
156199120,11cyclictest0-21swapper/111:23:161
156199120,11cyclictest0-21swapper/109:47:151
1560991210,1cyclictest0-21swapper/010:22:590
156099120,1cyclictest0-21swapper/011:52:090
156099120,1cyclictest0-21swapper/010:36:190
103882120,0sleep20-21swapper/209:28:452
92532110,1sleep11026-21sshd11:15:251
156399110,1cyclictest31884-21sshd10:54:153
156399110,10cyclictest0-21swapper/312:24:153
156399110,10cyclictest0-21swapper/311:45:353
156399110,10cyclictest0-21swapper/310:59:453
156399110,10cyclictest0-21swapper/310:46:343
156399110,10cyclictest0-21swapper/310:12:243
156299111,3cyclictest33-21ksoftirqd/210:07:342
156299110,10cyclictest0-21swapper/212:13:252
156299110,10cyclictest0-21swapper/211:27:042
156299110,10cyclictest0-21swapper/210:11:042
156299110,0cyclictest0-21swapper/210:31:052
156199119,1cyclictest31290-21sshd12:13:561
156199119,1cyclictest0-21swapper/111:40:551
156199119,1cyclictest0-21swapper/110:05:161
1561991110,0cyclictest0-21swapper/110:51:151
1561991110,0cyclictest0-21swapper/110:47:261
156199110,0cyclictest0-21swapper/110:55:561
156199110,0cyclictest0-21swapper/109:52:161
156099119,1cyclictest18548-21sshd09:33:390
156099113,4cyclictest1-21systemd09:05:010
156099110,10cyclictest0-21swapper/012:08:480
156399109,0cyclictest0-21swapper/312:17:143
156299109,0cyclictest12150-21lspci09:20:522
156299109,0cyclictest0-21swapper/210:55:252
156299109,0cyclictest0-21swapper/210:42:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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