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2026-03-08 - 06:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Sun Mar 08, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
234322920,2sleep32464099cyclictest22:15:153
243562910,0sleep00-21swapper/000:17:200
258282780,0sleep00-21swapper/023:22:220
264852670,0sleep00-21swapper/021:37:280
133592610,0sleep00-21swapper/000:10:520
96662580,2sleep32464099cyclictest00:16:033
87122550,1sleep18703-21rm23:18:091
12022550,0sleep30-21swapper/321:30:463
266762540,0sleep30-21swapper/320:30:183
169892530,0sleep00-21swapper/021:57:130
266282520,0sleep00-21swapper/000:06:310
59722510,1sleep15964-21lspci23:45:261
274212510,0sleep30-21swapper/322:38:313
274212510,0sleep30-21swapper/322:38:303
168972510,1sleep0101ktimersoftd/000:27:420
121612510,0sleep10-21swapper/123:32:121
298322500,1sleep129780-21sshd21:24:431
267682500,0sleep20-21swapper/222:32:572
145312500,0sleep30-21swapper/321:43:063
69892470,0sleep00-21swapper/000:04:550
40152470,2sleep32464099cyclictest23:23:163
300632470,0sleep10-21swapper/121:44:491
230912470,0sleep10-21swapper/123:02:511
213852470,2sleep32464099cyclictest22:11:353
115072460,1sleep3401ktimersoftd/323:07:233
41142400,2sleep22463799cyclictest00:29:242
2416923631,3sleep00-21swapper/019:05:370
227342309,7sleep30-21swapper/319:05:063
241602287,7sleep10-21swapper/119:05:291
242732268,6sleep20-21swapper/219:06:542
94242210,0sleep30-21swapper/323:34:463
87382200,0sleep30-21swapper/300:10:273
182382200,0sleep00-21swapper/022:18:130
208522180,0sleep10-21swapper/123:38:281
51812160,0sleep00-21swapper/023:37:080
302042160,0sleep10-21swapper/120:40:141
253792160,0sleep10-21swapper/121:51:091
253532160,0sleep00-21swapper/023:19:360
223302160,0sleep30-21swapper/321:23:213
195982160,0sleep10-21swapper/122:59:521
162262160,2sleep22463799cyclictest23:54:392
2462799150,1cyclictest28692-21bash21:44:400
181392150,0sleep329977-21packagekitd00:05:463
2463199144,3cyclictest25-21ksoftirqd/122:27:411
2463199144,3cyclictest25-21ksoftirqd/122:27:401
24627991410,3cyclictest0-21swapper/023:06:210
225762140,0sleep10-21swapper/121:12:091
16282140,0sleep2311rcuc/200:07:092
9002130,0sleep20-21swapper/222:25:162
9002130,0sleep20-21swapper/222:25:152
24640991311,1cyclictest0-21swapper/322:41:233
2463199135,1cyclictest25-21ksoftirqd/100:25:131
2463199133,1cyclictest25-21ksoftirqd/122:42:501
2462799130,0cyclictest0-21swapper/021:47:310
24492130,0sleep20-21swapper/222:09:372
2464099120,11cyclictest16498-21bash23:51:523
2464099120,11cyclictest0-21swapper/321:57:533
24637991210,1cyclictest7063-21sshd21:49:172
24637991210,1cyclictest0-21swapper/221:52:262
2463799120,1cyclictest24695-21lspci23:30:272
2463799120,11cyclictest23860-21bash23:08:272
2463799120,11cyclictest21116-21sshd22:37:562
2463799120,11cyclictest21116-21sshd22:37:562
2463199124,1cyclictest25-21ksoftirqd/122:20:491
2463199123,3cyclictest25-21ksoftirqd/122:51:411
2463199121,1cyclictest25-21ksoftirqd/123:20:121
24631991210,1cyclictest25-21ksoftirqd/122:31:521
2463199120,11cyclictest20420-21id21:28:371
2463199120,11cyclictest0-21swapper/121:59:071
2462799128,0cyclictest0-21swapper/020:00:200
2462799125,2cyclictest660-21avahi-daemon22:21:240
2462799124,4cyclictest674-21dbus-daemon19:39:590
2462799120,7cyclictest20779-21sshd22:46:080
2462799120,11cyclictest0-21swapper/000:32:100
2462799120,0cyclictest0-21swapper/021:07:200
24640991110,0cyclictest0-21swapper/323:13:423
24640991110,0cyclictest0-21swapper/322:57:423
2464099110,10cyclictest0-21swapper/323:38:523
2464099110,10cyclictest0-21swapper/322:28:533
2464099110,10cyclictest0-21swapper/322:28:523
2464099110,10cyclictest0-21swapper/321:46:233
2463799119,1cyclictest31005-21sshd21:37:572
2463799119,1cyclictest1-21systemd22:16:262
2463799117,3cyclictest13533-21lspci21:56:512
24637991110,0cyclictest0-21swapper/200:15:162
24637991110,0cyclictest0-21swapper/200:13:272
2463799110,10cyclictest0-21swapper/219:40:172
2463799110,10cyclictest0-21swapper/200:03:562
2463199119,1cyclictest25-21ksoftirqd/100:02:531
2463199119,0cyclictest25-21ksoftirqd/100:35:181
2463199113,1cyclictest25-21ksoftirqd/122:13:101
2463199113,1cyclictest25-21ksoftirqd/100:31:441
2463199112,1cyclictest25-21ksoftirqd/122:19:281
2463199112,1cyclictest25-21ksoftirqd/122:09:361
2463199111,1cyclictest25-21ksoftirqd/123:07:411
2463199111,1cyclictest25-21ksoftirqd/121:30:121
2463199111,1cyclictest131rcu_sched00:20:221
2463199110,3cyclictest25-21ksoftirqd/123:10:011
2463199110,1cyclictest25-21ksoftirqd/122:04:231
2463199110,1cyclictest25-21ksoftirqd/100:05:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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