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2026-01-17 - 15:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Sat Jan 17, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
188152850,0sleep018814-21sshd12:21:170
16982850,0sleep20-21swapper/211:22:232
16982850,0sleep20-21swapper/211:22:232
252462790,0sleep0111rcuc/011:21:370
252462790,0sleep0111rcuc/011:21:370
194102770,0sleep10-21swapper/110:34:401
317712560,0sleep30-21swapper/310:24:493
45132550,0sleep30-21swapper/311:19:563
284442540,1sleep228442-21lspci10:08:222
320562530,0sleep10-21swapper/109:58:231
129972530,0sleep10-21swapper/110:36:481
298092520,0sleep30-21swapper/310:15:193
265372520,0sleep10-21swapper/110:51:381
34202510,0sleep30-21swapper/309:34:423
317132510,0sleep10-21swapper/112:36:041
295502510,1sleep20-21swapper/211:38:262
217782510,0sleep10-21swapper/111:18:381
62912500,0sleep10-21swapper/111:06:201
296092500,0sleep00-21swapper/010:05:030
197232500,0sleep30-21swapper/309:23:413
91902490,0sleep20-21swapper/212:23:162
52842480,0sleep10-21swapper/110:05:481
251352480,1sleep229979-21gdbus12:10:502
163442480,0sleep30-21swapper/310:50:443
127272480,0sleep10-21swapper/111:53:271
108672480,0sleep30-21swapper/311:50:283
266072470,0sleep10-21swapper/110:59:551
165252350,0sleep20-21swapper/212:26:362
1929723110,6sleep20-21swapper/207:09:072
191782308,7sleep30-21swapper/307:07:403
190912298,7sleep00-21swapper/007:06:320
109472240,7sleep375750irq/24-eno1-rx-11:58:453
1905722110,7sleep10-21swapper/107:06:051
135142200,0sleep30-21swapper/311:39:513
19480991716,0cyclictest7738-21lspci12:01:102
88912160,0sleep10-21swapper/110:20:061
47682160,0sleep10-21swapper/112:20:101
306712160,0sleep30-21swapper/311:08:273
19486991615,0cyclictest1220-21lspci09:55:093
19480991615,0cyclictest8472-21lspci11:31:072
305472150,0sleep330548-21sshd11:02:583
303762150,0sleep30-21swapper/309:47:523
22842150,0sleep10-21swapper/111:22:261
22842150,0sleep10-21swapper/111:22:261
32642140,0sleep20-21swapper/210:27:482
319442140,0sleep30-21swapper/311:22:123
319442140,0sleep30-21swapper/311:22:123
262182140,0sleep00-21swapper/012:27:260
248872140,0sleep30-21swapper/312:24:373
1948099140,12cyclictest17158-21sshd11:18:142
17222140,0sleep21720-21lspci11:11:262
19486991311,1cyclictest622-13audispd11:47:583
19480991312,0cyclictest22257-21lspci09:46:592
19480991311,1cyclictest33-21ksoftirqd/212:37:572
19480991310,2cyclictest0-21swapper/211:02:142
1947699130,12cyclictest25854-21lspci12:08:121
19469991311,1cyclictest0-21swapper/012:02:590
17032130,0sleep0111rcuc/011:25:100
124812130,1sleep20-21swapper/212:18:032
1948699120,1cyclictest624-13audispd09:14:083
1948099123,3cyclictest33-21ksoftirqd/211:55:332
19480991211,0cyclictest5455-21lspci09:31:212
19480991210,1cyclictest33-21ksoftirqd/209:42:342
1948099120,3cyclictest1012-21sshd10:44:032
1948099120,1cyclictest710-21NetworkManager10:21:042
1948099120,1cyclictest21338-21sshd09:57:142
1948099120,11cyclictest26122-21lspci12:32:542
1948099120,11cyclictest0-21swapper/207:40:142
19476991211,0cyclictest24878-21kworker/1:311:57:281
19476991210,1cyclictest16239-21kworker/1:010:04:581
1947699120,11cyclictest7937-21bash11:44:521
1947699120,11cyclictest17105-21sshd11:31:521
1946999120,1cyclictest29977-21packagekitd11:57:490
1948699119,1cyclictest0-21swapper/312:34:283
19486991110,0cyclictest0-21swapper/312:03:383
1948699110,10cyclictest0-21swapper/310:35:383
1948699110,10cyclictest0-21swapper/309:39:483
1948099113,2cyclictest649-21polkitd11:43:022
1948099111,1cyclictest131rcu_sched10:01:182
19480991110,0cyclictest0-21swapper/211:08:042
1948099110,10cyclictest20379-21sshd09:18:142
1948099110,10cyclictest0-21swapper/212:05:242
1947699119,1cyclictest25-21ksoftirqd/110:25:211
1947699110,10cyclictest0-21swapper/109:34:521
1947699110,0cyclictest0-21swapper/112:10:021
1947699110,0cyclictest0-21swapper/109:12:521
1946999110,10cyclictest0-21swapper/012:35:390
1946999110,10cyclictest0-21swapper/010:25:090
1946999110,10cyclictest0-21swapper/009:40:590
1948699109,0cyclictest0-21swapper/310:41:083
1948699109,0cyclictest0-21swapper/310:33:483
1948699108,1cyclictest41-21ksoftirqd/312:19:273
1948699100,9cyclictest0-21swapper/308:56:483
1948699100,0cyclictest0-21swapper/311:25:423
1948699100,0cyclictest0-21swapper/310:09:283
1948099109,0cyclictest674-21dbus-daemon11:47:542
1948099109,0cyclictest0-21swapper/210:45:042
1948099109,0cyclictest0-21swapper/210:30:242
1948099109,0cyclictest0-21swapper/209:37:542
1948099108,1cyclictest33-21ksoftirqd/211:52:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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