You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-19 - 19:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Thu Feb 19, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51302910,0sleep20-21swapper/211:21:112
36332580,0sleep10-21swapper/110:53:551
258832580,0sleep30-21swapper/310:21:373
137662560,0sleep20-21swapper/212:20:192
27272540,2sleep0821699cyclictest10:49:570
78082530,0sleep20-21swapper/209:34:502
313942520,2sleep2822799cyclictest10:57:122
97172510,0sleep09646-21sshd12:27:420
129482510,0sleep20-21swapper/210:24:002
270092500,0sleep00-21swapper/011:58:460
81622490,0sleep30-21swapper/311:52:373
61192490,0sleep20-21swapper/210:13:232
134582490,0sleep00-21swapper/008:40:140
274182470,0sleep20-21swapper/209:26:562
185752470,0sleep10-21swapper/110:36:131
181982470,0sleep30-21swapper/311:11:073
285792460,1sleep228578-21sshd11:08:332
307112440,2sleep1822299cyclictest10:33:521
80152298,7sleep30-21swapper/307:08:483
79932287,7sleep10-21swapper/107:08:301
79472287,7sleep00-21swapper/007:07:570
77562249,13sleep20-21swapper/207:05:312
46852210,2sleep0821699cyclictest11:36:390
8222991818,0cyclictest18883-21kworker/1:208:05:551
264512180,0sleep00-21swapper/009:26:470
54722170,0sleep30-21swapper/312:19:283
8227991514,0cyclictest321ktimersoftd/211:49:062
8227991514,0cyclictest321ktimersoftd/209:14:512
5632150,0sleep1231rcuc/110:26:191
312892150,0sleep10-21swapper/112:10:491
307812150,0sleep00-21swapper/010:00:470
251982150,0sleep125183-21sshd11:08:091
823399140,1cyclictest674-21dbus-daemon11:38:293
8227991413,0cyclictest6994-21lspci11:17:352
323972140,0sleep10-21swapper/110:12:181
159622140,0sleep015963-21sshd12:36:110
8227991312,0cyclictest20759-21lspci11:26:572
8227991311,1cyclictest32295-21lspci11:40:022
822799130,1cyclictest0-21swapper/212:31:292
822799130,12cyclictest624-13audispd12:03:492
8222991311,1cyclictest6638-21kworker/1:211:52:491
8216991311,1cyclictest0-21swapper/011:53:370
8233991210,1cyclictest8723-21sshd10:38:593
8233991210,1cyclictest620-17auditd11:31:293
823399120,11cyclictest10841-21sshd10:19:493
8227991212,0cyclictest527-40kipmi011:30:412
8227991212,0cyclictest527-40kipmi010:16:442
8227991211,0cyclictest18541-21lspci10:51:462
8227991210,1cyclictest23573-21bash09:20:392
8227991210,1cyclictest0-21swapper/212:35:292
822799120,11cyclictest0-21swapper/209:37:092
822299120,1cyclictest25361-21sshd10:05:231
821699120,1cyclictest25661-21sshd12:14:070
821699120,1cyclictest18392-21bash11:03:270
821699120,11cyclictest15127-21sshd10:31:560
821699120,11cyclictest0-21swapper/009:49:370
823399119,1cyclictest674-21dbus-daemon12:23:293
823399119,1cyclictest3624-21bash09:17:193
823399110,10cyclictest0-21swapper/309:55:393
823399110,10cyclictest0-21swapper/309:11:293
823399110,0cyclictest0-21swapper/310:30:393
8227991110,0cyclictest18864-21lspci09:58:542
822799110,10cyclictest0-21swapper/210:31:492
822799110,10cyclictest0-21swapper/209:43:192
822799110,10cyclictest0-21swapper/207:15:192
822299119,1cyclictest26657-21tty09:21:131
822299119,1cyclictest0-21swapper/109:28:131
8222991110,0cyclictest0-21swapper/112:24:031
8222991110,0cyclictest0-21swapper/111:47:531
822299110,10cyclictest0-21swapper/111:42:231
822299110,10cyclictest0-21swapper/111:23:131
822299110,10cyclictest0-21swapper/111:03:331
822299110,10cyclictest0-21swapper/110:57:131
822299110,10cyclictest0-21swapper/110:18:331
822299110,0cyclictest0-21swapper/112:17:531
822299110,0cyclictest0-21swapper/111:33:331
821699119,1cyclictest1015-21runrttasks07:55:170
8216991110,0cyclictest0-21swapper/010:43:170
8216991110,0cyclictest0-21swapper/010:15:070
8216991110,0cyclictest0-21swapper/007:45:170
821699110,10cyclictest0-21swapper/009:36:570
823399109,0cyclictest0-21swapper/312:29:393
823399109,0cyclictest0-21swapper/312:05:593
823399109,0cyclictest0-21swapper/312:05:593
823399109,0cyclictest0-21swapper/311:58:393
823399109,0cyclictest0-21swapper/311:26:193
823399109,0cyclictest0-21swapper/310:58:293
823399109,0cyclictest0-21swapper/309:47:593
823399108,1cyclictest4379-21lspci12:11:293
823399100,0cyclictest0-21swapper/310:10:493
823399100,0cyclictest0-21swapper/310:05:093
823399100,0cyclictest0-21swapper/309:20:593
822799109,0cyclictest4887-21lspci10:26:512
822799109,0cyclictest0-21swapper/212:16:582
822799108,1cyclictest33-21ksoftirqd/212:10:162
822799100,0cyclictest0-21swapper/212:07:292
822799100,0cyclictest0-21swapper/212:07:292
822799100,0cyclictest0-21swapper/211:12:392
822799100,0cyclictest0-21swapper/209:54:082
822799100,0cyclictest0-21swapper/209:47:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional