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2025-12-05 - 16:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Fri Dec 05, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1113021040,1sleep311126-21lspci09:32:383
49442730,1sleep341-21ksoftirqd/309:24:493
266892730,0sleep30-21swapper/310:44:113
269082650,2sleep3472499cyclictest11:59:253
204422590,0sleep30-21swapper/309:57:573
303102570,0sleep20-21swapper/210:13:022
272502570,0sleep10-21swapper/111:59:271
315202560,0sleep10-21swapper/109:41:371
82832550,0sleep30-21swapper/310:56:413
306712550,0sleep030669-21sshd10:44:360
158752550,0sleep20-21swapper/211:16:022
65512540,0sleep00-21swapper/010:35:030
69262530,0sleep30-21swapper/309:18:043
178022530,0sleep10-21swapper/109:33:241
215382520,1sleep021536-21sshd09:40:320
310272510,0sleep0111rcuc/009:52:050
172092510,1sleep317210-21bash09:50:283
240672480,2sleep2472399cyclictest10:08:502
231482480,0sleep00-21swapper/010:08:440
149752480,0sleep30-21swapper/312:08:543
220062400,0sleep10-21swapper/110:47:141
267032370,1sleep326705-21bash11:17:153
42242309,7sleep00-21swapper/007:05:080
458922614,7sleep20-21swapper/207:09:392
442422311,7sleep30-21swapper/307:07:403
455222211,6sleep10-21swapper/107:09:141
195512220,0sleep00-21swapper/012:39:030
229732190,0sleep30-21swapper/310:19:123
4718991816,1cyclictest23061-21lspci09:37:180
7612170,0sleep10-21swapper/112:07:201
260052170,0sleep10-21swapper/112:29:511
137402170,1sleep0101ktimersoftd/009:22:140
4723991615,0cyclictest523-40kipmi012:29:142
161222160,0sleep30-21swapper/309:40:033
141332160,2sleep275650irq/25-eno1-tx-11:33:482
4723991514,0cyclictest26523-21lspci10:54:552
4723991514,0cyclictest20486-21lspci11:01:342
4723991514,0cyclictest18716-21lspci12:09:182
4718991514,0cyclictest9060-21lspci10:24:410
326222150,0sleep30-21swapper/312:20:363
272552150,0sleep20-21swapper/210:26:402
272552150,0sleep20-21swapper/210:26:402
161352150,0sleep00-21swapper/010:15:000
4724991410,3cyclictest616-17auditd12:00:143
4723991413,0cyclictest32755-21lspci09:59:162
4723991413,0cyclictest18857-21lspci10:01:112
280982140,0sleep20-21swapper/211:45:182
261022140,0sleep026103-21sshd11:48:280
229432140,0sleep20-21swapper/210:40:182
118072140,0sleep30-21swapper/311:43:433
87192130,0sleep20-21swapper/209:10:182
4723991312,0cyclictest30743-21lspci11:14:122
4723991312,0cyclictest19859-21lspci10:15:182
472299130,1cyclictest0-21swapper/110:18:491
127572130,0sleep212759-21bash09:36:132
52242120,0sleep10-21swapper/110:34:561
472499120,1cyclictest8277-21sshd09:14:343
472499120,11cyclictest2232-21cp11:35:543
472399120,11cyclictest619-17sedispatch12:14:252
472399120,11cyclictest619-17sedispatch09:30:442
472399120,11cyclictest0-21swapper/212:20:252
472399120,11cyclictest0-21swapper/211:51:452
472399120,11cyclictest0-21swapper/210:56:052
472299120,1cyclictest29978-21sshd09:27:391
472299120,1cyclictest19510-21cp10:25:491
472299120,1cyclictest19510-21cp10:25:491
4718991210,1cyclictest29404-21tty10:48:010
4718991210,1cyclictest0-21swapper/011:36:320
471899120,1cyclictest7571-21sshd10:52:410
471899120,11cyclictest0-21swapper/011:02:420
4724991110,0cyclictest75550irq/24-eno1-rx-09:26:243
4724991110,0cyclictest0-21swapper/312:39:543
472499110,10cyclictest75550irq/24-eno1-rx-10:11:543
4723991110,0cyclictest0-21swapper/212:03:052
4723991110,0cyclictest0-21swapper/210:30:242
472399110,10cyclictest20248-21sshd09:15:442
472299119,1cyclictest30175-21lspci11:17:391
472299119,1cyclictest15300-21lspci10:04:191
472299119,1cyclictest0-21swapper/109:46:191
472299110,10cyclictest0-21swapper/111:29:091
472299110,10cyclictest0-21swapper/110:58:291
471899119,1cyclictest20379-21sshd09:19:310
4718991110,0cyclictest17460-21lspci12:12:450
4718991110,0cyclictest14561-21lspci12:01:280
4718991110,0cyclictest0-21swapper/012:21:120
4718991110,0cyclictest0-21swapper/010:04:210
471899110,0cyclictest11445-21lspci12:05:020
471899110,0cyclictest0-21swapper/009:12:010
237382110,1sleep323718-21sshd10:50:563
61962100,0sleep20-21swapper/211:07:372
472499109,0cyclictest0-21swapper/312:18:443
472499109,0cyclictest0-21swapper/311:23:443
472499109,0cyclictest0-21swapper/311:00:543
472499108,1cyclictest775-21sshd10:06:143
472499100,0cyclictest0-21swapper/312:12:443
472499100,0cyclictest0-21swapper/311:49:243
472399109,0cyclictest0-21swapper/210:49:042
472399109,0cyclictest0-21swapper/209:46:542
472399109,0cyclictest0-21swapper/209:27:342
472299109,0cyclictest0-21swapper/112:16:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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