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2026-02-23 - 12:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Mon Feb 23, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269422740,0sleep20-21swapper/222:23:492
220082740,0sleep00-21swapper/022:50:370
270312550,0sleep30-21swapper/323:03:063
85452540,0sleep20-21swapper/200:03:412
19752540,0sleep00-21swapper/000:22:330
109112540,0sleep00-21swapper/023:12:560
91242520,0sleep30-21swapper/321:15:053
8362500,0sleep10-21swapper/121:52:511
82942500,0sleep20-21swapper/223:16:312
82942500,0sleep20-21swapper/223:16:312
291312500,0sleep30-21swapper/300:37:423
284252500,0sleep10-21swapper/123:50:181
187612500,0sleep30-21swapper/300:32:293
155062500,0sleep20-21swapper/200:20:152
133872500,0sleep30-21swapper/322:57:293
32542490,0sleep20-21swapper/223:59:082
256282490,0sleep10-21swapper/123:06:481
238552490,1sleep32729299cyclictest23:34:103
32422480,0sleep30-21swapper/323:39:313
321382480,0sleep10-21swapper/121:41:221
156152470,2sleep12728199cyclictest21:16:021
14902450,0sleep10-21swapper/121:24:591
325862440,0sleep00-21swapper/022:36:120
16192410,0sleep2321ktimersoftd/200:30:202
3782400,1sleep1379-21bash00:14:331
26892370,0sleep10-21swapper/100:30:271
269052286,6sleep00-21swapper/019:06:370
271252277,7sleep10-21swapper/119:09:281
2688322513,7sleep20-21swapper/219:06:232
2680422318,3sleep30-21swapper/319:05:283
21262210,0sleep10-21swapper/121:25:031
119032200,0sleep20-21swapper/223:48:232
243392160,0sleep30-21swapper/323:18:323
243392160,0sleep30-21swapper/323:18:323
33122150,1sleep2321ktimersoftd/223:51:122
27292991513,1cyclictest27067-21lspci00:17:443
288592140,0sleep10-21swapper/123:30:431
2727599140,12cyclictest1190-21sshd23:47:030
256092140,0sleep30-21swapper/323:14:483
152682140,0sleep3391rcuc/321:49:493
27281991311,1cyclictest25-21ksoftirqd/122:50:261
190972130,0sleep319096-21sshd21:44:533
27292991211,0cyclictest31071-21lspci22:47:543
27292991210,1cyclictest8354-21grep23:55:423
27292991210,1cyclictest17208-21lspci00:00:423
27287991210,1cyclictest1026-21sshd22:40:382
2728799120,1cyclictest4715-21lspci22:48:392
2728799120,1cyclictest0-21swapper/221:11:482
2728199120,10cyclictest0-21swapper/123:18:361
2728199120,10cyclictest0-21swapper/123:18:361
27275991210,1cyclictest7630-21lspci22:16:230
2727599120,11cyclictest1026-21sshd22:14:540
27292991110,0cyclictest0-21swapper/323:44:323
27292991110,0cyclictest0-21swapper/323:28:233
27292991110,0cyclictest0-21swapper/323:28:223
27292991110,0cyclictest0-21swapper/321:28:223
2728799119,1cyclictest8455-21lspci21:31:392
2728799119,1cyclictest27942-21lspci22:59:182
27287991110,0cyclictest0-21swapper/223:12:392
27287991110,0cyclictest0-21swapper/221:19:282
2728199119,1cyclictest25-21ksoftirqd/122:25:001
2728199119,1cyclictest11145-21cp23:01:071
2728199116,1cyclictest25-21ksoftirqd/100:18:251
2728199112,2cyclictest131rcu_sched00:36:021
2728199112,1cyclictest25-21ksoftirqd/100:27:011
27281991110,0cyclictest0-21swapper/100:01:561
2728199110,10cyclictest0-21swapper/100:05:461
27275991110,0cyclictest0-21swapper/023:22:540
2727599110,1cyclictest0-21swapper/023:32:230
51302100,0sleep10-21swapper/121:59:171
2729299109,0cyclictest527-40kipmi022:03:103
2729299109,0cyclictest0-21swapper/323:50:433
2729299109,0cyclictest0-21swapper/323:24:123
2729299109,0cyclictest0-21swapper/322:21:223
2729299109,0cyclictest0-21swapper/322:19:523
2729299109,0cyclictest0-21swapper/321:20:223
2729299109,0cyclictest0-21swapper/319:48:323
2729299100,0cyclictest0-21swapper/300:11:023
2728799109,0cyclictest0-21swapper/223:43:582
2728799109,0cyclictest0-21swapper/222:37:582
2728799109,0cyclictest0-21swapper/221:47:282
2728799109,0cyclictest0-21swapper/220:20:182
2728799100,0cyclictest0-21swapper/221:38:482
2728799100,0cyclictest0-21swapper/220:25:182
2728799100,0cyclictest0-21swapper/200:13:082
2728199109,0cyclictest0-21swapper/123:41:571
2728199109,0cyclictest0-21swapper/122:47:461
2728199109,0cyclictest0-21swapper/122:26:261
2728199103,1cyclictest25-21ksoftirqd/123:10:211
2728199101,1cyclictest25-21ksoftirqd/123:55:031
2728199101,1cyclictest131rcu_sched23:24:261
2728199100,1cyclictest131rcu_sched23:26:001
2728199100,1cyclictest131rcu_sched23:26:001
2728199100,1cyclictest131rcu_sched22:42:231
2728199100,0cyclictest131rcu_sched22:58:121
2727599109,0cyclictest0-21swapper/023:27:030
2727599109,0cyclictest0-21swapper/023:27:030
2727599109,0cyclictest0-21swapper/023:18:430
2727599109,0cyclictest0-21swapper/023:18:430
2727599109,0cyclictest0-21swapper/021:50:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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