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2026-01-19 - 11:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Mon Jan 19, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
144772830,1sleep1241ktimersoftd/123:01:231
298362810,1sleep0674-21dbus-daemon21:57:330
137062750,1sleep12747699cyclictest00:15:371
295222740,0sleep1231rcuc/121:24:101
325812560,0sleep00-21swapper/000:31:020
221842560,0sleep00-21swapper/022:03:420
221842560,0sleep00-21swapper/022:03:420
307462540,4sleep030742-21lspci23:57:490
59212530,0sleep00-21swapper/000:20:280
279142520,0sleep10-21swapper/100:05:471
222652510,1sleep0111rcuc/021:53:160
75012500,1sleep27499-21lspci21:37:482
184052500,1sleep018406-21sshd00:38:070
134382500,2sleep22747799cyclictest21:55:432
185272490,0sleep218525-21lspci00:05:042
261072480,0sleep10-21swapper/122:32:111
187662480,0sleep20-21swapper/223:37:282
306492470,0sleep10-21swapper/121:18:461
242442470,1sleep224243-21bash22:45:412
76982450,0sleep10-21swapper/122:02:071
76982450,0sleep10-21swapper/122:02:071
177402450,1sleep117720-21sshd21:27:381
124872430,0sleep10-21swapper/121:31:231
38142340,0sleep20-21swapper/222:19:062
2703823314,14sleep00-21swapper/019:05:550
269992308,7sleep30-21swapper/319:05:263
2711622520,3sleep10-21swapper/119:06:521
271172237,11sleep20-21swapper/219:06:532
256632200,0sleep20-21swapper/221:43:132
187372200,0sleep20-21swapper/223:29:152
151662190,0sleep20-21swapper/222:58:432
27476991715,1cyclictest674-21dbus-daemon23:21:161
174462170,2sleep32747999cyclictest22:17:033
122132170,0sleep10-21swapper/122:55:381
302112160,0sleep10-21swapper/122:35:151
285712160,0sleep00-21swapper/023:35:300
216042160,1sleep0111rcuc/023:10:150
77382150,1sleep0101ktimersoftd/021:20:160
27476991513,1cyclictest30324-21kworker/1:121:46:331
27476991513,1cyclictest25-21ksoftirqd/100:03:481
89462140,0sleep20-21swapper/223:14:412
291232140,0sleep30-21swapper/323:05:213
2747699143,3cyclictest25-21ksoftirqd/123:53:281
27476991414,0cyclictest27988-21kworker/1:223:13:131
27476991413,0cyclictest13421-21kworker/1:121:11:531
225712140,0sleep00-21swapper/023:32:180
55292130,0sleep10-21swapper/121:37:351
37062130,1sleep33700-21lspci21:54:493
27479991311,1cyclictest7273-21lspci22:12:293
27477991311,1cyclictest1441-21bash00:39:272
2747699133,2cyclictest25-21ksoftirqd/100:25:541
27476991313,0cyclictest26431-21kworker/1:023:30:441
61812120,0sleep20-21swapper/222:05:202
2747999120,1cyclictest1178-21sshd22:35:293
2747999120,11cyclictest0-21swapper/321:31:393
27477991210,1cyclictest30725-21sshd21:50:372
2747799120,11cyclictest15967-21cp22:28:382
2747699128,1cyclictest25-21ksoftirqd/100:11:041
2747699125,3cyclictest25-21ksoftirqd/121:40:131
2747699125,1cyclictest25-21ksoftirqd/122:46:221
2747699122,2cyclictest25-21ksoftirqd/123:45:021
2747699122,1cyclictest25-21ksoftirqd/123:07:091
2747699122,1cyclictest25-21ksoftirqd/122:50:391
27476991210,1cyclictest26138-21lspci23:27:061
27476991210,1cyclictest0-21swapper/121:56:061
2747699120,1cyclictest131rcu_sched00:24:401
2747699120,11cyclictest0-21swapper/121:54:161
2747399120,1cyclictest1-21systemd22:55:230
253922120,0sleep3401ktimersoftd/323:21:313
2747999119,1cyclictest9876-21sshd00:23:393
2747999119,1cyclictest23980-21sshd22:59:293
27479991110,0cyclictest0-21swapper/323:59:393
27479991110,0cyclictest0-21swapper/322:26:593
2747999110,10cyclictest0-21swapper/323:29:093
2747999110,10cyclictest0-21swapper/322:49:093
2747999110,10cyclictest0-21swapper/322:05:493
2747999110,10cyclictest0-21swapper/300:39:403
2747799119,1cyclictest8849-21sshd00:26:172
2747799119,1cyclictest0-21swapper/223:55:272
27477991110,0cyclictest0-21swapper/221:16:072
2747799110,10cyclictest0-21swapper/222:37:072
2747699119,1cyclictest25-21ksoftirqd/123:40:001
2747699116,1cyclictest25-21ksoftirqd/100:35:231
2747699114,1cyclictest25-21ksoftirqd/122:40:291
2747699113,1cyclictest25-21ksoftirqd/122:21:481
2747699112,1cyclictest25-21ksoftirqd/122:27:421
2747699111,1cyclictest131rcu_sched23:59:161
27476991111,0cyclictest13966-21kworker/1:220:51:261
27476991111,0cyclictest13966-21kworker/1:219:58:551
27476991110,1cyclictest7820-21kworker/1:019:40:111
27476991110,0cyclictest13966-21kworker/1:220:40:411
27476991110,0cyclictest0-21swapper/122:18:361
2747399119,1cyclictest19383-21lspci22:53:330
27473991110,0cyclictest0-21swapper/022:36:130
27473991110,0cyclictest0-21swapper/022:31:030
27473991110,0cyclictest0-21swapper/021:39:230
2747399110,10cyclictest0-21swapper/023:02:230
2747399110,10cyclictest0-21swapper/021:42:430
2747399110,10cyclictest0-21swapper/021:34:330
230602110,1sleep3391rcuc/323:46:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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