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2026-03-23 - 05:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Mon Mar 23, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
175532960,0sleep017529-21sshd21:17:040
3022940,0sleep30-21swapper/322:00:453
90842840,0sleep39083-21bash21:48:003
220062790,0sleep30-21swapper/322:18:553
254102780,1sleep025406-21crond00:20:000
135272730,0sleep00-21swapper/022:04:390
32402720,0sleep0111rcuc/021:36:390
255082640,0sleep01026-21sshd23:41:230
75352580,0sleep30-21swapper/323:09:383
88392550,0sleep00-21swapper/023:37:150
182742550,0sleep30-21swapper/323:29:533
162562550,0sleep20-21swapper/221:16:552
46782540,1sleep34679-21bash23:01:053
6372520,0sleep10-21swapper/100:39:561
257352520,1sleep125-21ksoftirqd/100:09:001
235412520,0sleep10-21swapper/122:05:231
165822520,0sleep2311rcuc/222:13:022
229972510,0sleep20-21swapper/200:14:182
8182500,0sleep10-21swapper/122:19:541
303772500,0sleep00-21swapper/021:10:560
289022500,1sleep328898-21lspci22:52:123
95552490,0sleep29553-21sshd22:01:322
160802490,0sleep10-21swapper/122:26:311
53212480,0sleep30-21swapper/321:42:153
152912480,0sleep00-21swapper/023:59:500
118842480,1sleep248-21kauditd23:48:302
204352470,1sleep219943-21/usr/sbin/munin23:05:132
17202470,0sleep21718-21sshd22:30:442
369224331,7sleep10-21swapper/119:05:251
245752380,0sleep20-21swapper/221:49:192
40202297,7sleep20-21swapper/219:09:312
400322615,7sleep00-21swapper/019:09:170
376222311,7sleep30-21swapper/319:06:153
243772220,0sleep3391rcuc/321:38:263
197942190,0sleep10-21swapper/100:22:131
283182180,1sleep2620-17auditd22:05:492
89602170,0sleep20-21swapper/200:04:482
89602170,0sleep20-21swapper/200:04:482
69212170,1sleep3391rcuc/300:01:493
69212170,1sleep3391rcuc/300:01:493
155702170,0sleep10-21swapper/121:56:391
103262170,0sleep30-21swapper/323:31:533
38192160,0sleep00-21swapper/000:34:420
157892160,0sleep00-21swapper/023:04:510
156062160,0sleep315595-21sshd21:51:113
6732150,0sleep30-21swapper/323:50:153
234892150,1sleep3391rcuc/322:35:183
194402140,0sleep1231rcuc/100:33:151
418299130,1cyclictest32310-21sshd22:25:123
418299130,12cyclictest0-21swapper/321:29:323
417699130,1cyclictest0-21swapper/222:17:092
4172991311,1cyclictest0-21swapper/123:05:161
252492130,0sleep30-21swapper/300:30:573
239162130,0sleep10-21swapper/123:35:441
80932120,0sleep30-21swapper/322:44:593
4182991211,0cyclictest0-21swapper/321:12:323
418299120,1cyclictest25516-21lspci22:49:123
418299120,1cyclictest13799-21sshd23:59:423
418299120,11cyclictest674-21dbus-daemon23:19:523
417699125,3cyclictest33-21ksoftirqd/200:39:132
417699124,1cyclictest33-21ksoftirqd/222:39:132
4176991210,1cyclictest0-21swapper/223:38:292
4176991210,1cyclictest0-21swapper/221:35:592
417699120,1cyclictest9795-21sshd22:47:492
417699120,1cyclictest0-21swapper/200:16:502
4172991210,1cyclictest26208-21lspci22:57:251
417299120,1cyclictest0-21swapper/121:49:461
417299120,11cyclictest674-21dbus-daemon21:18:261
4165991211,0cyclictest0-21swapper/021:56:110
416599120,1cyclictest31974-21sshd22:14:210
416599120,1cyclictest23008-21sshd22:46:100
416599120,11cyclictest32645-21sshd22:19:510
416599120,11cyclictest0-21swapper/023:30:110
416599120,11cyclictest0-21swapper/022:40:410
237172120,0sleep10-21swapper/121:29:151
113542120,0sleep20-21swapper/223:42:582
4182991110,0cyclictest0-21swapper/322:24:023
418299110,10cyclictest0-21swapper/300:22:023
417699119,1cyclictest33-21ksoftirqd/200:10:002
417699119,1cyclictest0-21swapper/223:22:482
417699114,2cyclictest33-21ksoftirqd/222:44:052
417699110,1cyclictest24286-21lspci21:29:182
417699110,10cyclictest0-21swapper/222:22:392
417699110,10cyclictest0-21swapper/200:30:202
417699110,0cyclictest0-21swapper/223:30:392
417299119,1cyclictest30013-21lspci23:28:061
417299119,1cyclictest0-21swapper/123:51:561
4172991110,0cyclictest0-21swapper/122:42:061
4172991110,0cyclictest0-21swapper/122:21:161
4172991110,0cyclictest0-21swapper/122:11:261
4172991110,0cyclictest0-21swapper/100:03:561
4172991110,0cyclictest0-21swapper/100:03:551
417299110,10cyclictest20438-21sshd21:38:061
417299110,10cyclictest0-21swapper/123:13:561
417299110,10cyclictest0-21swapper/122:51:561
417299110,10cyclictest0-21swapper/121:13:161
4165991110,0cyclictest0-21swapper/021:45:410
4165991110,0cyclictest0-21swapper/021:43:200
4165991110,0cyclictest0-21swapper/000:36:200
416599110,10cyclictest0-21swapper/023:09:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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