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2025-12-07 - 01:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Sun Dec 07, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
200632990,2sleep158499cyclictest22:10:461
264272920,0sleep20-21swapper/200:15:322
26502750,1sleep10-21swapper/123:29:571
223032740,0sleep00-21swapper/021:43:510
3762720,0sleep30-21swapper/321:55:143
77202650,0sleep30-21swapper/300:03:473
39282650,0sleep13917-21lspci21:45:151
201682640,0sleep20-21swapper/200:01:422
21302620,0sleep00-21swapper/023:56:360
166872620,0sleep20-21swapper/221:33:032
160552610,0sleep00-21swapper/023:01:040
149562610,0sleep10-21swapper/121:22:441
112902600,0sleep111282-21sshd23:50:551
63042580,0sleep20-21swapper/223:23:332
104432580,0sleep10-21swapper/123:17:151
264642570,0sleep20-21swapper/221:09:522
53532560,0sleep20-21swapper/223:10:072
230432560,0sleep00-21swapper/023:52:110
321342550,0sleep10-21swapper/121:38:021
278572530,0sleep10-21swapper/121:58:091
111762530,0sleep00-21swapper/021:22:190
81982520,0sleep00-21swapper/021:45:380
31022520,0sleep20-21swapper/222:22:412
263372520,1sleep1241ktimersoftd/123:39:101
145962500,0sleep00-21swapper/022:23:550
275592490,0sleep20-21swapper/223:29:102
63672480,0sleep00-21swapper/000:16:500
54892480,1sleep05484-21bash22:46:420
285202460,0sleep30-21swapper/323:09:123
59712440,0sleep30-21swapper/323:33:393
105732410,0sleep00-21swapper/023:30:410
39712400,0sleep00-21swapper/022:09:100
319592370,2sleep057899cyclictest22:25:390
4512309,7sleep20-21swapper/219:09:482
326262308,7sleep10-21swapper/119:06:271
3255922811,12sleep30-21swapper/319:05:373
55802230,0sleep10-21swapper/100:06:501
121322230,1sleep012131-21bash22:30:200
3275122210,7sleep00-21swapper/019:07:540
321482220,0sleep20-21swapper/222:39:232
43192210,0sleep10-21swapper/122:36:221
16882190,0sleep10-21swapper/122:59:411
283072170,0sleep00-21swapper/023:45:580
26832170,0sleep20-21swapper/222:43:042
232062170,0sleep20-21swapper/222:48:322
162292170,0sleep00-21swapper/023:27:550
69452160,0sleep10-21swapper/123:30:171
237992160,0sleep30-21swapper/321:26:593
205032160,1sleep00-21swapper/021:16:420
578991514,0cyclictest15832-21lspci23:21:070
134072150,0sleep00-21swapper/022:00:000
114282150,0sleep10-21swapper/123:44:191
584991412,1cyclictest616-17auditd22:53:231
584991412,1cyclictest616-17auditd22:53:221
58599130,2cyclictest700-21gdbus00:39:002
584991311,1cyclictest0-21swapper/122:02:221
58499130,12cyclictest646-21dbus-daemon22:43:221
150952130,0sleep30-21swapper/323:44:413
586991210,1cyclictest9465-21lspci23:10:273
58699120,1cyclictest30380-21lspci21:20:563
58699120,11cyclictest17054-21sshd00:21:173
58699120,11cyclictest12816-21sshd21:39:273
58699120,11cyclictest0-21swapper/300:05:483
585991210,1cyclictest25513-21bash00:29:402
58599120,1cyclictest25311-21lspci22:04:392
58599120,11cyclictest0-21swapper/200:10:012
584991210,1cyclictest9211-21sshd00:00:321
58499120,1cyclictest616-17auditd23:56:021
58499120,1cyclictest0-21swapper/123:10:521
57899120,1cyclictest31310-21sshd21:51:370
57899120,11cyclictest18141-21sshd22:17:270
586991110,0cyclictest0-21swapper/323:35:473
58699110,0cyclictest0-21swapper/322:44:083
58699110,0cyclictest0-21swapper/322:30:073
585991110,0cyclictest0-21swapper/222:50:502
585991110,0cyclictest0-21swapper/222:50:492
585991110,0cyclictest0-21swapper/200:30:512
58599110,1cyclictest0-21swapper/223:30:222
58599110,10cyclictest0-21swapper/222:15:192
58599110,10cyclictest0-21swapper/221:36:092
58599110,10cyclictest0-21swapper/221:15:192
58599110,0cyclictest0-21swapper/221:45:092
58599110,0cyclictest0-21swapper/221:20:392
584991110,0cyclictest0-21swapper/122:30:331
584991110,0cyclictest0-21swapper/100:20:331
58499110,1cyclictest13208-21bash21:53:121
58499110,10cyclictest0-21swapper/123:04:021
578991110,0cyclictest28639-21lspci00:22:360
578991110,0cyclictest14540-21lspci23:14:280
578991110,0cyclictest12182-21lspci21:29:110
578991110,0cyclictest10466-21lspci22:57:120
578991110,0cyclictest0-21swapper/022:04:270
578991110,0cyclictest0-21swapper/020:55:170
57899110,0cyclictest0-21swapper/021:10:170
164882110,0sleep316486-21lspci00:35:393
58699109,0cyclictest0-21swapper/323:03:373
58699109,0cyclictest0-21swapper/322:28:573
58699109,0cyclictest0-21swapper/322:01:173
58699109,0cyclictest0-21swapper/319:44:463
58699109,0cyclictest0-21swapper/300:11:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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