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2026-03-10 - 20:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Tue Mar 10, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27672950,0sleep00-21swapper/012:15:040
126632940,0sleep00-21swapper/010:47:360
174832630,0sleep20-21swapper/212:05:082
102202590,0sleep20-21swapper/211:09:172
57902570,0sleep30-21swapper/311:39:093
34732570,1sleep33467-21sshd11:08:423
30072550,0sleep10-21swapper/109:55:131
104682530,0sleep20-21swapper/209:59:312
243392520,0sleep30-21swapper/312:38:583
51352510,1sleep15132-21lspci11:14:201
77552500,0sleep30-21swapper/310:41:423
288882500,0sleep00-21swapper/011:55:010
12172500,0sleep20-21swapper/210:35:412
88482480,0sleep10-21swapper/112:07:161
194932480,0sleep00-21swapper/012:30:140
268842460,0sleep20-21swapper/209:29:202
128692460,1sleep112848-21sshd12:29:431
69522450,0sleep10-21swapper/109:52:141
52212350,1sleep11073-21nfsd11:52:581
2579523524,7sleep00-21swapper/007:06:160
83262250,0sleep00-21swapper/009:59:170
29402220,2sleep22620899cyclictest11:27:512
259742229,7sleep20-21swapper/207:08:292
2590922110,7sleep10-21swapper/107:07:411
243032219,7sleep30-21swapper/307:05:063
245912180,0sleep20-21swapper/212:11:202
70082170,0sleep00-21swapper/011:41:590
51402170,2sleep32621499cyclictest11:44:393
292192170,1sleep148-21kauditd10:51:421
284892170,0sleep30-21swapper/309:12:553
254162170,1sleep225417-21sshd11:32:322
225832170,0sleep00-21swapper/012:27:440
168762170,0sleep3391rcuc/312:07:583
52752160,1sleep0620-17auditd11:30:460
313872160,0sleep00-21swapper/011:00:050
223212160,0sleep10-21swapper/109:11:491
197832160,0sleep00-21swapper/010:40:030
18802160,1sleep31882-21id11:00:173
186602160,1sleep2311rcuc/209:32:522
136882160,0sleep1231rcuc/111:31:311
322152150,0sleep10-21swapper/110:30:111
288572150,1sleep128847-21rm11:41:041
95022140,1sleep19498-21sshd10:55:261
91012140,0sleep30-21swapper/309:26:083
71022140,0sleep20-21swapper/211:22:432
30362140,0sleep20-21swapper/212:28:512
2620299141,1cyclictest0-21swapper/110:45:251
2620299140,11cyclictest674-21dbus-daemon11:24:461
193202140,0sleep2311rcuc/210:20:502
36912130,0sleep10-21swapper/110:09:081
319612130,0sleep30-21swapper/310:05:133
26197991311,1cyclictest0-21swapper/010:04:090
2619799130,12cyclictest624-13audispd10:37:380
224122130,0sleep10-21swapper/111:37:471
48142120,0sleep00-21swapper/012:23:290
26214991210,1cyclictest10005-21sshd09:45:373
26214991210,1cyclictest0-21swapper/310:34:163
2621499120,1cyclictest29979-21gdbus09:39:573
2621499120,11cyclictest0-21swapper/311:50:473
26208991210,1cyclictest4358-21sshd11:36:122
26208991210,1cyclictest0-21swapper/211:18:232
2620899120,1cyclictest26934-21sshd10:11:332
26202991210,1cyclictest723-21gdbus10:43:061
2620299120,11cyclictest674-21dbus-daemon11:19:461
26197991210,1cyclictest0-21swapper/010:28:190
26197991210,1cyclictest0-21swapper/010:10:180
2619799120,11cyclictest9523-21sshd11:39:290
213752120,0sleep10-21swapper/109:43:281
2621499119,1cyclictest30757-21grep12:25:373
2621499119,1cyclictest15461-21lspci11:26:073
26214991110,0cyclictest0-21swapper/312:19:073
26214991110,0cyclictest0-21swapper/312:12:373
2621499110,10cyclictest0-21swapper/311:24:563
26208991110,0cyclictest0-21swapper/212:35:522
2620899110,10cyclictest0-21swapper/210:54:532
2620899110,10cyclictest0-21swapper/210:26:532
2620899110,10cyclictest0-21swapper/209:20:532
2620899110,0cyclictest0-21swapper/212:18:432
2620299119,1cyclictest28238-21grep12:03:161
26202991110,0cyclictest0-21swapper/112:31:561
2620299110,0cyclictest29618-21sshd10:15:161
26197991110,0cyclictest0-21swapper/012:02:280
2619799110,1cyclictest0-21swapper/011:17:290
2619799110,10cyclictest0-21swapper/010:56:190
2619799110,10cyclictest0-21swapper/009:38:190
2619799110,0cyclictest0-21swapper/012:39:290
2621499109,0cyclictest0-21swapper/310:23:073
2621499100,0cyclictest0-21swapper/311:46:573
2621499100,0cyclictest0-21swapper/311:46:573
2621499100,0cyclictest0-21swapper/311:19:573
2621499100,0cyclictest0-21swapper/310:51:273
2620899109,0cyclictest0-21swapper/211:50:232
2620899109,0cyclictest0-21swapper/211:46:332
2620899109,0cyclictest0-21swapper/211:46:322
2620899109,0cyclictest0-21swapper/210:16:332
2620899109,0cyclictest0-21swapper/209:44:022
2620899108,1cyclictest3039-21sshd12:34:232
2620899108,1cyclictest0-21swapper/211:58:022
2620899100,9cyclictest0-21swapper/207:40:232
2620899100,0cyclictest0-21swapper/211:02:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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