You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-12-05 - 02:36
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Fri Dec 05, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2722421130,2sleep32148599cyclictest22:42:243
786621070,0sleep20-21swapper/222:40:222
186292990,1sleep318625-21bash22:25:013
137962990,1sleep02146599cyclictest00:36:160
116232970,2sleep02146599cyclictest21:42:210
87242960,0sleep10-21swapper/121:13:261
42512920,0sleep04250-21sshd22:13:250
189082900,2sleep12147299cyclictest00:14:541
310442840,0sleep30-21swapper/320:50:183
174622660,0sleep00-21swapper/000:25:340
115162650,1sleep011519-21unixbench_multi20:00:220
164592640,0sleep20-21swapper/222:51:122
122392640,2sleep02146599cyclictest21:13:490
76612630,0sleep20-21swapper/223:56:442
305942620,0sleep10-21swapper/100:19:301
213842620,0sleep00-21swapper/022:32:030
210642580,0sleep10-21swapper/123:01:441
74782570,0sleep30-21swapper/322:20:253
313432570,0sleep131298-21sshd23:22:551
291412570,1sleep329143-21bash00:19:203
286102560,2sleep02146599cyclictest23:22:380
284902560,0sleep228484-21sshd23:35:542
212802560,0sleep20-21swapper/222:25:172
24582550,0sleep00-21swapper/022:56:270
179642540,0sleep10-21swapper/122:44:501
326322530,1sleep032629-21sshd23:59:230
195152530,0sleep20-21swapper/222:18:282
264802520,0sleep10-21swapper/100:05:211
81952510,0sleep38185-21sshd23:27:103
69722500,0sleep20-21swapper/221:19:442
311462500,0sleep30-21swapper/322:49:293
205832500,0sleep00-21swapper/022:18:340
237252490,2sleep22147699cyclictest21:56:132
92762480,0sleep10-21swapper/122:07:281
178912470,0sleep30-21swapper/322:01:583
145102440,0sleep314508-21lspci23:04:233
262022420,2sleep02146599cyclictest00:01:580
258062400,1sleep32148599cyclictest21:24:463
161772380,2sleep12147299cyclictest23:47:501
255942360,0sleep025523-21sshd23:39:000
2135423110,6sleep00-21swapper/019:09:540
213012297,7sleep10-21swapper/119:09:141
64852230,0sleep30-21swapper/323:10:153
2107922311,7sleep30-21swapper/319:06:283
2114922211,6sleep20-21swapper/219:07:192
101262220,0sleep10-21swapper/100:24:511
272672180,1sleep127268-21grep23:19:111
95782170,1sleep2700-21gdbus21:51:402
246772170,1sleep3391rcuc/300:08:393
204432160,1sleep020438-21sshd22:41:410
118072160,0sleep20-21swapper/222:47:272
297262150,0sleep2311rcuc/223:45:512
274372150,1sleep027408-21sshd22:45:410
2146599150,1cyclictest5594-21lspci23:50:060
144442150,0sleep20-21swapper/223:10:582
277452140,0sleep10-21swapper/123:58:521
218992140,0sleep121890-21cp21:46:301
21465991413,0cyclictest15558-21lspci22:24:440
262442130,0sleep226249-21latency_hist20:39:592
260682130,0sleep00-21swapper/023:29:030
225052130,0sleep322499-21bash22:32:103
2148599130,1cyclictest32157-21lspci00:12:473
2148599130,11cyclictest1807-21sshd00:23:473
2147699130,1cyclictest818-21grep21:44:312
215912120,0sleep2321ktimersoftd/223:41:462
21485991210,1cyclictest0-21swapper/321:27:263
2148599120,11cyclictest623-21bash00:27:273
2148599120,11cyclictest0-21swapper/300:02:273
2147699120,1cyclictest27733-21lspci23:32:312
2147699120,11cyclictest14246-21sshd22:14:312
21472991211,0cyclictest0-21swapper/121:41:201
21472991210,1cyclictest7580-21sed23:40:201
21472991210,1cyclictest4304-21sshd23:13:201
21472991210,1cyclictest11484-21lspci23:07:201
2147299120,11cyclictest0-21swapper/121:30:101
21465991210,1cyclictest31015-21lspci00:09:210
200032120,0sleep10-21swapper/123:28:241
11822120,0sleep31177-21lspci21:15:533
21485991110,0cyclictest0-21swapper/323:43:063
21485991110,0cyclictest0-21swapper/323:35:163
21485991110,0cyclictest0-21swapper/322:18:263
21485991110,0cyclictest0-21swapper/321:33:363
2148599110,10cyclictest0-21swapper/321:52:463
2148599110,10cyclictest0-21swapper/321:45:263
2148599110,0cyclictest0-21swapper/323:57:373
2147699119,1cyclictest1917-21sshd00:35:012
2147699119,1cyclictest15657-21sshd00:00:512
21476991110,0cyclictest0-21swapper/221:10:112
2147699110,10cyclictest0-21swapper/223:00:112
2147699110,0cyclictest0-21swapper/221:39:312
2147299119,1cyclictest1205-21lspci22:26:301
2147299110,10cyclictest17961-21sshd00:29:301
2147299110,10cyclictest13951-21lspci22:47:401
2147299110,10cyclictest0-21swapper/121:17:191
2147299110,10cyclictest0-21swapper/120:30:291
2147299110,10cyclictest0-21swapper/100:02:401
2146599119,1cyclictest0-21swapper/023:07:260
21465991110,0cyclictest0-21swapper/023:45:160
21465991110,0cyclictest0-21swapper/021:58:260
21465991110,0cyclictest0-21swapper/021:50:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional