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2026-02-19 - 23:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Thu Feb 19, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51302910,0sleep20-21swapper/211:21:112
36332580,0sleep10-21swapper/110:53:551
258832580,0sleep30-21swapper/310:21:373
137662560,0sleep20-21swapper/212:20:192
27272540,2sleep0821699cyclictest10:49:570
78082530,0sleep20-21swapper/209:34:502
313942520,2sleep2822799cyclictest10:57:122
97172510,0sleep09646-21sshd12:27:420
129482510,0sleep20-21swapper/210:24:002
270092500,0sleep00-21swapper/011:58:460
81622490,0sleep30-21swapper/311:52:373
61192490,0sleep20-21swapper/210:13:232
134582490,0sleep00-21swapper/008:40:140
274182470,0sleep20-21swapper/209:26:562
185752470,0sleep10-21swapper/110:36:131
181982470,0sleep30-21swapper/311:11:073
285792460,1sleep228578-21sshd11:08:332
307112440,2sleep1822299cyclictest10:33:521
80152298,7sleep30-21swapper/307:08:483
79932287,7sleep10-21swapper/107:08:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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