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2026-05-21 - 14:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Thu May 21, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64172790,0sleep30-21swapper/309:55:493
137152770,2sleep01145599cyclictest11:38:280
306062680,0sleep00-21swapper/010:59:470
86472600,1sleep08624-21sshd11:23:460
193002570,1sleep119272-21sshd11:13:111
53532550,1sleep05340-21sshd09:58:360
249172540,0sleep10-21swapper/110:45:031
233582540,0sleep30-21swapper/309:46:133
320722520,0sleep10-21swapper/109:46:581
257092510,0sleep20-21swapper/210:25:212
69842500,2sleep31146199cyclictest10:23:503
53112500,0sleep35304-21sshd11:34:553
41692500,0sleep20-21swapper/210:12:232
17332500,0sleep01726-21lspci11:17:220
60972490,0sleep10-21swapper/111:32:051
234432490,0sleep3391rcuc/312:02:113
43112480,0sleep10-21swapper/112:11:541
321972480,0sleep00-21swapper/011:25:480
44342470,0sleep20-21swapper/209:36:152
31342470,0sleep00-21swapper/012:28:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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