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2025-08-21 - 22:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Thu Aug 21, 2025 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62132910,0sleep10-21swapper/110:59:151
149522800,0sleep00-21swapper/010:08:270
114012730,0sleep111402-21tty11:19:581
37442700,0sleep10-21swapper/112:20:221
134952700,0sleep00-21swapper/012:24:140
54342610,0sleep30-21swapper/310:07:233
161442560,1sleep10-21swapper/111:13:441
11632550,0sleep20-21swapper/209:29:362
117272540,0sleep30-21swapper/312:35:293
187662530,0sleep20-21swapper/210:36:102
313082520,0sleep10-21swapper/109:15:291
246122520,0sleep10-21swapper/111:28:031
206292520,0sleep20-21swapper/209:31:332
127942520,1sleep1646-21dbus-daemon12:29:591
98882510,0sleep00-21swapper/009:30:220
285692510,1sleep00-21swapper/011:53:290
19432510,1sleep21939-21bash12:34:452
128652510,0sleep20-21swapper/211:49:102
102052500,0sleep20-21swapper/212:23:562
79622490,0sleep00-21swapper/010:18:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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