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2025-09-18 - 20:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Thu Sep 18, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1513821040,0sleep015117-21sshd12:03:510
798521010,0sleep37982-21sshd11:00:493
174872980,1sleep217488-21bash09:55:122
59302720,0sleep10-21swapper/109:57:151
313072680,0sleep00-21swapper/011:46:440
14082660,0sleep00-21swapper/010:03:270
27172580,0sleep20-21swapper/212:31:042
205622580,0sleep30-21swapper/310:46:323
79832570,0sleep10-21swapper/110:26:471
16852570,0sleep00-21swapper/012:05:350
286682550,0sleep30-21swapper/310:12:553
145342530,0sleep30-21swapper/308:15:013
23222510,0sleep00-21swapper/012:37:390
215532510,0sleep10-21swapper/111:36:271
99482500,0sleep10-21swapper/110:54:551
60102500,0sleep30-21swapper/309:43:593
51712500,0sleep25175-21bash10:48:112
293952500,0sleep30-21swapper/311:06:023
26932500,0sleep10-21swapper/109:20:021
269282500,0sleep20-21swapper/212:27:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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