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2025-05-03 - 01:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Fri May 02, 2025 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
115922960,0sleep111478-21sshd11:58:491
178292950,1sleep317824-21lspci11:02:233
90502930,0sleep00-21swapper/009:56:470
255332830,0sleep325534-21sshd12:05:353
285532630,1sleep20-21swapper/209:55:252
200652610,1sleep020054-21sshd09:51:020
53282570,0sleep20-21swapper/212:20:562
99182540,0sleep30-21swapper/310:48:013
9212540,0sleep10-21swapper/111:17:391
9212540,0sleep10-21swapper/111:17:381
29012540,0sleep10-21swapper/110:09:571
267372540,1sleep026728-21lspci11:10:120
213302540,0sleep30-21swapper/309:47:573
107562530,0sleep30-21swapper/311:40:443
171792520,0sleep30-21swapper/311:05:383
70262510,0sleep30-21swapper/311:15:013
224872510,1sleep122482-21lspci10:18:461
200762510,1sleep320075-21sshd10:05:033
141182510,0sleep10-21swapper/110:14:391
87682500,0sleep10-21swapper/111:43:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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