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2025-06-28 - 22:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Sat Jun 28, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
712921050,1sleep0880499cyclictest11:24:420
3209921000,0sleep00-21swapper/011:33:580
1060221000,0sleep00-21swapper/010:25:050
309632990,2sleep3882199cyclictest12:02:053
43632900,0sleep34236-21sshd11:27:453
246932770,1sleep3401ktimersoftd/311:33:103
269652760,0sleep30-21swapper/311:20:163
237882660,0sleep10-21swapper/109:59:151
294752610,0sleep10-21swapper/109:53:071
172692600,0sleep20-21swapper/211:19:192
70202560,1sleep27018-21sshd11:51:152
228072550,0sleep00-21swapper/012:29:510
60082540,0sleep10-21swapper/109:47:301
68092530,1sleep11-21systemd11:37:521
139952520,0sleep10-21swapper/110:59:111
44332510,0sleep00-21swapper/010:58:070
250732510,0sleep20-21swapper/212:38:342
232542510,1sleep21-21systemd12:07:052
231922510,0sleep10-21swapper/110:36:241
86132500,0sleep0111rcuc/009:38:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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