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2025-12-21 - 00:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Sat Dec 20, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2027821030,0sleep20-21swapper/211:09:422
261732900,0sleep10-21swapper/110:48:391
195412830,1sleep319539-21lspci10:21:043
30432630,1sleep019295-1kworker/0:1H12:23:450
326812580,0sleep30-21swapper/309:55:133
65462540,0sleep0111rcuc/012:26:420
252692540,0sleep20-21swapper/212:25:332
234922540,1sleep10-21swapper/110:59:121
212882540,0sleep30-21swapper/311:52:523
134252540,0sleep2311rcuc/210:52:552
285802530,0sleep10-21swapper/109:51:181
204302510,0sleep10-21swapper/110:23:551
196632510,1sleep319657-21bash11:01:303
69632490,0sleep20-21swapper/209:22:402
32682490,0sleep20-21swapper/210:30:292
272812490,1sleep227275-21sshd10:45:582
107382490,1sleep010697-21sshd10:36:310
64692480,0sleep00-21swapper/011:59:460
63852480,1sleep11073-21nfsd10:28:071
53032470,0sleep20-21swapper/211:40:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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