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2025-11-05 - 19:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Wed Nov 05, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2600621100,1sleep026005-21sshd09:12:560
276812920,0sleep0101ktimersoftd/012:39:170
288332910,0sleep128834-21sshd10:41:521
237542750,0sleep00-21swapper/009:43:080
179812740,0sleep317920-21sshd10:04:493
202982700,4sleep10-21swapper/111:41:161
26162690,0sleep30-21swapper/310:39:053
46492650,0sleep10-21swapper/110:10:321
68032630,1sleep36801-21lspci12:15:303
297042620,0sleep20-21swapper/209:13:222
27142600,0sleep30-21swapper/309:44:233
168132600,0sleep30-21swapper/311:44:173
49652580,0sleep30-21swapper/310:46:513
39242580,0sleep20-21swapper/210:06:402
215472570,0sleep20-21swapper/209:20:062
53372560,0sleep30-21swapper/312:02:283
120512560,0sleep30-21swapper/310:43:383
42302550,0sleep10-21swapper/110:39:161
190412540,0sleep00-21swapper/009:23:240
160332540,0sleep00-21swapper/011:20:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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