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2025-07-16 - 01:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Wed Jul 16, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114262920,1sleep3651099cyclictest23:40:383
124012800,1sleep212405-21switchtime22:55:222
112792740,2sleep2650099cyclictest23:46:402
62052570,1sleep3391rcuc/300:26:283
185052550,0sleep20-21swapper/222:16:252
256232540,0sleep10-21swapper/123:51:011
97872530,0sleep00-21swapper/021:26:570
310872530,0sleep20-21swapper/222:54:102
281262530,0sleep0111rcuc/023:36:090
205702520,0sleep00-21swapper/021:30:570
174932520,0sleep1231rcuc/100:05:231
73282510,1sleep10-21swapper/121:11:081
73282510,1sleep10-21swapper/121:11:071
270862500,0sleep30-21swapper/321:08:533
190222500,0sleep00-21swapper/022:43:550
190222500,0sleep00-21swapper/022:43:550
182702500,1sleep018261-21lspci23:44:230
81802490,0sleep20-21swapper/200:36:272
48222490,0sleep20-21swapper/200:19:342
308602490,0sleep10-21swapper/122:17:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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