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2025-11-02 - 12:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Sun Nov 02, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
194032980,2sleep2266199cyclictest21:48:352
127162980,0sleep012715-21sshd22:45:430
190752940,0sleep319076-21sshd22:36:463
225662900,0sleep10-21swapper/122:24:181
43012790,0sleep20-21swapper/223:45:452
186652730,0sleep00-21swapper/000:16:480
324352680,0sleep00-21swapper/022:34:580
323142600,0sleep10-21swapper/123:48:361
151522600,0sleep10-21swapper/122:04:201
314922590,0sleep30-21swapper/323:03:423
128252580,0sleep00-21swapper/021:51:040
326672570,1sleep232584-21sshd22:47:462
41792560,0sleep30-21swapper/322:41:423
294942560,0sleep20-21swapper/223:19:352
237892560,0sleep00-21swapper/021:32:540
164272560,0sleep016426-21bash23:11:470
156982560,0sleep215647-21sshd23:24:342
53382550,0sleep10-21swapper/121:34:191
243222550,0sleep30-21swapper/322:46:553
119932550,1sleep00-21swapper/022:13:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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