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2026-04-01 - 16:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Wed Apr 01, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69372720,0sleep00-21swapper/009:52:210
65992600,0sleep1231rcuc/110:44:331
182752560,1sleep2674-21dbus-daemon09:42:222
81532550,0sleep10-21swapper/111:12:091
236722550,1sleep223673-21bash10:01:572
104092550,0sleep20-21swapper/209:52:382
298352540,0sleep00-21swapper/012:06:150
54802530,1sleep35481-21sshd12:23:283
225492530,0sleep00-21swapper/011:27:100
256352520,0sleep20-21swapper/210:18:342
230472520,1sleep023045-21sshd12:16:400
94592510,0sleep30-21swapper/309:17:563
202562510,0sleep20-21swapper/210:53:552
116662510,0sleep20-21swapper/211:04:132
102522510,0sleep00-21swapper/010:55:460
56152500,0sleep00-21swapper/009:38:350
45592500,1sleep125-21ksoftirqd/110:16:451
294762500,0sleep30-21swapper/311:19:323
23932490,0sleep10-21swapper/112:37:161
156002490,0sleep10-21swapper/111:40:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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