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2026-03-15 - 12:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Sun Mar 15, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
176782840,0sleep117679-21sshd22:40:301
198112610,1sleep3649-21polkitd21:33:323
48432600,0sleep00-21swapper/000:24:030
197362550,0sleep20-21swapper/223:13:442
127422550,0sleep20-21swapper/222:48:242
64072540,0sleep20-21swapper/222:36:512
231432540,1sleep023135-21sshd23:41:290
199282520,0sleep10-21swapper/123:08:141
170292520,1sleep233-21ksoftirqd/223:07:592
26022510,0sleep00-21swapper/021:59:240
30482500,0sleep33032-21sshd21:59:273
263802500,0sleep10-21swapper/123:50:031
219622500,0sleep00-21swapper/022:43:420
43722490,0sleep04367-21bash22:20:150
299652490,0sleep30-21swapper/322:22:263
157032490,0sleep20-21swapper/222:00:422
244142480,0sleep024406-21bash00:14:430
232622480,0sleep20-21swapper/221:54:412
181832480,0sleep30-21swapper/321:47:093
79282470,0sleep10-21swapper/122:13:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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