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2026-08-25 - 08:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack2slot6.osadl.org (updated Tue Aug 25, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
796996411cyclictest0-21swapper16:03:440
796996310cyclictest0-21swapper15:16:180
796996011cyclictest0-21swapper16:21:010
796995911cyclictest0-21swapper16:33:350
796995910cyclictest3422-21aten2.4_r2power17:37:460
796995910cyclictest0-21swapper17:43:090
796995910cyclictest0-21swapper15:09:560
796995811cyclictest0-21swapper16:08:410
796995810cyclictest0-21swapper14:38:500
796995711cyclictest0-21swapper17:04:090
796995711cyclictest0-21swapper15:35:120
796995711cyclictest0-21swapper14:35:330
796995711cyclictest0-21swapper14:23:190
796995710cyclictest0-21swapper16:50:150
796995710cyclictest0-21swapper16:28:500
796995710cyclictest0-21swapper15:37:460
79699569cyclictest0-21swapper15:04:030
79699569cyclictest0-21swapper14:52:380
796995611cyclictest0-21swapper17:15:240
796995611cyclictest0-21swapper16:15:260
796995610cyclictest0-21swapper17:24:360
796995610cyclictest0-21swapper15:59:080
796995610cyclictest0-21swapper15:27:460
796995610cyclictest0-21swapper14:20:210
79699559cyclictest0-21swapper15:18:550
796995511cyclictest0-21swapper15:47:520
796995510cyclictest0-21swapper17:08:350
796995510cyclictest0-21swapper16:23:590
796995510cyclictest0-21swapper14:54:160
796995510cyclictest0-21swapper14:47:090
79699549cyclictest75150irq/9-eth217:27:440
79699548cyclictest0-21swapper16:38:240
796995411cyclictest0-21swapper16:58:220
796995411cyclictest0-21swapper14:59:360
796995410cyclictest3846-21kworker/0:214:28:050
796995410cyclictest0-21swapper17:18:260
796995410cyclictest0-21swapper15:53:340
796995410cyclictest0-21swapper15:44:040
79699539cyclictest0-21swapper15:25:260
796995310cyclictest0-21swapper16:53:180
796995310cyclictest0-21swapper16:42:560
796995210cyclictest0-21swapper17:33:050
31520ksoftirqd/03509-21ls12:23:120
796995010cyclictest32701-21ls13:38:070
79699499cyclictest3685-21latency_hist13:47:500
79699479cyclictest0-21swapper12:19:430
79699478cyclictest0-21swapper12:28:270
79699459cyclictest0-21swapper14:08:530
796994510cyclictest0-21swapper14:03:480
79699449cyclictest0-21swapper13:06:230
796994410cyclictest0-21swapper12:36:480
79699439cyclictest0-21swapper13:31:380
79699439cyclictest0-21swapper13:18:330
79699439cyclictest0-21swapper12:53:280
79699438cyclictest0-21swapper14:13:170
79699438cyclictest0-21swapper12:41:110
796994310cyclictest0-21swapper13:17:250
79699429cyclictest0-21swapper13:57:240
79699429cyclictest0-21swapper13:26:160
79699429cyclictest0-21swapper12:52:340
79699419cyclictest0-21swapper13:35:040
79699419cyclictest0-21swapper13:11:350
796994020cyclictest788-21cyclictest12:58:080
796993712cyclictest11293-21ls12:43:100
796993711cyclictest8568-21ls13:58:100
796993512cyclictest4673-21ls13:48:100
796992810cyclictest803-21latency_hist12:17:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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