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2026-02-18 - 09:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack2slot6.osadl.org (updated Wed Feb 18, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14727995433cyclictest8863-21kworker/0:022:33:020
14727994929cyclictest0-21swapper19:33:280
14727994915cyclictest8863-21kworker/0:020:51:570
14727994915cyclictest8863-21kworker/0:020:18:160
14727994914cyclictest8863-21kworker/0:021:53:350
14727994830cyclictest0-21swapper20:22:470
14727994829cyclictest0-21swapper20:56:250
14727994827cyclictest0-21swapper20:26:190
14727994827cyclictest0-21swapper19:52:080
14727994824cyclictest0-21swapper21:01:410
14727994817cyclictest8863-21kworker/0:021:07:360
14727994728cyclictest27025-21ls21:41:190
14727994725cyclictest0-21swapper20:03:410
14727994723cyclictest0-21swapper19:37:200
14727994714cyclictest8863-21kworker/0:022:41:030
14727994714cyclictest18024-21kworker/0:119:42:210
14727994626cyclictest0-21swapper21:34:010
14727994621cyclictest0-21swapper19:26:270
14727994620cyclictest14718-21cyclictest21:24:480
14727994617cyclictest75150irq/9-eth221:16:140
14727994616cyclictest18024-21kworker/0:119:58:280
14727994615cyclictest8863-21kworker/0:020:38:350
14727994614cyclictest8863-21kworker/0:022:03:040
14727994613cyclictest8863-21kworker/0:021:49:590
14727994527cyclictest0-21swapper20:06:220
14727994526cyclictest75150irq/9-eth219:50:180
14727994526cyclictest0-21swapper21:12:520
14727994525cyclictest0-21swapper20:32:480
14727994518cyclictest0-21swapper19:25:380
14727994516cyclictest8863-21kworker/0:022:38:440
14727994515cyclictest8863-21kworker/0:022:24:360
14727994515cyclictest8863-21kworker/0:022:06:280
14727994514cyclictest8863-21kworker/0:022:46:500
14727994512cyclictest8863-21kworker/0:022:13:140
14727994512cyclictest8863-21kworker/0:021:57:310
14727994512cyclictest8863-21kworker/0:021:40:060
14727994427cyclictest0-21swapper20:49:160
14727994415cyclictest8863-21kworker/0:022:26:350
14727994414cyclictest8863-21kworker/0:022:17:460
14727994414cyclictest8863-21kworker/0:020:13:590
14727994413cyclictest8863-21kworker/0:020:43:320
14727994310cyclictest8863-21kworker/0:021:26:270
14727993821cyclictest0-21swapper18:02:020
14727993610cyclictest0-21swapper17:54:190
14727993519cyclictest0-21swapper17:36:440
14727993510cyclictest29007-21ls17:56:340
14727993510cyclictest23475-21sensors17:41:400
1472799349cyclictest0-21swapper17:32:210
14727993421cyclictest0-21swapper19:06:420
1472799339cyclictest0-21swapper18:55:030
1472799339cyclictest0-21swapper18:42:470
1472799339cyclictest0-21swapper17:30:140
14727993323cyclictest0-21swapper18:35:460
14727993310cyclictest26245-21taskset17:50:260
14727993310cyclictest15634-21munin-node18:46:260
1472799329cyclictest0-21swapper19:01:270
14727993223cyclictest0-21swapper19:19:110
14727993223cyclictest0-21swapper19:15:390
14727993223cyclictest0-21swapper18:37:450
14727993223cyclictest0-21swapper18:27:100
14727993223cyclictest0-21swapper18:22:220
14727993223cyclictest0-21swapper18:13:300
14727993223cyclictest0-21swapper18:06:350
14727993223cyclictest0-21swapper17:23:440
14727993220cyclictest75150irq/9-eth218:57:310
14727993210cyclictest0-21swapper18:19:290
1472799239cyclictest14746-21latency_hist17:21:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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