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2026-01-29 - 03:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Thu Jan 29, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311500ksoftirqd/031748-21threads21:23:430
32160995030cyclictest0-21swapper21:00:360
32160994926cyclictest0-21swapper20:38:150
32160994921cyclictest1256-21yum20:13:500
32160994916cyclictest11274-21kworker/0:222:54:270
32160994915cyclictest27042-21kworker/0:220:45:460
32160994813cyclictest19366-21kworker/0:120:42:190
32160994732cyclictest0-21swapper23:03:430
32160994729cyclictest0-21swapper21:05:040
32160994728cyclictest0-21swapper21:38:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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