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2026-01-31 - 21:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Sat Jan 31, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19387995328cyclictest0-21swapper09:48:210
19387994924cyclictest7467-21kworker/0:008:30:390
19387994924cyclictest0-21swapper09:02:340
19387994829cyclictest0-21swapper08:19:530
19387994828cyclictest0-21swapper10:23:060
19387994815cyclictest7467-21kworker/0:009:59:360
19387994815cyclictest17889-21kworker/0:110:53:570
19387994728cyclictest0-21swapper10:39:570
19387994727cyclictest0-21swapper10:17:450
19387994727cyclictest0-21swapper07:55:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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