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2026-01-16 - 11:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Fri Jan 16, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12073995227cyclictest0-21swapper23:11:520
1207399519cyclictest0-21swapper21:55:100
12073995026cyclictest599-21kworker/0:020:28:080
12073995015cyclictest599-21kworker/0:020:31:270
12073994926cyclictest0-21swapper20:46:150
12073994914cyclictest23666-21kworker/0:123:42:380
12073994815cyclictest7673-21kworker/0:121:38:420
12073994728cyclictest0-21swapper22:22:030
12073994727cyclictest0-21swapper23:14:470
12073994727cyclictest0-21swapper20:15:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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