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2026-01-14 - 15:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Wed Jan 14, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311530ksoftirqd/018144-21ps11:21:590
31124995525cyclictest0-21swapper11:12:500
31124995333cyclictest0-21swapper08:55:080
31124995327cyclictest13861-21kworker/0:208:18:010
31124995326cyclictest27502-21kworker/0:111:07:500
31124995326cyclictest12189-21kworker/0:109:33:100
31124995239cyclictest12189-21kworker/0:109:15:270
31124995228cyclictest75150irq/9-eth211:18:250
31124995225cyclictest24052-21kworker/0:210:36:480
31124995225cyclictest12189-21kworker/0:110:01:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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