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2026-01-15 - 06:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Thu Jan 15, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13029995328cyclictest14274-21kworker/0:021:01:420
13029995228cyclictest0-21swapper22:40:420
13029994915cyclictest5191-21kworker/0:222:04:030
13029994830cyclictest0-21swapper22:25:300
13029994830cyclictest0-21swapper20:48:060
13029994829cyclictest28364-21missed_timers23:16:090
13029994824cyclictest5670-21kworker/0:123:37:000
13029994814cyclictest5191-21kworker/0:222:31:070
13029994724cyclictest0-21swapper22:30:430
13029994715cyclictest14274-21kworker/0:020:28:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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