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2026-01-30 - 05:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Fri Jan 30, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311610ksoftirqd/06405-21threads20:12:120
4959996511cyclictest0-21swapper23:16:100
4959996310cyclictest0-21swapper20:33:280
495999629cyclictest0-21swapper21:02:140
4959996011cyclictest25167-21timerandwakeup19:57:140
495999599cyclictest0-21swapper22:13:070
4959995912cyclictest0-21swapper22:30:260
4959995910cyclictest0-21swapper23:21:160
4959995812cyclictest1620-21kworker/0:021:54:090
4959995812cyclictest0-21swapper22:50:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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