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2026-01-18 - 21:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Sun Jan 18, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17576995425cyclictest24842-21kworker/0:108:31:140
17576995323cyclictest22865-21kworker/0:010:36:240
17576995227cyclictest24842-21kworker/0:108:14:000
17576995226cyclictest22865-21kworker/0:011:39:200
17576995223cyclictest22865-21kworker/0:010:30:550
17576995223cyclictest0-21swapper10:16:310
17576995124cyclictest24842-21kworker/0:108:44:540
17576995025cyclictest17335-21kworker/0:110:20:510
17576995025cyclictest0-21swapper10:55:170
17576995023cyclictest24842-21kworker/0:109:40:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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