You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-07 - 22:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Sat Feb 07, 2026 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14105995126cyclictest0-21swapper09:46:180
14105994915cyclictest24949-21kworker/0:010:49:590
14105994915cyclictest24949-21kworker/0:009:31:160
14105994830cyclictest0-21swapper10:24:340
14105994814cyclictest24949-21kworker/0:009:18:560
14105994734cyclictest0-21swapper10:56:580
14105994729cyclictest0-21swapper10:59:440
14105994728cyclictest0-21swapper10:43:220
14105994726cyclictest0-21swapper07:58:300
14105994715cyclictest24949-21kworker/0:010:18:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional