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2026-02-22 - 02:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Sun Feb 22, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10322995426cyclictest0-21swapper20:55:400
10322995227cyclictest0-21swapper19:29:320
10322995225cyclictest0-21swapper21:27:250
10322995225cyclictest0-21swapper20:29:370
10322995125cyclictest0-21swapper22:40:330
10322995026cyclictest0-21swapper22:09:400
10322995025cyclictest3583-21kworker/0:121:58:080
10322995025cyclictest0-21swapper19:47:260
10322995023cyclictest0-21swapper21:20:280
10322995016cyclictest3583-21kworker/0:121:16:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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