You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-14 - 02:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack2slot6.osadl.org (updated Wed Jan 14, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24215995324cyclictest22557-21ls22:22:490
24215995231cyclictest0-21swapper22:21:580
24215995125cyclictest730-21fschecks_time21:22:500
24215995024cyclictest0-21swapper22:42:100
24215994924cyclictest0-21swapper20:59:200
24215994830cyclictest0-21swapper21:03:020
24215994830cyclictest0-21swapper20:43:310
24215994827cyclictest29033-21strings21:17:540
24215994825cyclictest0-21swapper22:59:430
24215994824cyclictest25067-21kworker/0:221:50:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional