You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-06 - 02:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack2slot6.osadl.org (updated Fri Feb 06, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2675199598cyclictest0-21swapper22:15:370
2675199589cyclictest0-21swapper19:42:440
2675199579cyclictest0-21swapper22:06:360
2675199569cyclictest0-21swapper21:21:320
2675199569cyclictest0-21swapper20:10:190
26751995525cyclictest75150irq/9-eth220:58:100
2675199548cyclictest75150irq/9-eth220:40:050
2675199548cyclictest0-21swapper21:44:180
2675199539cyclictest75150irq/9-eth221:17:590
2675199538cyclictest0-21swapper22:44:120
2675199538cyclictest0-21swapper22:01:460
26751995326cyclictest198442sleep021:04:090
2675199529cyclictest75150irq/9-eth222:55:260
2675199529cyclictest75150irq/9-eth221:58:330
2675199529cyclictest0-21swapper22:50:160
2675199529cyclictest0-21swapper20:27:460
2675199529cyclictest0-21swapper19:50:340
2675199528cyclictest75150irq/9-eth222:32:210
2675199528cyclictest75150irq/9-eth221:52:150
2675199528cyclictest0-21swapper23:04:290
2675199528cyclictest0-21swapper22:51:000
2675199528cyclictest0-21swapper20:45:030
2675199528cyclictest0-21swapper20:19:580
2675199528cyclictest0-21swapper20:01:360
2675199519cyclictest75150irq/9-eth221:31:010
2675199519cyclictest0-21swapper21:10:330
2675199519cyclictest0-21swapper20:34:130
2675199519cyclictest0-21swapper19:49:550
2675199518cyclictest75150irq/9-eth220:46:200
2675199518cyclictest0-21swapper22:24:300
2675199518cyclictest0-21swapper21:29:380
2675199518cyclictest0-21swapper20:22:340
2675199509cyclictest75150irq/9-eth222:14:240
2675199508cyclictest75150irq/9-eth221:46:590
2675199508cyclictest75150irq/9-eth221:36:450
2675199508cyclictest0-21swapper22:27:440
2675199508cyclictest0-21swapper20:51:000
2675199508cyclictest0-21swapper20:13:350
2675199499cyclictest0-21swapper23:06:360
2675199499cyclictest0-21swapper22:40:170
2675199498cyclictest0-21swapper21:07:290
26751994914cyclictest4542-21kworker/0:219:55:440
2675199489cyclictest0-21swapper18:33:470
2675199469cyclictest0-21swapper18:17:210
2675199459cyclictest0-21swapper18:12:210
2675199449cyclictest0-21swapper19:03:270
2675199449cyclictest0-21swapper18:27:540
2675199439cyclictest0-21swapper19:22:340
2675199439cyclictest0-21swapper18:52:050
2675199439cyclictest0-21swapper18:38:510
2675199438cyclictest0-21swapper19:16:380
2675199438cyclictest0-21swapper19:13:250
2675199429cyclictest0-21swapper19:26:560
2675199429cyclictest0-21swapper17:46:510
26751994218cyclictest26745-21cyclictest17:50:580
2675199419cyclictest0-21swapper18:57:390
2675199419cyclictest0-21swapper18:01:070
2675199418cyclictest0-21swapper19:37:380
26751993921cyclictest26745-21cyclictest17:45:420
26751993821cyclictest4815-21ls18:05:550
26751993711cyclictest5723-21ls19:30:510
26751993613cyclictest26754-21latency_hist17:40:430
26751993611cyclictest20453-21missed_timers18:45:550
26751993611cyclictest18483-21ls18:40:540
26751993515cyclictest27790-21munin-node19:05:500
26751993511cyclictest10302-21munin-node18:20:500
26751993410cyclictest316-21munin-node17:55:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional