You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-18 - 22:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack2slot6.osadl.org (updated Wed Feb 18, 2026 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311530ksoftirqd/023291-21threads08:05:430
31303995225cyclictest0-21swapper09:13:300
31303995124cyclictest0-21swapper09:43:370
31303994915cyclictest29056-21kworker/0:207:53:340
31303994914cyclictest30390-21kworker/0:008:56:110
31303994828cyclictest0-21swapper09:22:320
31303994827cyclictest0-21swapper08:22:450
31303994731cyclictest0-21swapper10:43:420
31303994728cyclictest0-21swapper10:22:160
31303994727cyclictest0-21swapper07:46:460
31303994716cyclictest30390-21kworker/0:010:48:280
31303994715cyclictest29056-21kworker/0:208:48:190
31303994714cyclictest29056-21kworker/0:208:11:110
31303994713cyclictest29056-21kworker/0:207:56:340
31303994628cyclictest0-21swapper10:27:540
31303994626cyclictest0-21swapper09:17:330
31303994626cyclictest0-21swapper08:19:230
31303994615cyclictest30390-21kworker/0:010:13:460
31303994614cyclictest30390-21kworker/0:010:31:520
31303994614cyclictest29056-21kworker/0:207:30:560
31303994613cyclictest30390-21kworker/0:010:09:070
31303994613cyclictest30390-21kworker/0:010:04:000
31303994613cyclictest29056-21kworker/0:207:35:300
31303994528cyclictest0-21swapper09:31:570
31303994527cyclictest0-21swapper09:36:450
31303994527cyclictest0-21swapper08:50:300
31303994526cyclictest0-21swapper08:29:220
31303994524cyclictest0-21swapper09:50:150
31303994524cyclictest0-21swapper08:01:270
31303994516cyclictest29056-21kworker/0:207:22:100
31303994515cyclictest29056-21kworker/0:208:38:080
31303994515cyclictest29056-21kworker/0:208:34:060
31303994514cyclictest29056-21kworker/0:208:43:260
31303994514cyclictest29056-21kworker/0:207:44:350
31303994512cyclictest30390-21kworker/0:010:16:010
31303994512cyclictest30390-21kworker/0:009:30:080
31303994512cyclictest30390-21kworker/0:009:02:550
31303994512cyclictest29056-21kworker/0:207:25:420
31303994511cyclictest30390-21kworker/0:009:07:230
31303994415cyclictest30390-21kworker/0:010:37:030
31303994415cyclictest30390-21kworker/0:009:58:100
31303994415cyclictest30390-21kworker/0:009:47:320
31303993611cyclictest24421-21munin-node06:25:420
31303993510cyclictest26374-21munin-node06:30:450
31303993411cyclictest0-21swapper05:35:370
3130399339cyclictest0-21swapper05:49:380
3130399339cyclictest0-21swapper05:26:190
3130399338cyclictest0-21swapper06:20:410
31303993323cyclictest7352-21iostat_ios05:40:460
31303993311cyclictest2952-21munin-node05:30:440
31303993310cyclictest1436-21runrttasks06:05:410
31303993310cyclictest0-21swapper07:19:470
3130399329cyclictest0-21swapper07:15:110
3130399329cyclictest0-21swapper06:42:390
3130399329cyclictest0-21swapper06:12:000
31303993223cyclictest31294-21cyclictest06:45:470
31303993211cyclictest28322-21munin-node06:35:410
31303993210cyclictest0-21swapper05:51:360
3130399319cyclictest0-21swapper07:07:110
3130399319cyclictest0-21swapper07:00:300
3130399319cyclictest0-21swapper05:23:340
31303993120cyclictest13205-21irqstats05:55:460
31303993110cyclictest15513-21sendmail_mailst06:00:490
31303993110cyclictest0-21swapper06:59:330
31303993110cyclictest0-21swapper06:52:480
31303993110cyclictest0-21swapper06:15:390
31303992920cyclictest31340-21date05:20:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional