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2026-01-26 - 23:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack2slot6.osadl.org (updated Mon Jan 26, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17340995424cyclictest0-21swapper08:10:290
17340995423cyclictest0-21swapper09:11:170
17340995325cyclictest0-21swapper09:47:080
17340995322cyclictest0-21swapper09:53:280
17340995321cyclictest0-21swapper08:43:400
17340995224cyclictest0-21swapper09:00:410
17340995220cyclictest0-21swapper08:06:410
17340995216cyclictest26352-21kworker/0:208:17:320
17340995127cyclictest0-21swapper08:16:090
17340995122cyclictest0-21swapper09:48:000
17340995122cyclictest0-21swapper08:33:560
17340995121cyclictest0-21swapper08:49:130
17340995023cyclictest0-21swapper10:52:470
17340995022cyclictest0-21swapper11:08:140
17340995019cyclictest0-21swapper10:15:340
17340995018cyclictest0-21swapper10:39:490
17340994923cyclictest0-21swapper10:18:350
17340994922cyclictest0-21swapper09:41:280
17340994921cyclictest0-21swapper10:23:210
17340994918cyclictest0-21swapper10:09:310
17340994917cyclictest0-21swapper11:02:090
17340994823cyclictest0-21swapper10:02:530
17340994822cyclictest0-21swapper08:00:340
17340994821cyclictest0-21swapper08:37:290
17340994820cyclictest1408-21kworker/0:110:27:320
17340994819cyclictest0-21swapper11:25:270
17340994818cyclictest0-21swapper10:43:050
17340994815cyclictest23252-21kworker/0:210:49:480
17340994721cyclictest0-21swapper10:33:180
17340994719cyclictest0-21swapper11:19:430
17340994714cyclictest26482-21kworker/0:209:25:020
17340994713cyclictest26482-21kworker/0:209:18:440
17340994630cyclictest0-21swapper09:03:140
17340994626cyclictest0-21swapper09:30:100
17340994623cyclictest0-21swapper11:03:130
17340994621cyclictest0-21swapper09:58:500
17340994617cyclictest0-21swapper08:53:140
17340994615cyclictest26482-21kworker/0:209:33:460
17340994615cyclictest26482-21kworker/0:209:15:020
17340994612cyclictest17771-21kworker/0:108:30:520
17340994518cyclictest0-21swapper08:23:300
17340994513cyclictest9817-21kworker/0:111:14:010
1734099359cyclictest0-21swapper07:38:300
1734099359cyclictest0-21swapper06:56:530
1734099349cyclictest0-21swapper07:18:320
17340993412cyclictest999-21hald07:48:030
1734099339cyclictest0-21swapper07:43:470
1734099339cyclictest0-21swapper06:36:500
17340993311cyclictest0-21swapper07:33:330
1734099329cyclictest17388-21sshd05:57:460
1734099329cyclictest0-21swapper07:54:390
1734099329cyclictest0-21swapper07:23:050
1734099329cyclictest0-21swapper07:00:190
1734099329cyclictest0-21swapper06:27:460
1734099329cyclictest0-21swapper06:19:290
1734099329cyclictest0-21swapper06:09:500
17340993221cyclictest37712sleep006:43:380
17340993221cyclictest121682sleep007:06:480
17340993211cyclictest0-21swapper07:12:510
17340993211cyclictest0-21swapper06:52:070
17340993210cyclictest20209-21aten2.4_r2power07:27:430
1734099319cyclictest0-21swapper06:05:140
17340993122cyclictest17682sleep006:38:480
17340993119cyclictest75150irq/9-eth207:07:500
17340993110cyclictest0-21swapper06:13:280
17340993021cyclictest287802sleep006:26:190
75150260irq/9-eth20-21swapper05:52:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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