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2026-02-14 - 01:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Fri Feb 13, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19882996128cyclictest0-21swapper10:15:520
19882995827cyclictest0-21swapper08:17:540
19882995826cyclictest0-21swapper10:51:390
19882995826cyclictest0-21swapper10:46:020
19882995825cyclictest0-21swapper09:05:350
19882995727cyclictest0-21swapper10:06:510
19882995726cyclictest0-21swapper10:55:300
19882995725cyclictest75150irq/9-eth208:08:180
19882995724cyclictest75150irq/9-eth210:33:170
19882995629cyclictest0-21swapper09:02:030
19882995628cyclictest0-21swapper09:21:490
19882995627cyclictest0-21swapper09:33:200
19882995626cyclictest0-21swapper07:34:070
19882995625cyclictest75150irq/9-eth210:10:080
19882995527cyclictest27537-21runrttasks10:19:120
19882995527cyclictest0-21swapper09:16:290
19882995527cyclictest0-21swapper09:09:590
19882995527cyclictest0-21swapper08:51:150
19882995526cyclictest0-21swapper07:55:150
19882995525cyclictest75150irq/9-eth209:23:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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