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2026-01-21 - 00:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Tue Jan 20, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27967995213cyclictest12069-21kworker/0:210:58:090
27967994914cyclictest12069-21kworker/0:210:34:390
27967994828cyclictest0-21swapper10:46:060
27967994815cyclictest8450-21kworker/0:209:59:310
27967994814cyclictest28829-21kworker/0:208:50:260
27967994728cyclictest75150irq/9-eth211:10:080
27967994716cyclictest15600-21kworker/0:008:12:470
27967994715cyclictest4831-21kworker/0:009:40:430
27967994715cyclictest28829-21kworker/0:209:03:080
27967994715cyclictest12069-21kworker/0:211:24:550
27967994715cyclictest12069-21kworker/0:210:47:270
27967994714cyclictest28829-21kworker/0:208:37:300
27967994713cyclictest18061-21kworker/0:010:16:500
27967994712cyclictest12069-21kworker/0:211:17:170
27967994629cyclictest0-21swapper09:33:510
27967994628cyclictest0-21swapper10:27:330
27967994626cyclictest0-21swapper10:17:070
27967994623cyclictest0-21swapper08:44:470
27967994615cyclictest4831-21kworker/0:009:20:210
27967994615cyclictest12069-21kworker/0:211:36:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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