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2026-01-24 - 00:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Fri Jan 23, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32123996613cyclictest0-21swapper11:19:180
32123996316cyclictest0-21swapper11:08:190
32123996315cyclictest9113-21kworker/0:010:57:420
32123996315cyclictest9113-21kworker/0:009:32:300
32123996315cyclictest6856-21kworker/0:008:24:060
32123996314cyclictest0-21swapper11:04:150
3212399629cyclictest0-21swapper11:16:100
32123996115cyclictest9113-21kworker/0:010:38:210
32123996115cyclictest9113-21kworker/0:009:49:130
32123996114cyclictest9113-21kworker/0:009:58:410
32123996114cyclictest10874-21kworker/0:209:01:460
32123996114cyclictest0-21swapper08:17:530
32123996113cyclictest9113-21kworker/0:009:44:550
32123996110cyclictest0-21swapper08:38:200
32123996015cyclictest9113-21kworker/0:011:25:090
32123996015cyclictest9113-21kworker/0:010:52:570
32123996015cyclictest9113-21kworker/0:009:30:140
32123996015cyclictest6856-21kworker/0:008:31:090
32123996015cyclictest10874-21kworker/0:208:46:270
32123996013cyclictest9113-21kworker/0:010:12:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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