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2026-02-24 - 01:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Tue Feb 24, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29413995323cyclictest0-21swapper22:27:080
29413995124cyclictest0-21swapper20:53:300
29413995027cyclictest9259-21kworker/0:220:21:480
29413995026cyclictest0-21swapper21:57:060
29413994926cyclictest13084-21taskset21:00:000
29413994921cyclictest0-21swapper20:15:300
29413994915cyclictest9259-21kworker/0:221:09:290
29413994914cyclictest9259-21kworker/0:219:30:190
29413994821cyclictest9259-21kworker/0:219:24:210
29413994819cyclictest0-21swapper19:17:550
29413994815cyclictest9259-21kworker/0:220:39:250
29413994815cyclictest9259-21kworker/0:220:00:570
29413994814cyclictest9259-21kworker/0:221:02:330
29413994725cyclictest0-21swapper19:34:330
29413994722cyclictest27161-21kworker/0:122:12:510
29413994716cyclictest9259-21kworker/0:219:43:010
29413994714cyclictest9259-21kworker/0:221:32:110
29413994713cyclictest9259-21kworker/0:220:36:010
29413994713cyclictest27161-21kworker/0:122:34:260
29413994627cyclictest0-21swapper21:36:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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