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2026-02-25 - 03:32
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Wed Feb 25, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32257995123cyclictest0-21swapper20:35:380
32257995122cyclictest0-21swapper22:04:040
32257994927cyclictest0-21swapper20:44:280
32257994915cyclictest21933-21kworker/0:122:09:150
32257994814cyclictest29087-21kworker/0:220:58:490
32257994813cyclictest29087-21kworker/0:220:46:100
32257994717cyclictest21933-21kworker/0:122:22:390
32257994716cyclictest11122-21kworker/0:119:49:200
32257994715cyclictest7008-21kworker/0:219:14:560
32257994714cyclictest21933-21kworker/0:121:19:580
32257994714cyclictest11122-21kworker/0:120:10:350
32257994629cyclictest0-21swapper20:25:460
32257994627cyclictest1948-21missed_timers22:29:590
32257994627cyclictest0-21swapper21:51:010
32257994627cyclictest0-21swapper19:39:480
32257994627cyclictest0-21swapper19:28:050
32257994626cyclictest8067-21nfs4_client21:25:030
32257994626cyclictest0-21swapper22:26:110
32257994616cyclictest21933-21kworker/0:121:45:340
32257994615cyclictest671-21kworker/0:019:30:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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