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2026-01-31 - 00:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Fri Jan 30, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28126995024cyclictest0-21swapper10:02:370
28126994924cyclictest0-21swapper09:36:340
28126994837cyclictest75150irq/9-eth208:33:100
28126994824cyclictest0-21swapper09:10:190
28126994731cyclictest0-21swapper09:18:340
28126994725cyclictest0-21swapper10:44:020
28126994722cyclictest75150irq/9-eth209:48:150
28126994720cyclictest75150irq/9-eth209:33:330
28126994716cyclictest30424-21kworker/0:209:04:430
28126994714cyclictest18326-21kworker/0:110:08:520
28126994714cyclictest18326-21kworker/0:109:21:500
28126994713cyclictest21802-21kworker/0:211:16:410
28126994713cyclictest18326-21kworker/0:110:56:210
28126994713cyclictest18326-21kworker/0:110:40:170
28126994629cyclictest0-21swapper08:47:130
28126994628cyclictest0-21swapper10:49:360
28126994626cyclictest12627-21runrttasks08:28:530
28126994626cyclictest0-21swapper09:56:490
28126994615cyclictest30424-21kworker/0:208:08:410
28126994614cyclictest30424-21kworker/0:208:51:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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