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2026-01-13 - 00:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Mon Jan 12, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311590ksoftirqd/027657-21threads08:35:250
30744995428cyclictest17974-21sort08:25:200
30744995030cyclictest30059-21runrttasks09:14:450
30744995028cyclictest0-21swapper10:19:350
30744995015cyclictest2152-21kworker/0:209:58:410
30744995014cyclictest2152-21kworker/0:210:22:010
30744994926cyclictest7472-21kworker/0:109:41:060
30744994924cyclictest75150irq/9-eth209:05:210
30744994923cyclictest75150irq/9-eth208:45:190
30744994914cyclictest2152-21kworker/0:211:20:140
30744994822cyclictest24500-21unixbench_singl10:55:170
30744994816cyclictest13157-21kworker/0:108:22:130
30744994733cyclictest0-21swapper10:25:120
30744994717cyclictest75150irq/9-eth210:12:580
30744994716cyclictest2152-21kworker/0:210:35:220
30744994714cyclictest7472-21kworker/0:109:46:400
30744994714cyclictest2152-21kworker/0:211:04:540
30744994714cyclictest2152-21kworker/0:210:30:230
30744994713cyclictest2152-21kworker/0:210:07:290
30744994627cyclictest0-21swapper11:15:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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