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2026-01-15 - 21:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Thu Jan 15, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17552995124cyclictest22762-21kworker/0:109:48:010
17552995121cyclictest75150irq/9-eth209:32:120
17552995025cyclictest0-21swapper10:02:300
17552994921cyclictest0-21swapper10:10:340
17552994829cyclictest0-21swapper10:23:090
17552994823cyclictest22762-21kworker/0:109:29:370
17552994816cyclictest12918-21kworker/0:011:01:550
17552994814cyclictest22762-21kworker/0:109:11:100
17552994813cyclictest22762-21kworker/0:108:24:070
17552994730cyclictest0-21swapper08:30:050
17552994717cyclictest0-21swapper10:42:480
17552994714cyclictest22762-21kworker/0:109:53:590
17552994626cyclictest0-21swapper11:09:260
17552994620cyclictest75150irq/9-eth210:35:350
17552994619cyclictest0-21swapper08:38:000
17552994616cyclictest22762-21kworker/0:109:22:490
17552994615cyclictest5378-21kworker/0:111:27:310
17552994615cyclictest25964-21kworker/0:010:17:420
17552994615cyclictest22762-21kworker/0:108:41:330
17552994615cyclictest22762-21kworker/0:108:16:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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