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2026-02-21 - 01:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Sat Feb 21, 2026 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31760ksoftirqd/0718-21threads22:01:310
30283995125cyclictest0-21swapper20:19:030
30283995024cyclictest0-21swapper21:18:500
30283994930cyclictest0-21swapper22:27:580
30283994929cyclictest0-21swapper19:51:230
30283994924cyclictest0-21swapper19:42:500
30283994915cyclictest12576-21kworker/0:119:50:490
30283994824cyclictest0-21swapper21:52:110
30283994814cyclictest12576-21kworker/0:119:26:150
30283994727cyclictest12576-21kworker/0:121:07:470
30283994727cyclictest0-21swapper21:36:540
30283994727cyclictest0-21swapper20:43:090
30283994726cyclictest0-21swapper21:15:300
30283994715cyclictest12576-21kworker/0:121:50:240
30283994713cyclictest12576-21kworker/0:122:17:430
30283994713cyclictest12576-21kworker/0:119:40:520
30283994630cyclictest0-21swapper22:33:370
30283994627cyclictest0-21swapper21:24:140
30283994627cyclictest0-21swapper19:28:090
30283994626cyclictest12576-21kworker/0:121:58:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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