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2026-02-28 - 05:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Sat Feb 28, 2026 00:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1765995329cyclictest1956-21kworker/0:219:35:130
1765995327cyclictest0-21swapper20:53:220
1765995132cyclictest75150irq/9-eth220:32:280
1765995118cyclictest1956-21kworker/0:222:00:060
1765995032cyclictest0-21swapper21:22:240
1765994929cyclictest0-21swapper21:59:010
1765994926cyclictest0-21swapper21:37:560
1765994913cyclictest1956-21kworker/0:219:13:530
1765994815cyclictest1956-21kworker/0:221:05:150
1765994728cyclictest0-21swapper20:25:140
1765994728cyclictest0-21swapper19:55:320
1765994723cyclictest0-21swapper19:32:180
1765994719cyclictest1759-21cyclictest19:48:110
1765994716cyclictest1956-21kworker/0:221:51:250
1765994716cyclictest1956-21kworker/0:219:20:160
1765994714cyclictest1956-21kworker/0:220:42:090
1765994713cyclictest1956-21kworker/0:221:13:070
1765994713cyclictest1956-21kworker/0:220:35:570
1765994713cyclictest1956-21kworker/0:219:43:210
1765994630cyclictest0-21swapper21:47:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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