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2026-01-16 - 23:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Fri Jan 16, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18685995226cyclictest0-21swapper10:58:420
18685995129cyclictest0-21swapper11:07:120
18685994928cyclictest0-21swapper11:24:200
18685994925cyclictest0-21swapper10:29:350
18685994915cyclictest5896-21kworker/0:110:52:290
18685994915cyclictest5896-21kworker/0:108:47:220
18685994914cyclictest5896-21kworker/0:111:22:360
18685994815cyclictest5896-21kworker/0:109:30:240
18685994813cyclictest5896-21kworker/0:110:18:480
18685994729cyclictest0-21swapper08:27:000
18685994726cyclictest0-21swapper09:45:370
18685994716cyclictest5896-21kworker/0:108:38:290
18685994714cyclictest5896-21kworker/0:111:32:480
18685994714cyclictest5896-21kworker/0:110:47:350
18685994713cyclictest5896-21kworker/0:109:36:220
18685994630cyclictest0-21swapper09:18:130
18685994629cyclictest0-21swapper09:11:090
18685994628cyclictest0-21swapper11:41:440
18685994628cyclictest0-21swapper10:27:430
18685994628cyclictest0-21swapper08:32:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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