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2026-01-20 - 00:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack2slot6.osadl.org (updated Mon Jan 19, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19555995225cyclictest0-21swapper11:18:390
19555995015cyclictest15903-21kworker/0:109:05:550
19555994915cyclictest16940-21kworker/0:211:17:140
19555994914cyclictest15903-21kworker/0:109:13:470
19555994826cyclictest0-21swapper09:41:350
19555994825cyclictest0-21swapper11:26:020
19555994823cyclictest15903-21kworker/0:110:12:510
19555994729cyclictest7684-21munin-node10:38:490
19555994728cyclictest21416-21munin-node10:53:510
19555994717cyclictest15903-21kworker/0:109:18:480
19555994714cyclictest16940-21kworker/0:211:34:310
19555994628cyclictest0-21swapper10:19:440
19555994627cyclictest0-21swapper10:44:400
19555994627cyclictest0-21swapper09:58:580
19555994625cyclictest0-21swapper11:06:420
19555994616cyclictest15903-21kworker/0:108:59:370
19555994615cyclictest28474-21kworker/0:208:12:370
19555994615cyclictest15903-21kworker/0:108:27:210
19555994614cyclictest15903-21kworker/0:109:45:260
19555994613cyclictest16940-21kworker/0:210:53:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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