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2026-01-20 - 14:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack2slot6.osadl.org (updated Tue Jan 20, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27967995213cyclictest12069-21kworker/0:210:58:090
27967994914cyclictest12069-21kworker/0:210:34:390
27967994828cyclictest0-21swapper10:46:060
27967994815cyclictest8450-21kworker/0:209:59:310
27967994814cyclictest28829-21kworker/0:208:50:260
27967994728cyclictest75150irq/9-eth211:10:080
27967994716cyclictest15600-21kworker/0:008:12:470
27967994715cyclictest4831-21kworker/0:009:40:430
27967994715cyclictest28829-21kworker/0:209:03:080
27967994715cyclictest12069-21kworker/0:211:24:550
27967994715cyclictest12069-21kworker/0:210:47:270
27967994714cyclictest28829-21kworker/0:208:37:300
27967994713cyclictest18061-21kworker/0:010:16:500
27967994712cyclictest12069-21kworker/0:211:17:170
27967994629cyclictest0-21swapper09:33:510
27967994628cyclictest0-21swapper10:27:330
27967994626cyclictest0-21swapper10:17:070
27967994623cyclictest0-21swapper08:44:470
27967994615cyclictest4831-21kworker/0:009:20:210
27967994615cyclictest12069-21kworker/0:211:36:030
27967994615cyclictest12069-21kworker/0:211:16:200
27967994614cyclictest28829-21kworker/0:208:59:030
27967994614cyclictest15600-21kworker/0:008:25:580
27967994614cyclictest15600-21kworker/0:008:08:170
27967994613cyclictest28829-21kworker/0:208:28:000
27967994613cyclictest12069-21kworker/0:210:38:550
27967994527cyclictest0-21swapper09:28:120
27967994526cyclictest0-21swapper11:27:300
27967994514cyclictest4831-21kworker/0:009:49:480
27967994514cyclictest4831-21kworker/0:009:42:440
27967994513cyclictest18061-21kworker/0:010:04:500
27967994513cyclictest15600-21kworker/0:008:19:070
27967994512cyclictest28829-21kworker/0:209:09:590
27967994512cyclictest18061-21kworker/0:010:08:030
27967994512cyclictest0-21swapper08:33:520
27967994415cyclictest12069-21kworker/0:211:03:130
27967994413cyclictest4831-21kworker/0:009:22:290
27967994412cyclictest4831-21kworker/0:009:15:060
27967994412cyclictest18061-21kworker/0:010:23:110
27967994412cyclictest12069-21kworker/0:210:55:040
27967994411cyclictest28829-21kworker/0:208:55:110
27967994314cyclictest8450-21kworker/0:209:52:250
27967993711cyclictest17187-21munin-node07:02:330
2796799369cyclictest0-21swapper07:56:160
27967993510cyclictest19135-21munin-node07:07:270
27967993410cyclictest28900-21munin-node07:32:310
2796799339cyclictest10221-21munin-node06:42:360
2796799339cyclictest10187-21ls08:07:110
2796799339cyclictest0-21swapper08:00:500
2796799339cyclictest0-21swapper07:30:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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