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2026-02-21 - 22:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 792 highest latencies:
System rack2slot6.osadl.org (updated Sat Feb 21, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13888995217cyclictest16251-21kworker/0:208:28:400
13888995027cyclictest16251-21kworker/0:208:10:440
13888995027cyclictest0-21swapper10:24:020
13888995024cyclictest0-21swapper08:51:040
13888994831cyclictest0-21swapper09:19:240
13888994826cyclictest0-21swapper09:21:210
13888994825cyclictest0-21swapper10:01:590
13888994823cyclictest16251-21kworker/0:209:50:340
13888994816cyclictest16251-21kworker/0:207:58:180
13888994816cyclictest16251-21kworker/0:207:41:480
13888994815cyclictest16251-21kworker/0:209:28:010
13888994728cyclictest0-21swapper07:25:090
13888994717cyclictest16251-21kworker/0:208:23:300
13888994716cyclictest16251-21kworker/0:207:48:360
13888994715cyclictest16251-21kworker/0:208:37:250
13888994714cyclictest16251-21kworker/0:209:49:280
13888994713cyclictest16251-21kworker/0:209:11:270
13888994713cyclictest16251-21kworker/0:208:43:100
13888994713cyclictest16251-21kworker/0:208:30:550
13888994627cyclictest0-21swapper10:11:480
13888994614cyclictest16251-21kworker/0:210:20:110
13888994614cyclictest16251-21kworker/0:208:07:100
13888994613cyclictest16251-21kworker/0:208:17:450
13888994611cyclictest16251-21kworker/0:208:59:280
13888994526cyclictest0-21swapper10:33:070
13888994525cyclictest0-21swapper10:08:290
13888994525cyclictest0-21swapper09:57:540
13888994515cyclictest16522-21kworker/0:110:40:580
13888994515cyclictest16251-21kworker/0:209:42:260
13888994514cyclictest6091-21kworker/0:107:33:520
13888994514cyclictest16522-21kworker/0:110:36:470
13888994514cyclictest16251-21kworker/0:207:51:530
13888994514cyclictest0-21swapper09:09:030
13888994511cyclictest20907-21kworker/0:207:17:090
1388899449cyclictest0-21swapper09:00:470
13888994416cyclictest16251-21kworker/0:208:00:460
13888994415cyclictest16251-21kworker/0:209:30:520
13888994415cyclictest16251-21kworker/0:207:37:350
13888994413cyclictest6091-21kworker/0:107:26:040
13888994413cyclictest16251-21kworker/0:210:26:590
13888994412cyclictest16251-21kworker/0:209:36:460
13888994412cyclictest16251-21kworker/0:208:48:390
13888993610cyclictest8970-21munin-node06:25:550
1388899359cyclictest0-21swapper06:13:420
1388899359cyclictest0-21swapper05:59:570
1388899349cyclictest0-21swapper06:06:070
1388899349cyclictest0-21swapper05:19:210
13888993410cyclictest14821-21munin-node06:40:530
1388899339cyclictest0-21swapper05:49:100
13888993311cyclictest18815-21aten2.4_r2power06:50:470
13888993311cyclictest0-21swapper06:56:120
13888993310cyclictest0-21swapper06:16:070
1388899329cyclictest19812-21munin-node05:30:550
1388899329cyclictest0-21swapper07:12:230
1388899329cyclictest0-21swapper06:32:420
1388899329cyclictest0-21swapper05:37:550
13888993222cyclictest23717-21munin-node05:40:560
13888993212cyclictest17636-21sshd05:24:580
13888993211cyclictest0-21swapper05:50:570
13888993210cyclictest0-21swapper06:20:430
1388899319cyclictest0-21swapper07:02:150
1388899319cyclictest0-21swapper06:46:240
1388899319cyclictest0-21swapper06:36:120
1388899319cyclictest0-21swapper06:01:220
13888993112cyclictest24575-21munin-node07:05:470
1388899308cyclictest0-21swapper05:27:020
1248722613sleep012560-21munin-node05:11:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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