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2026-02-14 - 22:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 792 highest latencies:
System rack2slot6.osadl.org (updated Sat Feb 14, 2026 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311390ksoftirqd/016569-21ps10:06:590
18495995528cyclictest0-21swapper10:26:170
18495995427cyclictest0-21swapper09:14:140
18495995232cyclictest0-21swapper09:17:240
18495995227cyclictest75150irq/9-eth208:15:410
18495995226cyclictest0-21swapper10:54:320
18495995225cyclictest0-21swapper08:48:470
18495995026cyclictest0-21swapper08:20:130
18495995015cyclictest32215-21kworker/0:108:45:390
18495994925cyclictest0-21swapper10:20:430
18495994925cyclictest0-21swapper09:28:220
18495994924cyclictest0-21swapper07:45:570
18495994922cyclictest0-21swapper09:47:070
18495994921cyclictest0-21swapper10:27:240
18495994921cyclictest0-21swapper09:56:340
18495994915cyclictest32215-21kworker/0:109:36:140
18495994830cyclictest0-21swapper07:53:150
18495994828cyclictest0-21swapper08:57:190
18495994827cyclictest0-21swapper07:29:070
18495994825cyclictest75150irq/9-eth209:45:510
18495994824cyclictest0-21swapper10:37:240
18495994816cyclictest32215-21kworker/0:107:48:520
18495994815cyclictest32215-21kworker/0:107:57:470
18495994814cyclictest32215-21kworker/0:108:27:030
18495994813cyclictest32215-21kworker/0:108:39:120
18495994728cyclictest0-21swapper10:34:370
18495994728cyclictest0-21swapper08:01:580
18495994727cyclictest0-21swapper09:05:030
18495994724cyclictest0-21swapper10:48:420
18495994723cyclictest0-21swapper10:42:450
18495994723cyclictest0-21swapper08:53:130
18495994722cyclictest0-21swapper07:39:430
18495994721cyclictest75150irq/9-eth210:00:120
18495994716cyclictest32215-21kworker/0:109:26:070
18495994627cyclictest0-21swapper09:37:070
18495994626cyclictest0-21swapper10:15:460
18495994626cyclictest0-21swapper09:07:140
18495994625cyclictest0-21swapper08:31:480
18495994620cyclictest0-21swapper07:34:520
18495994612cyclictest32215-21kworker/0:108:08:060
18495994523cyclictest0-21swapper06:40:500
18495994514cyclictest32215-21kworker/0:110:02:160
18495994513cyclictest32215-21kworker/0:108:22:010
18495994422cyclictest0-21swapper07:18:110
18495994420cyclictest0-21swapper06:05:450
18495994321cyclictest0-21swapper07:23:470
18495994321cyclictest0-21swapper06:42:430
18495994222cyclictest0-21swapper07:08:270
18495994221cyclictest0-21swapper06:57:010
18495994221cyclictest0-21swapper06:22:060
18495994221cyclictest0-21swapper05:49:490
18495994221cyclictest0-21swapper05:27:270
18495994123cyclictest0-21swapper06:53:350
18495994031cyclictest75150irq/9-eth206:17:310
18495994023cyclictest0-21swapper06:09:110
18495994021cyclictest0-21swapper06:12:410
18495994020cyclictest0-21swapper05:59:280
18495993921cyclictest0-21swapper07:02:040
18495993920cyclictest0-21swapper06:32:070
18495993920cyclictest0-21swapper05:39:280
18495993920cyclictest0-21swapper05:33:430
18495993822cyclictest0-21swapper06:47:310
18495993822cyclictest0-21swapper05:42:110
18495993821cyclictest0-21swapper05:52:260
18495993820cyclictest0-21swapper06:27:290
18495993720cyclictest0-21swapper07:13:260
18495992713cyclictest18497-21latency_hist05:27:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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